JP2001188807A - Time fault simulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time fault simulation method by which whether or not a pertinent test pattern is provided with time fault inspection ability is verified for a time fault generated on a signal path inside a logic circuit for making signal change time fluctuate. SOLUTION: For the time fault generated on the signal path inside the logic circuit for making the signal change time fluctuate, prescribed time Δt is defined as the time fault, the signal change time on the signal path is delayed for the prescribed time Δt by the test pattern and circuit simulation is performed. Output signals from the logic circuit by the circuit simulation are compared with the output signal result of normal circuit simulation and when a difference between them is confirmed, it is defined that the time fault can be detected by the test pattern and it is defined that the time fault can not be detected by the test pattern when the difference can not be confirmed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating a time failure for investigating a time failure inspection capability using a test pattern for inspection of a semiconductor circuit or the like.

[0002]

2. Description of the Related Art Normally, a failure of a semiconductor circuit that constitutes a logic circuit or the like is caused by a defect or the like that occurs accidentally in the manufacture of the semiconductor circuit, and does not satisfy the intrinsic function of the semiconductor circuit. Point to. In order to inspect such a semiconductor circuit for a failure, a test pattern for a failure inspection is conventionally created, and as its failure inspection capability, it is necessary to check in advance whether the inspection test pattern to be used is valid in the failure inspection. There is a failure simulation.

In this fault simulation, for example, a fault circuit for simulation in which a fault is virtually generated inside a logic circuit, for example, is formed as a semiconductor circuit, and the fault circuit includes the above-described test pattern for inspection. By use, a signal change that occurs in a normal circuit due to a fault in the circuit propagates to the outside of the circuit and is executed to determine whether a fault in the circuit is detected.

When executing a fault simulation, a fault simulator is replaced with a fault model including a specific fault circuit so as to easily simulate a fault in a logic circuit. One of the fault models is a stuck-at fault. There is a model, for example, a single stuck-at fault model is assumed as a fault that is logically fixed to 1 or 0 at one point inside a logic circuit.

[0005] These fault models and fault simulation algorithms are described, for example, in "Digital Circuit Fault Diagnosis (above)" issued by Kogyo Tosho Co., Ltd.

[0006]

However, the conventional fault simulation method as described above naturally applies to a fault whose logic value is permanently fixed to 1 or 0 such as a single stuck-at fault model. The problem is that faults that occur physically and temporally inside the actual circuit cannot be dealt with because they are not only faults represented by the stuck-at fault model. I was

For example, due to a fault occurring inside a circuit,
If the time of signal transition on a predetermined signal path or a predetermined gate terminal fluctuates for a specific time, there is no effective fault simulation method for such a fault, and a fault that fluctuates the transition time of such a signal path. Does not affect the desired operation of the semiconductor circuit even if it exists, in other words, it can be ignored if there is a sufficient operation time margin as the semiconductor circuit.

However, if the required performance of the semiconductor circuit is improved with the technological progress in the semiconductor circuit and the semiconductor manufacturing process, the processing speed is increased, so that it is impossible to have a sufficient operation time margin. However, even a slight change in the signal transition time causes a problem in operation. Therefore, in the future, it is necessary to deal with a failure that temporally fluctuates the transition time of the signal path as described above, that is, a time failure. A time failure simulation for investigating the inspection capability of a time failure by a test pattern is indispensable.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. It is possible to easily determine whether or not a test pattern used in a failure test of a semiconductor circuit is effective for a time failure test. The present invention provides a time-failure simulation method capable of generating an inspection test pattern having a high test capability for a time-failure and an efficient test pattern.

[0010]

In order to solve the above-mentioned problems, a time failure simulation method according to the present invention uses a time failure when a shift of a signal transition time of a predetermined time Δt from a predetermined signal transition time occurs. Constructing a time-failure model by shifting the signal transition time by a predetermined time Δt, causing at least one or more time-failures on a predetermined signal path or a predetermined gate terminal inside the semiconductor circuit,
The difference in signal transition time between the case where the time fault exists and the case where the time fault does not exist is transmitted to the outside by a circuit model simulation using a predetermined test pattern to determine whether the time fault can be detected. Features.

As described above, it is possible to easily determine whether or not the test pattern used in the failure inspection of the semiconductor circuit is effective for the inspection for the time failure. A high and efficient test pattern for inspection can be generated.

[0012]

A time fault simulation method according to claim 1 of the present invention defines a fault that shifts the transition time of its signal level at an arbitrary point in a semiconductor circuit as a time fault, and A time failure simulation method for performing a simulation on the semiconductor circuit in order to verify a test capability of the test pattern for circuit failure inspection against the time failure, the method comprising: Displacing the transition time on the signal path or on the gate terminal by a predetermined time,
A method of causing the time failure in the semiconductor circuit and determining whether or not an influence on an output signal from the semiconductor circuit due to the displacement of the transition time is detected based on the test pattern.

According to a second aspect of the present invention, there is provided a method for simulating a time fault, wherein a time fault occurrence location is arbitrarily set for all gate terminals and all nodes in the semiconductor circuit according to the first aspect. A first step of storing the displacement time of the signal transition time at the time-failure location as time-failure list information in association with each of the all gate terminals and all the nodes, and an input to a simulation target semiconductor circuit. A second step of generating a test pattern, and at least one or more of the time-failure locations included in the time-failure list information and a displacement time of a signal transition time at the time-failure location with respect to the input test pattern. And executing the simulation on the faulty circuit model and the normal circuit model without the setting. And a fourth step of executing a process of propagating a time displacement event occurring at the gate terminal and the node having the displacement time by the input test pattern, and simulating the faulty circuit model and the normal circuit model Each propagation output result by
A fifth step of comparing at a predetermined strobe time during the simulation, and, when there is a difference in the comparison result, storing that the displacement time is detectable, and then determining the displacement time and the time failure location. A sixth step of deleting from the time failure list information, and when no difference occurs in the comparison result or when the sixth step is executed, all the entries in the time failure list information for the input test pattern are performed. A seventh step of determining whether or not an event due to the time failure location and the displacement time has been processed, and if there is an unprocessed event, executing a transition process to the third step; If it is confirmed that there is an input test pattern that does not exist and the simulation has not been executed, the input test pattern is updated to that input test pattern. , And a method and a eighth step of executing the transition process to the second step.

According to a third aspect of the present invention, in the first step of the second aspect, a time fault location is arbitrarily set for all signal paths from an input terminal to an output terminal of the semiconductor circuit. The time fault location and the displacement time of the signal transition time at the time fault location are stored as time fault list information in association with each of the signal paths.

According to a fourth aspect of the present invention, there is provided a method for simulating a time fault, wherein in the first step according to the second aspect, a signal whose level changes from "1" to "0" and "0" to "1" as a signal change. A method of storing the displacement time for displacing each of the transition times separately as the time failure list information. According to a fifth aspect of the present invention, there is provided a time fault simulation method according to the first aspect of the present invention, wherein the signal transition is from "1" to "0" and from "0" to "1".
For a signal transition time at which a level transition occurs, one common displacement time is stored as the time failure list information.

According to a sixth aspect of the present invention, there is provided a method for simulating a time fault, wherein in the first step according to the second aspect, a signal whose level shifts from "1" to "0" and "0" to "1" as a signal shift. In this method, the displacement times to be separately delayed from the transition times are stored as the time failure list information. According to a seventh aspect of the present invention, there is provided the time failure simulation method according to the first aspect, wherein the signal transition is changed from "1" to "0" and from "0" to "1".
A method is employed in which, for each signal transition time at which a level transition occurs, the separately advanced displacement time is stored as the time failure list information.

According to an eighth aspect of the present invention, there is provided a method for simulating a time fault, wherein the input test pattern is executed at a gate terminal and a node having a displacement time with respect to a signal transition time in the fourth step of the second aspect. If the time displacement event does not occur, the method shifts to the seventh step without going through the fifth step. Claim 9
The time fault simulation method according to claim 2, wherein in the third step according to claim 2, a signal transition time at which a level transition from "1" to "0" and from "0" to "1" occurs as a signal transition In a case where two or more displacement times included in the time failure list information are set, in the fourth step, during a propagation process, a time displacement event generated from a plurality of time failure locations with respect to the input test pattern has the same time in the semiconductor circuit. For the same point propagation time failure event that has propagated to the gate terminal or node at the point, at the time of occurrence, the subsequent same point propagation time failure event processing is interrupted, and the fanout of the gate terminal or node at the same point occurs. In the fifth step, all the connected signal paths and output terminals are invalidated. Without comparison processing propagation output result of Deployment, in the seventh step, and how to handle only a plurality of time failure event executing the sixth step of the process events.

According to a tenth aspect of the present invention, in the fourth step of the ninth aspect of the present invention, the semiconductor circuit is configured such that a time displacement event generated from a plurality of time fault locations with respect to the input test pattern is propagated. Of the same location propagation time fault event propagated to the same location gate terminal or node within the same location, one of the same location propagation time fault events is validated, and the other It is a method of processing as an event state in which no failure has occurred.

According to these methods, a fault model for a fault whose signal transition time fluctuates for a specific time on a predetermined signal path or a predetermined gate terminal inside a semiconductor circuit is set,
By using the test pattern for inspection, it is possible to determine whether or not a signal change caused by a circuit fault in the fault model propagates to the outside and whether a fault in the circuit is detected. Hereinafter, a time failure simulation method according to an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a flowchart showing a processing procedure in the time failure simulation method according to the present embodiment. In FIG. 1, reference numeral 101 denotes a step indicating the start of a time failure simulation; 102, a step of generating an input test pattern to be applied to a circuit model to be simulated; A step of setting a time fault for the faulty circuit model and executing a simulation; and 104, executing a simulation of the target event set in the step 103, and transmitting a signal at that time to each gate connection destination in each circuit model. The step of propagating 105 detects the propagation result of step 104 at each external terminal of the normal circuit model and the failure circuit model, and compares the detection results. Register for that event Step, 107 Step 1
The step of deleting the registered time fault from the time fault list of each gate in step 06, the step of judging the end of the time fault simulation of the circuit model for one input test pattern, the step of 109 the time of the circuit model for all input test patterns The step 110 for determining the end of the failure simulation is a step indicating the end of the time failure simulation.

The specific procedure of the time failure simulation method including the above processing steps will be described below. First, in step 102, an input test pattern to be given to a circuit model to be simulated is generated. Next, in step 103, the input test pattern generated in step 102 is given to both circuit models of the normal circuit and the faulty circuit, and their simulation is executed. At this time, the target event is set in both circuit models, and at least one or more time faults are selected and set from the time fault list of each gate for the fault circuit model. As a result, the event is propagated from the input terminal of the circuit model to each of the connected gates.

By executing the simulation as described above, in step 104, the target event set for both circuit models in step 103 is propagated to each gate connection destination in the circuit model. Thus, when a time fault exists in the gate of the propagated event destination in the fault circuit model, the time fault event is propagated to the connection destination of the gate.

In step 105, the results of the propagation output to the external terminal, which is the final gate connection, are detected for the two circuit models, and the detection results are compared between the two circuit models. In this case, what is to be compared is the result of propagation output at the external terminal to which the time failure event generated in the failure circuit model has propagated. If the comparison results are different, it is determined that the time failure set in step 103 has been detected, and the process proceeds to the next step 106. If the comparison results are equal, it is determined that the time failure has not been detected. Then, the process proceeds to Step 108.

In step 106, the time fault detected in step 105 is registered in the memory, and the propagation output of the normal circuit model is also registered as the expected value of the input test pattern. In step 107, processing is performed to search all gates and delete the time fault registered in step 106 from the time fault list of each gate.

In step 108, the end of the time fault simulation of the circuit model for one input test pattern is determined. At this time, for one input test pattern used in the time-failure simulation whose execution has been completed, it is determined whether or not all-time faults in the time-failure list have been set in the faulty circuit model and subjected to event processing. If an unprocessed event exists, the process proceeds to step 103; otherwise, the process proceeds to step 109.

In step 109, the end of the time failure simulation of the circuit model for all the input test patterns is determined. If all the test pattern inputs have not been completed, the processing shifts to step 102 to execute the above series of processing. Is repeated, and when all the test pattern inputs have been completed, the process proceeds to step 110 to end the time failure simulation.

As described above, according to the present embodiment, the shift Δtn of the signal transition time generated at each gate of the logic circuit is defined as a time fault, and a time fault list is registered. At least one or more time faults are selected and generated from the time fault list in the circuit model, a simulation is performed on the logic circuit, and a process of propagating an event based on the test pattern input in step 102 is performed. In step 105, it is determined whether or not a difference between each event change propagated to the external output of the logic circuit by the simulation of the faulty circuit model and the normal circuit model can be detected, thereby checking the time fault Δtn occurring in the logic circuit. be able to.

Therefore, it is possible to inspect and evaluate the ability of the logic circuit to detect the time failure of the corresponding test pattern.
It is possible to easily determine whether a test pattern used in a failure test of a semiconductor circuit is valid for a time failure test, and to use the test pattern to provide a high-performance and efficient test for a time failure. Test patterns can be generated.

FIG. 2 is a configuration diagram of a logic circuit showing an example of a fault circuit model used in the time fault simulation method of the present embodiment. This logic circuit 201 has a total of six circuit input terminals A to F, as shown in FIG.
And one circuit output terminal Y are provided.
Logic gates G1 to G5 are provided. In FIG. 2, a circuit input terminal A is connected to an OR gate G by a node n1.
Circuit input terminals B and C are connected to the input terminals a and b of the AND gate G1 by nodes n2 and n3.
Are connected to the input terminals a and b of the OR gate G2 by nodes n4 and n5, and the circuit input terminal F is connected to the D flip-flop G5 by a node n6.
Is connected to the clock input terminal CLK.

The output terminals y of the AND gate G1 and the OR gate G2 are connected to the input terminals a and b of the AND gate G3 by nodes n7 and n8, respectively.
Of the D flip-flop G by the node n9.
5 and the output terminal Q of the D flip-flop G5 is connected to the OR gate G4 by the node n10.
Output terminal y of the OR gate G4.
Is connected to the circuit output terminal Y by the node n11.

The D flip-flop G5 takes in the input signal to the input terminal D in synchronization with the rising edge of the input signal to the clock input terminal CLK, and outputs the value to the output terminal Q. FIG. 3 is a timing chart for explaining the operation of the logic circuit used in the time fault simulation method according to the present embodiment. Specifically, the test pattern is applied to the logic circuit 201 shown in FIG. Is applied, the circuit input signals of the circuit input terminals A to F, the failure circuit model in which a time failure occurs in the output terminal y of the AND gate G1 inside the logic circuit 201, and the normal circuit model in which the time failure does not occur 4 is a timing chart showing a relationship between an output signal from each circuit output terminal Y and an output signal from an output terminal y of an AND gate G1. Here, the logic circuit 201
As a time failure generated in the internal AND gate G1,
The case where the output terminal y of the AND gate G1 changes from “1” to “0” and the change time is delayed by the time ΔtG1y is shown.

The operation when the time failure simulation method according to the present embodiment is applied to the logic circuit 201 will be described below with reference to FIGS. First, the list of all-time faults targeted in the current time-failure simulation includes "1" for n locations including all internal nodes of the logic circuit and gate input / output pins.
Consider a delay time Δt that occurs when the signal transitions from “0” to “0” and from “0” to “1”. Accordingly, the total number of all-time faults is 2n, and in the case of the logic circuit 201 in FIG. 2, 11 internal nodes n1 to n11 and 15 input / output pins of gates G1 to G5 are provided. 52 time failures are targeted. The time fault ΔtG1y generated in the internal AND gate G1 is as follows.
One of the 52 time failures.

First, in the test pattern 1 state of FIG. 3, "1" is applied to the circuit input terminals B and C (step 102), and "1" is applied to the output terminal y of the AND gate G1.
Is output, no time failure event occurs. In this case, no difference occurs between the normal circuit model and the faulty circuit model as a result of the event propagation, "1" is output to the output terminal Y of each circuit model, and the strobe to detect the output signal is output. At time t1, which is a point, "1" is detected in both circuit models (steps 103 and 104).

Therefore, no difference in event propagation can be obtained between the two circuit models, and the time of transition from "1" to "0" generated at the output terminal y of the internal AND gate G1 in the test pattern 1 is not obtained. It can be confirmed that the failure ΔtG1y cannot be detected (step 105).
Thereafter, in the time failure simulator, except for the time failure ΔtG1y of the transition from “1” to “0” generated at the output terminal y of the internal AND gate G1, unprocessed time failures in the time failure The same processing (step 108) as described above is executed for a time failure, but for the sake of simplicity, the next test pattern input processing for handling other time failures (step 109)
Will be executed.

Therefore, "0" is applied to the circuit input terminals B and C in the state of the test pattern 2 (step 10).
2) Since the output terminal y of the AND gate G1 changes from “1” to “0”, a time failure event occurs in the logic circuit 201. In this case, there is a difference between the result of event propagation between the normal circuit model and the faulty circuit model. That is, in the normal circuit model, after the output terminal y of the AND gate G1 changes from “1” to “0”, the value is AND
At time t2rf through the gate G3, the signal is taken into the input terminal D of the flip-flop G5, and "0" is output to the output terminal Q. Input terminals a and b of OR gate G4
"0" from the circuit input terminal A and "0" from the output terminal Q of the flip-flop G5 are input to
“0” is output to the output terminal y of the R gate G4. Therefore, “0” is also output to the circuit output terminal Y (Step 103 and Step 104).

On the other hand, in the faulty circuit model, although the output terminal y of the AND gate G1 changes from "1" to "0",
Since a delay of time ΔtG1y occurs as compared with the case of the normal circuit model, the output terminal y is taken into the input terminal D of the flip-flop G5 through the AND gate G3 while maintaining the state of “1” at the time t2rf. “1” is output to the output terminal Q. Input terminal b of OR gate G4
"1" is input from the output terminal Q of the flip-flop G5, and "1" is output to its output terminal y. Therefore, "1" is output to the circuit output terminal Y (Step 103 and Step 104).

Accordingly, at time t2, which is the strobe point in this case, "0" is detected from the output terminal Y in the normal circuit model and "1" is detected in the faulty circuit model, and the normal circuit model and the faulty circuit are detected. Event propagation differences between models can be obtained. Therefore,
By detecting such a difference in event propagation, in test pattern 2, a time failure ΔtG1 of transition from “1” to “0” generated at output terminal y of internal AND gate G1.
y can be confirmed to be detectable (step 10
5).

The time fault that can be detected in this manner (here, a time fault ΔtG1y of a transition from “1” to “0” occurring at the output terminal y of the AND gate G1) is stored as detected time fault data. The test pattern, the fault event caused by the test pattern, and the value of the output terminal Y of the normal circuit model are registered as expected values (step 106).

Since the time fault ΔtG1y has already been detected at this point, it is deleted from the time fault list to be subjected to the time fault simulation (step 107). Thereafter, the time failure simulator performs the same processing (step 10) on the unprocessed time failures in the time failure list other than the time failure ΔtG1y.
8) is performed, and when there is no unprocessed time failure, the next test pattern 3 is input (step 109), and the same processing as before is performed.

In the above embodiment, a delay time of Δt is set as a time failure. However, if a shortened time in which the transition time becomes earlier by Δt with respect to the time at which the internal signal transitions is set, the signal becomes longer. It is possible to simulate a time failure that causes a fast transition. Further, in the above embodiment, two signal transitions from “1” to “0” and “0” to “1” are set. For example, when a signal delay or shortening at the same time Δt with respect to a certain time is observed, these may be treated as one time failure. In this case, the total number of faults at all times is n for all internal locations n of the logic circuit.
And the event processing time is reduced.

In the above-described embodiment, the fault location is set at n locations including all the internal nodes of the logic circuit and the gate input / output pins. However, the failure path is changed to a signal path from the circuit input to the circuit output. It is possible to As an example, in the case of the logic circuit 201 in FIG. 2, the circuit input terminal A → the node n1 → the input terminal a of the OR gate G4 → O
Similarly, a signal path from the output terminal y of the R gate G4 to the circuit output terminal Y, a signal path from the circuit input terminal B to the circuit output terminal Y, and a signal path from the circuit input terminal C to the circuit output terminal Y , A signal path from the circuit input terminal D to the circuit output terminal Y, a signal path from the circuit input terminal E to the circuit output terminal Y, and a signal path from the circuit input terminal F to the circuit output terminal Y. The path is set as the time fault location.

In the event processing process of the above-described embodiment, no time-failure event occurs at the output terminal y of the internal AND gate G1 when the test pattern 1 is input. When it is recognized that no fault event has occurred, the subsequent event propagation processing (step 104) and the comparison of the output values at the output terminal Y of the normal circuit model and the fault circuit model (step 10)
5) may be omitted. This is because when a time failure event does not occur, the difference between the output values of the normal circuit model and the failure circuit model cannot be detected, that is, it is clear that the time failure cannot be detected.

In the event processing process of the above embodiment, a plurality of time faults to be processed may be selected and set from the time fault list. In order to clearly show the time fault detection situation, it is necessary to prevent the effects of the plurality of time faults from affecting each other and being output outside the logic circuit. Therefore, when each time fault event for a plurality of set time faults propagates to the same circuit internal node or gate output during the propagation process, the time fault event is interrupted, and the fan-out of the internal node or gate output occurs. All connected signal paths and circuit outputs are invalidated, and comparison of simulation propagation output results is performed only with valid circuit outputs. Alternatively, one of the time-failure events is validated at the time of propagation to an internal node or a gate output of the same circuit, and the remaining time-failure events are returned to a state in which no time-failure has occurred, and event processing is performed. It is also possible.

It is apparent that the simultaneous (parallel) execution of a plurality of time-failure event processes shortens the simulation process time. However, the simulation processing program becomes complicated.

[0045]

As described above, according to the present invention, a fault model is set for a fault in which the signal transition time fluctuates for a specific time on a predetermined signal path or a predetermined gate terminal inside a semiconductor circuit, and a test pattern for an inspection test pattern is set. By using, the signal change caused by the circuit fault in the fault model propagates to the outside,
It can be determined whether an in-circuit fault is detected.

Therefore, it is possible to easily determine whether or not a test pattern used in a fault test of a semiconductor circuit is effective for a time fault test. In addition, an efficient test pattern for inspection can be generated.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure in a time failure simulation method according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a logic circuit showing an example of a faulty circuit model used in the embodiment.

FIG. 3 is a timing chart for explaining the operation of the logic circuit used in the embodiment;

[Explanation of symbols]

 201 Logic circuit

Claims (10)

[Claims] 1. A failure that shifts a transition time of a signal level at an arbitrary point in a semiconductor circuit is defined as a time failure, and a test pattern for a failure test of the semiconductor circuit is verified with respect to the time failure. A time failure simulation method for performing a simulation on the semiconductor circuit, wherein the transition time on a specific signal path or on a gate terminal of the arbitrary point of the semiconductor circuit is changed by a predetermined time. Displacing, causing the time failure in the semiconductor circuit, and determining, by the test pattern, whether or not the influence on the output signal from the semiconductor circuit due to the displacement of the transition time is detected. Characteristic time failure simulation method. 2. A method for arbitrarily setting a time fault occurrence location for all gate terminals and all nodes in a semiconductor circuit, and calculating the time fault location and a displacement time of a signal transition time at the time fault location. A first step of storing as time failure list information corresponding to each of all gate terminals and all nodes, a second step of generating an input test pattern to be applied to the semiconductor circuit to be simulated, On the other hand, at least one or more of the time-failure locations included in the time-failure list information and the displacement time of the signal transition time at the time-failure location are set, and the fault circuit model with the setting and the fault circuit model are not performed. A third step of executing the simulation for the normal circuit model, and providing the displacement time by the input test pattern. A fourth step of executing a propagation process of a time displacement event occurring at the gate terminal and the node, and transmitting each propagation output result by simulation of the faulty circuit model and the normal circuit model at a predetermined strobe time during the simulation. A fifth step of comparing and, when a difference occurs in the comparison result, storing that the displacement time is detectable, and then deleting the displacement time and the time failure location from the time failure list information. Step 6 and when no difference occurs in the comparison result or when the sixth step is executed, the input test pattern is calculated based on all the time fault locations and displacement times in the time fault list information. It is determined whether or not the event has been processed. If there is an unprocessed event, the process proceeds to the third step. A seventh step of executing a process, and when it is confirmed that the unprocessed event does not exist and the simulation has an unexecuted input test pattern, the input test pattern is updated to the input test pattern. 8. The time failure simulation method according to claim 1, further comprising an eighth step of executing a transition process to a step. 3. In a first step, a time-failure point is arbitrarily set for all signal paths from an input terminal to an output terminal of the semiconductor circuit, and the time-failure point and a signal transition time at the time-failure point are determined. The time failure simulation method according to claim 2, wherein the displacement time is stored as time failure list information in correspondence with each of the signal paths. 4. The method according to claim 1, wherein, in the first step, a signal transition time at which the signal transitions from "1" to "0" and a signal transition from "0" to "1" is respectively displaced. 3. The time failure simulation method according to claim 2, wherein the time failure simulation information is stored as failure list information. 5. The method according to claim 1, wherein in the first step, one common displacement time is set for the signal transition time at which the signal transitions from "1" to "0" and "0" to "1". 3. The time failure simulation method according to claim 2, wherein the time failure simulation method is stored as list information. 6. The method according to claim 1, wherein, in the first step, a signal transition time at which a level transition from "1" to "0" and a signal transition from "0" to "1" is separately delayed by the time. 3. The time failure simulation method according to claim 2, wherein the time failure simulation information is stored as failure list information. 7. In the first step, a signal transition time at which a level transition from "1" to "0" and a level transition from "0" to "1" as a signal transition is respectively advanced by a different time. 3. The time failure simulation method according to claim 2, wherein the time failure simulation information is stored as failure list information. 8. In a fourth step, at a gate terminal and a node having a displacement time with respect to a signal transition time,
The time failure simulation method according to claim 2, wherein when a time displacement event does not occur with respect to execution of the input test pattern, the process proceeds to a seventh step without passing through the fifth step. 9. In a third step, two or more signal transition times included in the time failure list information with respect to the signal transition times at which the signal transitions from “1” to “0” and from “0” to “1” as the signal transition In the fourth step, in the fourth step, during the propagation process, the time displacement events generated from a plurality of time-failure locations for the input test pattern propagated to the gate terminal or node at the same location in the semiconductor circuit. At the time of occurrence of a location propagation time failure event, the subsequent same location propagation time failure event processing is interrupted, and all signal paths and output terminals connected to the same terminal gate terminal or node fan-out are invalidated. And the fifth
In the step, the comparison processing of the propagation output result by the simulation at the output terminal invalidated due to the same location propagation time failure is not performed, and in the seventh step, only the plurality of time failure events of executing the sixth step are performed. The time failure simulation method according to claim 2, wherein is treated as a processing event. 10. In the fourth step, during a propagation process, a time displacement event generated from a plurality of time-failure locations for an input test pattern propagates to the same location gate terminal or node in the semiconductor circuit. For a failure event, one time failure event of the same location propagation time failure event is validated, and the other time failure event is processed as an event state in which no time failure has occurred. The time failure simulation method according to claim 9.