JP2669968B2 - Circuit failure pseudo test apparatus and circuit failure pseudo test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Table of Contents] Industrial Application Conventional Technology (FIGS. 23 and 24) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 to 3) Action Example (1) First Implementation Description of Example (FIGS. 4 to 9) (2) Description of Second Embodiment (FIGS. 10 to 16) (3) Description of Third Embodiment (17th to 22nd) Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit failure pseudo test apparatus and a circuit failure test method, and more specifically, it tests a semiconductor device under test (hereinafter referred to as LSI under test) having a failure point set therein. The present invention relates to simplification of an apparatus and method for supplying data and performing failure simulation.

In recent years, ultra-high integration of semiconductor integrated circuit devices,
In the field of LSI automatic design, with the increase in ultra-high density, failure simulation of a LSI under test in which logic gates are assembled is under way using a large-scale computer.

According to this, by performing a failure simulation for each failure of logic gates including a failure set inside the LSI under test based on the test data, the failure detection rate, undetected failure, etc. Information is obtained.

Therefore, it is necessary to calculate the output value of the logic gate for each of the logic gate not including the fault and the logic gate including the fault, and to compare the respective results at the output points of the respective logic gates. Further, it is necessary to judge each failure point whether or not the failure result is transmitted to the signal output section of the LSI under test.

As a result, the LSI under test can be highly integrated,
With ultra-high density, failure detection and evaluation becomes more and more difficult, leading to a longer logic gate design period. In addition, the central processing unit (hereinafter CP
(U) is used (occupied) for a long time, and the memory capacity of the data storage device is inevitably increased in order to calculate the output value of each logic gate and compare them.

Therefore, the presence / absence of failure propagation is determined for each logic gate such as a circuit having a gate delay time or a state memory based on the failure information in which the failure mode is defined in advance to simplify the failure detection evaluation. What is desired is a device and method that can reduce the memory capacity and the load on the CPU in addition to the above.

[0008]

2. Description of the Related Art FIGS. 23 and 24 are explanatory views of a conventional example. FIG. 23 is a configuration diagram for explaining a failure simulation according to the conventional example, and FIG. 24 shows a processing flowchart of the comparison / determination editor.

In FIG. 23, a plurality of logic gates LG1, L
The apparatus for performing a failure simulation of the LSI under test 7 in which G2, LGi... LGn are incorporated includes a failure simulation control memory 1, a test data file memory 2, a failure information memory 3, a comparison / judgment editor 4, a CPU 5, a display 6, a keyboard 9 And a system bus 8 for transmitting data between them.

The function of the device is, for example, the logic gate L.
G1, LG2, LGi ... LGn assembled LS under test
Comparison of Fig. 24 when performing a failure simulation of I7
/ As shown in the processing flow chart of the judgment editor,
First, at step P1, a failure point FLT is set in the LSI under test 7, and the test data DT is set in the signal input section IN of the LSI 7.
Supply processing. At this time, the LSI under test 7 is displayed on the display 6 or the like based on the display data D3.

Further, the operator inputs the input data D2 relating to the fault point FLT via the keyboard 9, and sets the fault point FLT in the signal input section IN of the logic gate LG1, for example. Further, the test data DT is read from the test data file memory 2 via the CPU 5.

Next, in step P2, the output values of the respective logic gates LG1, LG2, LGi ... LGn of the LSI to be tested 7 which have been set as failures are compared with the output values under normal conditions. At this time, the comparison / judgment editor 4, based on the control data D1 read from the failure simulation control memory 1, etc.
The CPU 5 performs arithmetic processing.

In this operation processing, the influence of the fault point FLT is determined for each of the logic gates LG1, LG2, LGi.
The failure simulation is performed by comparing the output value at the normal time when the value is not set and the output value at the failure when the failure point FLT is set one by one. The normal output value, the failure output value, and the comparison result data are stored in the failure information memory 3.

Thereafter, in step P3, it is determined whether or not the influence of the fault point FLT is transmitted to the signal output unit OUT.
At this time, if the influence of X is transmitted to the signal output unit OUT (YES), the process proceeds to step P4 and it is determined that "the influence of the fault point FLT can be observed by the test data DT".

When the influence of X does not propagate to the signal output unit OUT (NO), the process shifts to step P5 and "the influence of the fault point FLT cannot be observed in the test data DT".
Is determined. The above processing of steps P1 to P5 is performed for all the faults and all the test data DT to be the targets of fault detection.

As a result, it is possible to perform a failure simulation for all the failure points set in the LSI under test 7 which are targets of the failure detection, and information such as the failure detection rate and the undetected failure for the LSI under test 7 can be obtained. can get.

[0017]

By the way, according to the conventional example, the failure point FLT set in the LSI under test 7 is subjected to a failure simulation for each failure based on the test data DT, so that the LSI under test 7 is tested. Information such as the failure detection rate and undetected failures is obtained.

Therefore, the output value of the logic gate for each of the logic gates LG1, LG2, LGi ... LGn of the logic circuit not including the fault point FLT and the logic gates LG1, LG2, LGi ... LGn of the logic circuit including the fault point FLT. Must be processed by the comparison / judgment editor 4 and the CPU 5, and each must be compared at each logic gate output point.

Further, in order to judge whether or not the failure result is transmitted to the failure detection judgment point of the LSI under test, the result data of each arithmetic processing is stored in the failure information memory 3 in order to judge each failure point. I have to do it. That is,
LSI under test with failure points set for test data
Then, it is confirmed whether or not the difference in the output value of each logic gate between the LSI under test having no failure point is transmitted to the signal output section of the LSI under test.

As a result, the LSI to be tested is highly integrated,
With ultra-high density, fault detection and evaluation becomes more and more difficult, and, for example, the gate delay time and the logic gate design period of a circuit having state memory are prolonged. In addition, there is a problem that the CPU 5 is used (occupied) for a long time in the fault simulation, and the memory capacity of the fault information memory 3 for calculating the output value of each logic gate and comparing them is inevitably increased. There is.

The present invention was created in view of the problems of the conventional example, and a failure mode is defined in advance for each logic gate such as a circuit having a gate delay time and a state memory so as to determine whether or not there is a failure transfer. To provide a circuit failure pseudo test apparatus and a circuit failure test method capable of making a detection judgment based on failure information and simplifying failure detection evaluation, and at the same time, reducing a load on a memory capacity and a CPU. To aim.

[0022]

Means for Solving the Problems FIG. 1, FIG. 2 (a),
FIG. 3B is a principle diagram (1 and 2) of the circuit fault pseudo test apparatus according to the present invention, and FIGS. 3A and 3B are principle diagrams of the circuit fault test method according to the present invention. ing.

The first circuit fault pseudo test apparatus of the present invention comprises:
As shown in FIG. 1, a plurality of logic gates LG1, LG2, LGi ...
Regarding the semiconductor device 16 under test formed by connecting LGn,
An apparatus for simulating the propagation of a fault in the logic gate LGi, wherein an input value of the logic gate LGi is a logic 1
Alternatively, failure information fSa1 and fSa indicating a failure fixed at logic 0
The first storage means 11 for storing 0, the second storage means 12 for storing the test data DT of the semiconductor device under test 16, and the second storage means 12 to the semiconductor device under test 16 for the test The data DT is read and input, the normal operation of the semiconductor device 16 to be tested is simulated, and the first processing for obtaining the normal output value of each of the logic gates LG1, LG2, LGi ... LGn is performed. One of the logic gates LG1, LG2, LGi ... LGn is targeted, and one input terminal of the targeted logic gate LGi has a logic value opposite to a normal input value of the input terminal. 1
Alternatively, the failure information fSa1 and fSa0 of logic 0 is read from the first storage means 11 and input, and the normal input values are input to the remaining input terminals of the logic gate LGi to detect the failure information of the logic gate LGi. The second process of simulating the operation and obtaining the output value at the time of failure is performed, and the output value at the time of failure of the target logic gate LGi obtained by the second process is obtained by the first process. If the output value at the time of failure of the logic gate LGi has a logic value opposite to the output value at the time of normality as compared with the output value at the time of normality, it indicates that "the failure propagates to the logic gate". When the identification information “1” is given to the failure information fSa1 and fSa0 of the logic gate LGi and the output value at the time of failure of the logic gate LGi has the same logic value as the output value at the time of normal operation, “the failure is Do not propagate the logic gate ” Is applied to the fault information fSa1 and fSa0 of the logic gate LGi, and for each of the logic gates LGi, the second process is performed for all the input terminals of the logic gate LGi. And the failure information fSa1, to which the identification information is added by the control means 15 and the control means 15 that sequentially executes the third processing.
The failure information fSa1 and fSa0 to which the identification information 0 or 1 is added is searched from the third storage unit 13 that stores fSa0 and the storage content of the third storage unit 13, and the above Information for detecting whether or not the logic gate LGi having the failure information fSa1 and fSa0 to which identification information indicating "propagate through gate" is added is continuous from the input section IN of the semiconductor device 16 under test to the output section OUT. And a detection means 14.

The second circuit fault pseudo test apparatus of the present invention is the first apparatus, wherein the third storage means 13 is the same as that of FIG.
As shown in (a), the scheduled transfer time information ts0, ts1 that defines the time until the fault reaching the input point of the logic gate reaches the logic gate LGi of the next stage is stored, and the control means 15 is stored. When the failure information fSa0, fSa1 when a signal change is given to the test data DT is obtained, the current time has elapsed with reference to the scheduled transfer time information ts0, ts1 read from the third storage means 13. The present invention is characterized in that the failure information fSa0 and fSa1 that are present are made valid.

The third circuit fault pseudo test apparatus of the present invention is
In the first device, the third storage means 13 is the same as that shown in FIG.
As shown in (b), the failure information fSa0, f from the final failure detection determination time T1 one cycle before of the test data DT to an arbitrary failure detection determination time TX of the current cycle.
Sa1 is stored, and the control unit 15 logically ORs the failure information fSa0, fSa1 read from the third storage unit 13 with the latest failure information fSa0, fSa1 of the arbitrary failure detection determination time TX in the current cycle. It is characterized by calculating.

Furthermore, the first circuit fault pseudo-test method of the present invention uses a plurality of logic gates LG as shown in FIG.
A method for simulating the propagation of a failure of the logic gate LGi in a semiconductor device under test in which 1, LG2, LGi ... LGn are connected, as shown in the flowchart of FIG. To generate fault information fSa1, fSa0 indicating a fault that fixes the input value of the logic gate LGi to logic 1 or logic 0, and then to step P
2, test data DT is input to the semiconductor device 16 under test. At step P 3, the normal operation of the semiconductor device 16 under test is simulated to
The first processing for obtaining the normal output value of G1, LG2, LGi ... LGn is performed, and 1 of the logic gates LG1, LG2, LGi ... LGn is performed.
For one of the target logic gates LG i, one of the input terminals of the logic gate LG i is input with failure information of logic 1 or logic 0 having a logic value opposite to the normal input value of the input terminal, The second processing is performed by inputting a normal input value to the remaining input terminal of the logic gate LGi and simulating the operation of the logic gate LGi at the time of failure to obtain an output value at the time of failure. The output value at the time of failure of the target logic gate LGi obtained by the above is compared with the output value at the time of normality obtained by the first process, and the output value at the time of failure of the logic gate LGi When the logic value is opposite to the output value, the identification information "1" indicating that "the fault propagates through the logic gate" is added to the fault information fSa1 and fSa0 of the logic gate LGi, and the logic gate concerned is added. Output when the output value at the time of failure of LGi is normal If the same logic value "failure the logic gate does not propagate" the "0" identification information indicating that the logical gates LGi malfunction information f with respect to
Sa3 and fSa0 are subjected to a third process, and for each of the logic gates LG1, LG2, LGi ... LGn, the second and third processes are sequentially executed for all input terminals of the logic gate, Then, in step P4, the failure information fSa1 and fSa0 to which the identification information is added is searched, and the logic having the failure information fSa1 and fSa0 to which the identification information indicating that the “fault propagates through the logic gate” is added. Gate LG i
Is detected from the input section of the semiconductor device under test to the output section.

In the first circuit fault pseudo test method of the present invention, the fault mode information is the first single stuck-at fault M0.
And a second single stuck-at fault M1. In the first stuck-at fault M1, the output signal or the input signal of the logic gate is logical when the fault point is set in the semiconductor device 16 under test. The first stuck-at fault fixed to “0” is defined as the case where only one first stuck-at fault exists in the semiconductor device 16 under test, and the second single stuck-at fault M1 is defined.
Is a second stuck-at fault in which an output signal or an input signal of the logic gate is fixed to logic “1” when a failure point is set in the semiconductor device under test 16, and the second stuck-at fault is It is specified that only one semiconductor device under test 16 exists.

In the first circuit fault pseudo test method of the present invention, the fault information fSa0, fSa1 includes first fault information and second fault information, and the first fault information is the first fault information. It is defined as a case where the single stuck-at fault M0 of 1 propagates to the logic gate of the next stage, and the second fault information is that the second stuck-at fault M1 of the next stage is It is characterized in that each is defined as a case of indicating whether or not it is transmitted to the logic gate.

The second circuit fault pseudo test method of the present invention is
In the first method, when the time until the fault reaching the input point of the logic gate reaches the logic gate of the next stage is defined as the scheduled propagation time information ts0, ts1,
In step P3 of the flowchart of FIG. 3B, when obtaining the fault information fSa0 and fSa1 when a signal change is given to the test data DT for the fault simulation, the transmission scheduled time information ts0 and ts1 are used as a reference. The failure information fSa0 and fSa1 whose current time has passed are validated.

Further, the third circuit fault pseudo-testing method of the present invention is the same as that of the flowchart of FIG. 3B when the semiconductor device 16 under test includes the memory element MEM in the first method. In Step P3, the latest failure information fSa0, fSa1 detected at the final failure detection determination time T1 one cycle before the test data and the arbitrary failure detection determination time T in the current cycle from the final failure detection determination time T1.
The feature is that the failure information fSa0 and fSa1 up to X is ORed.

In the third circuit failure pseudo test method, when the semiconductor device under test 16 includes the memory element MEM, step P in the flowchart of FIG. 3B.
4, the first search from the signal output part of the semiconductor device under test 16 to the memory element MEM, and the memory element M
The second search from the input portion of the EM to the signal input portion of the semiconductor device under test 16 is executed.

In the third circuit failure pseudo test method, when the semiconductor device under test 16 includes the memory element MEM, the failure information fSa0, After the detection of fSa1, all pieces of failure information fSa0 and fSa1 from the last failure detection determination time T1 one cycle before the test data to any failure detection determination time T2 of the current cycle are replaced with the current cycle of the test data. The object is achieved by matching the latest failure information fSa0 and fSa1 at the last failure detection determination time T2.

[0033]

According to the circuit failure pseudo-testing apparatus of the present invention, as shown in FIG.
, The first, second, and third storage means 11, 12,
13, information detecting means 14 and control means 15 are provided.

In the case of failure simulation of the semiconductor device 16 under test incorporating a plurality of logic gates LG1, LG2, LGi ... LGn with such a configuration, first, when the logic gates LG1, LG2, LGi ... LGn are normal. The control means 15 reads the test data DT from the second storage means 12 and obtains the output value of the semiconductor device 16 under test.
Input to and perform normal logic simulation. Next, in order to assume a failure (setting of a failure point FLT) that fixes the input of the logic gate LG i to logic 1 or logic 0, the control means 15
Target one of the logic gates LG1, LG2, LGi ... LGn, and have a logic 1 or logic 0 that has a logic value opposite to the normal input value of the input terminal of the logic gate LG1. Failure information fSa1, fSa0 of the first storage means 11
Choose from Then, the control means 15 inputs the failure information fSa1 and fSa0 of the selected logic 1 or logic 0 to one input terminal of the logic gate LGi in order to obtain the output value at the time of failure, and when the other input terminals are normal. Is input to simulate the operation of the logic gate at the time of failure (second processing). Next, the control means 15 determines the output value at the time of failure of the target logic gate LGi in order to determine whether or not the failure information fSa1, fSa0 assumed in the input part of the logic gate LGi exceeds the logic gate LGi. Compare with the output value under normal conditions. Based on this comparison result, the logic gate L
When the output value of Gi at the time of failure has a logic value opposite to the output value at the time of normal operation, identification information indicating that “the failure propagates through the logic gate” is added to the failure information fSa1 and fSa0. When the output value at the time of failure of the logic gate LG i has the same logic value as the output value at the time of normality, the identification information indicating that “the failure does not propagate through the logic gate” is added to the failure information f.
It is given to Sa1 and fSa0. Then, the control unit 15 associates the failure information fSa1 and fSa0 to which the identification information has been added with the target logic gate LGi (third processing). Failure information f in which identification information and logic gate LG i are associated
Sa1 and fSa0 are transferred from the control means 15 to the third storage means 13 and stored therein. The control means 15 sequentially executes the second and third processes for each of the logic gates LG1, LG2, LGi ... LGn and for all the input terminals of the logic gates LG1, LG2, LGi ... LGn. . At this point, it is only known whether or not the failure information for fixing the input to logic 1 or logic 0 propagates through one logic gate LGi, and the logic gates LGi throughout the semiconductor device 16 to be tested.
It is impossible to determine whether or not the path assumed to have propagated from the input section to the output section OUT of the semiconductor device 16 under test is formed. Therefore, in the present invention, the control means 15 sets the second gate for all the input terminals of the logic gate LGi.
And when the third process is executed and ended, the information detecting means 14
However, the stored information in the third storage unit 13 is searched for the failure information fSa1 and fSa0 to which the identification information is added. The search method is, for example, the output unit OUT of the semiconductor device 16 under test.
From the input part IN. Then, the information detecting means 14 causes the failure information fSa1 and fSa0 to which the identification information is added.
Is detected from the input unit IN of the semiconductor device under test 16 to the output unit OUT. Based on this detection result, the logic gate LGi having the failure information fSa1 or fSa0 to which the identification information that "the failure propagates through the logic gate" is added is continuously connected from the output section OUT of the semiconductor device 16 under test to the input section IN. If it is, the semiconductor device under test 16 has an input unit IN to an output unit OU.
Since the fault propagation path reaching T is formed, it can be determined that "the stuck-at fault assumed at the input part of the logic gate at the output part of the semiconductor device under test can be observed in this test data". It should be noted that the failure information f added with identification information that "the failure does not propagate through the logic gate"
If the logic gate LG i having Sa1 or fSa0 exists between the input section IN and the output section OUT of the semiconductor device 16 under test, the fault propagation path is cut off on the way,
It can be determined that "at the output section of the semiconductor device under test, the stuck-at fault assumed at the input section of the logic gate cannot be observed in this test data."

For this reason, the output values of the logic gates LG1, LG2, LGi... LGn are respectively calculated by the logic circuit having a fault point and the logic circuit having no fault point FLT for the test data DT, and until the two match, or , Until the external output point is reached, the comparison / judgment editor 4 and CPU as in the conventional example
5 eliminates the need for comparison and arithmetic processing. As a result, the load on the control means 15 is increased by each logic gate LG1, LG2,
Failure information fSa0, fSa1 remaining at the input point of LGi ... LGn
Is calculated and stored in the third storage unit 13.

Further, regarding whether or not the influence of the fault point FLT is transmitted to the signal output section (fault detection judgment point) of the semiconductor device 16 under test (fault propagation), each logic gate for each fault. Since it is not determined for each output point of LG1, LG2, LGi ... LGn, each logic gate LG as in the conventional example.
It becomes unnecessary to store the calculation result data of the output values of 1, LG2, LGi ... LGn.

As a result, the control means 15 is different from the conventional example.
It is possible to reduce the use (occupation) time of the device and to reduce the memory capacity of the third storage means (failure information memory 3).

As shown in FIG. 2A, the expected propagation times ts1 and ts0 for the failure information fSa0 and fSa1 of the logic gates LG1, LG2, LGi ... By storing in the storage means 13, it becomes possible to perform a highly accurate failure simulation including the gate delay time td of the logic gates LG1, LG2, LGi ... LGn.

Further, as shown in FIG. 2B, the final failure detection determination time T1 one cycle before the test data DT.
From the failure information DSa0, DSa1 based on the failure information fSa0, fSa1 up to the arbitrary failure detection determination time TX related to the current cycle of the test data DT in the third storage means 13 to store the storage element MEM. It is possible to perform a highly accurate failure simulation for the semiconductor device 16 under test including the above.

Further, according to the first circuit fault pseudo-test method of the present invention, as shown in the flowchart of FIG. 3B, the input value of the logic gate LGi is previously set to logic 1 or logic 0 in step P1. Failure information fSa1, indicating the failure to be fixed
fSa0 is created, and then the test data DT is input to the semiconductor device under test 16 in step P2, and in step P3,
The first and second processes calculate whether or not the fault information fSa1 and fSa0 propagates through the logic gate LGi, and the third process indicates that "fault propagates through the logic gate" by the third process. The identification information (hereinafter also referred to as an identification flag) "1" indicating "Yes" or the identification flag "0" indicating "a failure does not propagate through the logic gate" is added to the failure information fSa1 and fSa0 of the logic gate LGi. Then, these processes are sequentially executed, and thereafter, the failure information fSa1 and fSa0 to which the identification information is added in step P4 is searched, and the identification information indicating that “the failure propagates through the logic gate” is added. Logic gate L having failure information fSa1 and fSa0
Gi is the input unit IN to the output unit OU of the semiconductor device 16 under test.
Whether or not it is continuous to T is detected.

Therefore, a plurality of logic gates LG1, LG2,
When a failure point FLT is set in the semiconductor device 16 under test in which LGi ... LGn is incorporated and a failure simulation is performed,
In step P4, the final fault information fSa0 = 1 or 0 indicating the possibility of transmitting the first single stuck-at fault M0 from the signal output unit OUT to the signal input unit IN or the second single stuck-at fault M1.
The failure detection evaluation of the semiconductor device 16 under test can be easily performed by performing the detection processing of arbitrary failure information fSa1 = 1 or 0 indicating the propagation possibility of the semiconductor device 16 under test.

As a result, even when there is a demand for ultra-high integration and ultra-high density of the semiconductor device 16 under test, failure detection and evaluation can be simplified, and the design period of the logic gate can be shortened. It becomes possible.

Further, according to the second circuit fault pseudo test method of the present invention, step P in the flow chart of FIG.
In the calculation storage processing of 3, the storage processing of the scheduled propagation times ts1 and ts0 relating to the failure information fSa0 and fSa1 and the failure information fSa0 whose current time tc has passed the scheduled propagation times ts1 and ts0,
A calculation process for determining the failure information DSa0, DSa1 with fSa1 valid is executed.

Therefore, the logic gates LG1, LG2, LGi ...
When the fault point FLT is set in LGn, for example, even if a signal change (event) occurs in the input net, no event occurs in the output net of the normal circuit, that is, the logic gates LG1, LG2, LGi. ... When a signal change is scheduled to be propagated at a time after the gate delay time of LGn, it is necessary to detect a fault in which the current time tc has passed until the scheduled propagation time ts1, ts0, not the signal generation time of the input net. Becomes possible. In other words, when the influence of the fault point is transmitted to the output net after the gate delay time, it is assumed that the fault information fSa0, fSa1 at that time is transmitted by the fault "f.
Sa0, fSa1 = 1 ”can be set.

As a result, the logic gates LG1, LG2, L
It is possible to execute a failure simulation based on an actual failure circuit in consideration of the gate delay time td of Gi ... LGn with high accuracy.

Further, according to the third circuit fault pseudo test method of the present invention, step P in the flow chart of FIG.
In the calculation storage process of 3, the latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before the test data DT and an arbitrary failure detection determination time related to the current cycle of the test data DT. Failure information f up to TX
The logical sum operation processing with Sa0 and fSa1 is performed.

Therefore, even if the memory element MEM is included in the logic gates LG1, LG2, LGi ... LGn of the semiconductor device under test 16, the internal state of the memory element MEM which changes with time is, for example, The latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before the test data DT and the arbitrary failure detection determination time TX related to the current cycle of the test data DT from the final failure detection determination time T1. To determine the fault propagation property related to the memory element MEM by performing an OR operation with "fSa0, fSa1 = 1", which is assumed that the fault information fSa0, fSa1 up to the above has been transmitted even once. Is possible.

In step P4, the storage element M
The detection process of the fault information fSa0, fSa1 of the logic gates LG1, LG2, LGi... LGn including EM is executed by first and second search processes, and after the detection process, the test data D
The latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before T and the final failure detection determination time T1
To all of the failure information MSa0, M from the end to the final failure detection determination time T2 related to the current cycle of the test data DT
Sa1, DSa0, and DSa1 are used as fault information fSa0, f of the last fault detection determination time T2 in the current cycle of the test data DT.
Matches Sa1.

Therefore, even if the influence of the failure of the input net of the storage element MEM is not reflected on the output net by one operation, the failure information fSa0 and fSa1 staying in the storage element MEM can be obtained. The fault information fSa0, fSa1 can be detected with good reproducibility without ignoring it.

As a result, a highly accurate failure simulation of the semiconductor device 16 under test including the storage element MEM can be performed.

[0051]

Next, an embodiment of the present invention will be described with reference to the drawings. 4 to 22 are views for explaining the circuit fault pseudo test apparatus and the circuit fault test method according to the embodiment of the present invention.

(1) Description of First Embodiment FIG. 4 is a configuration diagram of a circuit failure pseudo test apparatus according to each embodiment of the present invention, and FIGS. 5 and 6 show supplementary explanatory diagrams thereof.

For example, a device for simulating a failure of a semiconductor device under test (hereinafter referred to as LSI under test) 16 having a plurality of logic gates LG1, LG2, LG3 as shown in FIG. Control memory 21, test data file memory 22, failure information memory 23, data search editor 24, CPU 2
5, a display 26, a keyboard 27, and a system bus 28 for transmitting data therebetween.

That is, the failure simulation control memory 21 is an embodiment of the first storage means 11, and the failure mode information Sa0, S of the LSI 16 under test which is defined in advance.
a1 and control data D1 are stored. The definition process will be described with reference to FIGS.

The test data file memory 22 is an embodiment of the second storage means 12, and stores the test data DT for performing the failure simulation of the LSI under test 16.

The fault information memory 23 is the third storage means 13.
In this embodiment, failure information fSa0, fSa1 calculated with respect to a failure propagation at each of the logic gates LG1, LG2, LGi... LGn based on test data DT is stored (see FIG. 5). In the circuit fault pseudo test method according to the second embodiment, the fault information memory 23 has fault information fSa0, f of the logic gates LG1, LG2, LGi ... LGn of the LSI under test 16.
The transmission scheduled time ts1 and ts0 for each Sa1 are stored.

In the circuit failure simulation test method according to the third embodiment, the failure information memory 23 stores the latest failure information fSa0, fSa1 relating to the last failure detection determination time T1 one cycle before the test data DT. And failure information f from the last failure detection determination time T1 to any failure detection determination time TX related to the current cycle of the test data DT.
The fault information MSa0, MSa1 based on Sa0, fSa1 is stored.

The data search editor 24 is the information detecting means 1
4 is an embodiment of the present invention, and detects the failure information fSa0, fSa1, MSa0, MSa1 calculated for the failure propagation at each logic gate gate LG1, LG2, LGi ... LGn based on the definition process.

The CPU 25 is an embodiment of the control means 15, and controls the input / output of the failure simulation control memory 21, the test data file memory 22, the failure information memory 23, the data search editor 24, the display 26 and the like. For example, the CPU 25 performs the following calculation regarding failure propagation. First, the test data DT is read from the test data file memory 22 and the test data L is tested.
Input to SI16 to simulate the normal operation of the LSI under test 16 to obtain logic gates LG1, LG2, LG
The output value of i ... LGn at the normal time is obtained (first processing). Further, the CPU 25 uses the logic gates LG1, LG2, LGi ... LGn.
Failure information fSa of logic 1 or logic 0, which has a logic value opposite to the input value of the logic gate LG i, which is the target of the logic gate LG i.
1, fSa0 is read from the failure simulation control memory 21 and input, input values at the time of normality are input to the remaining input terminals of the logic gate LGi, and the operation at the time of failure of the logic gate LGi is simulated. The output value is obtained (second process). Based on these first and second processes, the CPU 25 gives an identification flag to the failure information fSa1 and fSa0. The addition of the identification flag will be described later.
Further, the CPU 25 manages the time of the test data DT, that is, the final failure detection determination time T1 one cycle before the latest information of the failure information fSa0, fSa1 or the last failure detection determination time T1. Counting processing and the like are performed until an arbitrary failure detection determination time TX related to the current cycle of DT.

Further, the CPU 25 transmits the test data DT
Failure information DSa0 obtained by performing a logical sum operation based on the failure information fSa0 and fSa1 from the last failure detection determination time T1 one cycle before to any failure detection determination time TX related to the current cycle of the test data DT. , DSa1 is output.

The display 26 displays the display data D3.
Based on the above, the LSI under test 16 being designed is displayed. The keyboard 27 is used by an operator or the like to input the input data D2 relating to the failure point FLT when performing the failure simulation. For example, the logic gate LG1
The fault point FLT is set in the signal input portion IN of the.

FIG. 5 is an explanatory diagram of the contents of the failure mode memory table according to the first embodiment of the present invention. FIG.
Is a failure mode, and is classified into first and second single stuck-at faults M0 and M1. The first single stuck-at fault M0 is the first one in which the output signal or the input signal of the logic gates LG1, LG2, LGi... LGn is fixed to logic "0" when the fault point FLT is set in the LSI under test 16. A stuck-at fault is a fault mode in which only one first stuck-at fault exists in the LSI 16 under test.

For example, a two-input OR logic gate (hereinafter OR
Circuit) and an output value of a logic gate LGi such as a two-input AND logic gate (hereinafter referred to as an AND circuit) is logic “0”.
Mode. This is due to, for example, a failure in which one line of the signal input section of the OR circuit or AND circuit touches the ground line GND, and a "0" level is always applied to one signal input section of the circuit. . Thereby, when “1” is input to another signal input unit, the OR circuit and the AND
The output value of the circuit becomes “0”. This failure mode information is defined as Sa0.

Further, fSaO is failure information indicating the propagation property of the first single stuck-at fault M0 as an example of the final failure information. For example, fSaO = 0 is defined when the first single stuck-at fault M0 does not propagate to the next-stage logic gate LGi. Further, the case where the first single stuck-at fault M0 propagates to the logic gate LGi of the next stage is defined as fSaO = 1.

The second single stuck-at fault M1 is the LSI under test.
When the fault point FLT is set in 16, the logic gate LG
It is a failure mode in which the output signal or the input signal of 1, LG2, LGi ... LGn is the second stuck-at fault fixed to the logic "1", and only one second stuck-at fault exists in the LSI under test 16. For example, this is a mode in which the output value of the logic gate LG i of the OR circuit, the AND circuit, or the like is fixed to the logic “1”.

This is because one line of the signal input section of the OR circuit or AND circuit is opened due to a failure such as disconnection, and the "1" level is always applied to one signal input section of the circuit. Things. As a result, when "1" is input to the other signal input section, the output value of the OR circuit or AND circuit becomes "1". This failure mode information is defined as Sa1. Further, fSa1 is failure information indicating the propagation property of the second single stuck-at fault M1 as an example of the second failure information. For example, fSa1 = 0 is defined when the second single stuck-at fault M1 does not propagate to the next-stage logic gate LGi. Further, fSa1 = 1 is defined when the second single stuck-at fault M1 propagates to the logic gate LGi at the next stage.

The defined failure mode information Sa0, S
a1, the first and second failure information fSa0, fSa1 are stored in the failure simulation control memory 21 as control data D1.

FIG. 6 is an explanatory diagram of the contents of the failure information memory table according to the first embodiment of the present invention. In FIG. 6, m is the content of the failure information memory table, for example, failure information storage when the failure point FLT is set in either of the input nets A and B of the logic gate LGi such as an OR circuit and an AND circuit. Indicates the situation.

For example, the failure information fSa0 = 1 for the input net A of the OR circuit is stored in the first net A.
This is the case where the single stuck-at fault M0 exists and propagates to the next-stage logic gate LGi. The output value of the OR circuit at this time is different from the output value at the normal time. Also,
Similarly, the failure information fSa1 = 0 for A is stored when the second single stuck-at failure M1 exists in the net A and is not transmitted to the logic gate LGi at the next stage. The output value of the OR circuit at this time is the same as the output value at the normal time.

Further, the failure information fSa0 = 0 for the input net B of the OR circuit is stored in the first net B.
This is a case where the single stuck-at fault M0 exists and does not propagate to the next-stage logic gate LGi. The output value of the OR circuit at this time is the same as the output value at the normal time.
Similarly, the failure information fSa1 = 0 for the net B is stored only when the second single stuck-at failure M1 exists in the net B and is not propagated to the logic gate LGi at the next stage. is there. The output value of the OR circuit at this time is the same as the output value at the normal time.

The fault information fSa0 = 0 is stored for the input net A of the AND circuit only when the first single stuck-at fault M0 exists in the net B, and the logic gate LGi of the next stage is stored. This is the case when you don't spread to. AN at this time
The output value of the D circuit is different from the output value at the normal time.

Similarly, failure information fSa1 for A =
0 is stored when the second single stuck-at fault M1 exists in the net A and is not transmitted to the logic gate LGi at the next stage. This is a case where the output value of the AND circuit at this time becomes the same as the output value at the normal time.

Further, the fault information fSa0 = 0 is stored for the input net B of the AND circuit only when the first single stuck-at fault M0 exists in the net B, and the logic gate LGi of the next stage is stored. This is the case when you don't spread to. A at this time
This is the case where the output value of the ND circuit becomes the same as the output value at the normal time.

Similarly, the failure information f for the net B is
Sa1 = 1 is stored when the second single stuck-at fault M1 exists in the net B and is transmitted to the logic gate LGi at the next stage. The output value of the AND circuit at this time is different from the output value at the normal time.

The failure information fSa0 = 0, fSa
For 1 = 0, fSa1 = 1, fSa0 = 1, the CPU 25 that has executed the first and second processes described above indicates a failure flag (“0”) indicating whether or not failure information propagates through the logic gate. Alternatively, an identification flag indicating "1" is set to the failure information fSa.
It is obtained by giving 0 and fSa1. That is, C
The PU 25 compares the output value at the time of failure of the logic gate LGi with the output value at the time of normality, and when the output value at the time of failure of the logic gate LGi becomes the opposite logic value to the output value at the time of normality, An identification flag (hereinafter also referred to as a failure propagation flag) "1" indicating that "a failure propagates through the logic gate" is given to the failure information fSa0 or fSa1. Also, the CPU 25
When the output value at the time of failure of the logic gate LGi has the same logic value as the output value at the time of normal operation, an identification flag (also referred to as a failure non-propagation flag) indicating that "the failure does not propagate through the logic gate". “0” is added to the failure information fSa1 or fSa0 (third processing). These processes are sequentially executed by the CPU 25 for each logic gate LGi for all the input terminals of the logic gate LGi. The failure information fSa0 = 0, fSa1 =
0, fSa1 = 1, fSa0 = 1 are the target logic gates LG
It is stored in the failure information memory 23 in association with i.
The amount of data is determined by the circuit configuration of the LSI under test 16. Therefore, compared with the conventional example, the failure information memory 23
Greatly reduces the amount of failure information stored in the.

As described above, according to the circuit fault pseudo test apparatus of each embodiment of the present invention, as shown in FIG. 4, the fault simulation control memory 21, the test data file memory 22, the fault information memory 23, the data retrieval editor. Two
4, a CPU 25, and the like.

In the case of performing a failure simulation of the semiconductor device 16 under test incorporating a plurality of logic gates LG1, LG2, LG3 with such a configuration, first, the failure mode information Sa is read from the failure simulation control memory 21.
0 or Sa1 and the fault information fSa1, fSa1 are read and set to the logic gate LG1, the test data DT is read from the test data file memory 22, input to the input part of the LSI under test 16, and then test data is input. At this time, the logic gates LG1 and LG are processed by the CPU 25 from the input section to the output section of the LSI under test 16.
2, the logic output of LG3 is calculated, and according to the calculation result,
An identification flag for distinguishing failure propagation or failure non-propagation is given to the failure information fSa0, fSa1 propagated from the logic gate LG1 to which the failure mode information Sa0 or Sa1 is set to the output OUT of the LSI under test 16, Next, the failure information fSa0 and fSa1 are stored in the failure information memory 23.

Further, the identification flags of the failure information fSa0 and fSa1 are set by the data search editor 24 to the LSI under test.
By detecting from the 16 output units to the input unit,
Fault propagation or non-propagation is searched. As a result, the failure mode information Sa0 is output from the output section OUT of the LSI under test 16.
Or Sa1 in logical late <br/> disabled information up to the gate LG1 fSa0, fSa1 set to, when the identification flag fSa0 = 1 of "fault propagation" could be retrieved, the influence of the fault from the "output section This test data D as "observable"
T can be selected. In addition, the LSI under test 16
In the output section OUT, "failure" of the failure information fSa0, fSa1
When the identification flag fSa0 = 0 of "non-propagation" is searched
With this test data, the search can be terminated early as "the effect of the failure at the output section can no longer be observed", and the test data effective for the test of the LSI under test 16 can be terminated.
It is possible to select only the data.

Therefore, the output values of the logic gates LG1, LG2, LGi ... LGn are calculated in the logic circuit having the fault point and the logic circuit having no fault point with respect to the test data DT, respectively, until the two coincide with each other, or Until the external output point is reached, the comparison / judgment editor 4 and the CPU 5 do not have to perform comparison and arithmetic processing as in the conventional example.

As a result, the burden on the CPU 25 is to calculate the fault information fSa0, fSa1 obtained from the input points of the respective logic gates LG1, LG2, LGi ... LGn, and to store it in the fault information memory 2
The processing to be stored in 3 is reduced.

Further, the influence of the fault point FLT depends on the LSI 1 under test.
Regarding whether to propagate to the signal output unit (fault detection determination point) 6 (fault propagation property), it is determined for each output point of each logic gate LG1, LG2, LGi ... LGn for each fault. Since it is not performed, each logic gate LG1 as in the conventional example,
It becomes unnecessary to store the calculation result data of the output values of LG2, LGi... LGn.

The logic gate LG of the LSI under test 16
By storing the scheduled transfer time ts1, ts0 for each of the failure information fSa0, fSa1 of 1, LG2, LGi ... LGn in the failure information memory 23, the gate delay time td of the logic gate LG1, LG2, LGi ... It is possible to perform a highly accurate failure simulation that includes this (see Fig. 11). .

Further, the latest failure information fSa related to the final failure detection determination time T1 one cycle before of the test data DT.
0, fSa1 and failure information MSa0, MSa1 based on all the failure information fSa0, fSa1 from the final failure detection determination time T1 to an arbitrary failure detection determination time TX related to the current cycle of the test data DT. By storing in the failure information memory 23, it is possible to perform a highly accurate failure simulation for the LSI under test 16 including the flip-flop circuit FF having state storage.

As a result, it is possible to reduce the use (occupancy) time of the CPU 25 and the memory capacity of the failure information memory 23 as compared with the conventional example. Next, a circuit fault pseudo test method according to an embodiment of the present invention will be described with supplementing the operation of the device.

FIG. 7 is a process flow chart of the circuit fault pseudo test according to the first embodiment of the present invention, and FIG.
(C) has shown the supplementary explanatory view.

For example, as shown in FIG. 8A, three stages of logic gates LG1 = AND circuit, LG2 = OR circuit, LG3 = A
When performing a failure simulation of the LSI under test 16 in which the ND circuit is incorporated, in FIG. 7, the failure modes M0 and M1 of the LSI under test 16 are defined in advance in step P1 to define failure information fSa0 and fSa1 indicating failure propagation. To process. In the embodiment of the present invention, it is assumed that the fault point FLT is set in the input net A of the LSI under test 16 (FIG. 8).
(See (a) to (c)).

The process of defining the failure modes M0 and M1 at this time is the first stuck-at fault in which the output signal or the input signal of the logic gates LG1, LG2, LGi... LGn is fixed to logic "0". The first single stuck-at fault M0 having only one stuck-at fault in the LSI under test 16 and the logic gates LG1, LG
2, a second stuck-at fault in which an output signal or an input signal of LGn is fixed to a logic "1", and only one stuck-at second fault exists in the LSI under test 16. It is defined as M1.

The failure information propagates through logic gate LGi.
Is defined by fault propagation or fault non-propagation.
ing. When the failure information propagates through the logic gate LGi
Is information indicating failure propagation in the failure information fSa0 and fSa1.
Another flag "1" is given, and the failure information indicates the logic gate LGi.
If not propagated, the failure information fSa0, fSa1
By giving an identification flag “0” indicating failure non-propagation,
To distinguish . For the first single stuck-at fault M0, fS
a0 = 0 or 1 for the second single stuck-at fault M1
Is defined as fSa1 = 0 or 1 ( see FIGS. 5 and 6).

Then, in step P2, the test data DT is supplied to the signal input portion IN of the LSI under test 16.
At this time, the test data DT for simulating the failure of the LSI under test 16, for example, “0, 1, 1, 1” is read by the test data file memory 22 via the CPU 25.

Next, in step P3, the test data DT
Based on each logic gate LG1 = AND circuit, LG2 = OR
Fault information fSa0, fSa1 relating to fault propagation is calculated and stored for each circuit, LG3 = AND circuit. Here, the CPU 25
Performs the following calculations regarding fault propagation. First, the test data DT = "0111" read from the test data file memory 22 is input to the LSI 16 to be tested, and the normal operation of the LSI 16 to be tested is simulated.
The output values of the respective logic gates LG1, LG2, LGi ... LGn in the normal state are obtained (first processing). In the example of FIG. 8A, the output values of the logic gates LG1 to LG3 in the normal state are "0",
It becomes "1" and "1". Further, the CPU 25 targets one of the logic gates LG1 to LG3 and causes one input terminal of the target logic gate LG1 to have an opposite logic to the input value "0" at the normal time of the input terminal. The failure information fSa1 of logic 1 having a value is read from the failure simulation control memory 21 and input, and the input value "1" in a normal state is input to the remaining input terminals of the logic gate LG1 to input the logic gate L.
The operation at Gi failure is simulated, and the output value at failure is obtained (second processing). Then, the CPU 25 compares the output value "1" at the time of failure of the logic gate LG1 with the output value "0" at the time of normal operation. Here, since the output value at the time of failure of the logic gate LG1 has a logic value opposite to the output value at the time of normal operation, an identification flag (hereinafter, a failure propagation flag) indicating that “the failure propagates through the logic gate”. Also called) "1"
Is given to the failure information fSa1. The failure information fSa1 given the identification flag "1" is described as fSa1 = 1. Note that C
When the output value at the time of failure of the logic gate LGi has the same logic value as the output value at the time of normal operation, the PU 25 identifies an identification flag (fault non-propagation flag) indicating that "the failure does not propagate through the logic gate". (Also called) "0" is the failure information fSa1
To be given. Failure information fSa1 with identification flag "0"
Describes that fSa1 = 0. In the present embodiment, in order to simplify the drawing, FIG. 8A to FIG. 8C only when the failure information fSa1 and fSa0 do not exceed the logic gate LGi.
It is decided to fill in (c) (third processing).

In the example of FIG. 8A, the fault information fSa1 assumed for the input net A becomes fSa1 = 1, propagates through the logic gate LG1, and assumes the fault information fSa0 assumed for the input net B.
And fSa1 are fSa0 = 0 and fSa1 = 0, and neither propagates through the logic gate LG2. The logic gate LG1
When the calculation is completed for all the input terminals, the same calculation is performed for the remaining logic gates LG2 and LG3. When calculation is performed for the logic gate LG2, the failure information fSa0 assumed for the input net C is fSa0 = 1, and the logic gate L
Propagate G2. Failure information fSa0 assumed for input net E
And fSa1 are fSa0 = 0 and fSa1 = 0, and neither propagates through the logic gate LG2. Furthermore, the logic gate LG3
Is calculated, the fault information fSa0 assumed for the input net D is fSa0 = 1 and propagates through the logic gate LG3. The failure information fSa0 assumed for the input net F is fSa0
= 1 and propagates through the logic gate LG3. Each logic gate LG based on the test data DT calculated in this way.
The failure information fSa0, fSa1 of 1, LG2, LG3 is stored in the failure information memory 23 via the CPU 25. At this point, it is only known whether or not the assumed failure information fSa0, fSa1 of each logic gate LG1, LG2, LG3 propagates through the logic gate LGi.
Failure information fSa0, f assumed at the input of each logic gate LGi
It cannot be determined whether or not Sa1 has a path that propagates from the input section IN of the LSI under test 16 to its output section OUT. Therefore, in the present embodiment, when the CPU 25 executes the second and third processes for all the input terminals of the logic gates LG1, LG2, LG3 and ends, the next step is executed. That is, in step P4, the identification flag attached to the fault information fSa0, fSa1 assumed for each input net is detected from the signal output unit OUT of the LSI under test 16 toward the signal input unit IN. At this time, the failure information fSa0, fSa1 to which the identification flag is added is the data search editor 2
4 is detected.

For example, it is checked whether or not there is a signal change inside the circuit at a preset failure detection determination time, and the failure information fSa0, fSa1 for each net is output from the signal output unit OUT which becomes the failure detection determination point G. Tracking is started.

Then, in step P5, the failure information fSa0 =
In order to detect whether the logic gates LG1 to LG3 having 1 or fSa1 = 1 are continuous from the input section IN of the LSI under test 16 to the output section OUT, the data search editor 24
Indicates that the identification flag of either of the failure information fSa0 and fSa1 is "1" from the signal output section OUT to the signal input section IN.
, And any one of the identification flags of the failure information fSa0 and fSa1 is “1”, or any one of the identification flags of the failure information fSa0 and fSa1 is “0”. At this time, one of the identification flags of the failure information fSa0, fSa1 is "1" and the failure information fSa0, fSa1.
In the case where the logic gates whose identification flags of 1 are "1" are continuous from the input part IN to the output part OUT (YES), the failure information of the failure point is propagated to the failure determination detection point G, and therefore, step P6 Move to.

If both the identification flags of the failure information fSa0 and fSa1 are "0" (NO), the failure point F
Since the failure information assumed in LT does not propagate to the failure determination detection point G, the process moves to step P7, where failure information fSa0, fSa
1 is interrupted, and it is determined that a failure cannot be detected with this test data DT. In an embodiment of the present invention,
Although the net A has fSa1 = 1, the output of the logic gate LG1, that is, the failure information fSa0, fSa1 of the net E has "0" in both identification flags. In the example of FIG. 8A, the fault propagation path (the portion indicated by the thin line in the figure) from the logic gate LG1 to the logic gate LG2 is not formed. Therefore, the fault information fSa0, fSa from the net E to the signal input unit
The search for Sa1 is interrupted.

As a result, "test data DT =" 0,
1, 1, 1 ", test data DT can be evaluated as" 1 "stuck-at fault of net A cannot be observed at fault detection determination point G. In Step P6, it can be evaluated that "failure information of the nets C and D can be observed by the test data DT". That is, in the test data DT = “0, 1, 1, 1”, the “1” stuck-at fault of the net A cannot be observed, but from the fault detection judgment point G the input nets C, D, E, F are stuck at “0”. It becomes possible to observe failures. In the example of FIG. 8A, the failure information f
The logic gates LG2 and LG3 having Sa0 = 1 are the LS under test.
I16 is continuously arranged from the input part IN to the output part OUT. From this, it can be seen that a fault propagation path (the thick line portion in the figure) that propagates the fault information fSa0 (0 stuck-at fault) assumed to the input nets C, D, E, and F is formed.
As described above, by searching the logic gate having the failure information fSa0 = 1 or fSa1 = 1 from the signal output unit OUT of the LSI under test 16 to the signal input unit IN, it is possible to determine a failure that can be detected by the test data DT. Further, in the last logic gate of the LSI under test 16, the fault information fSa0 =
When 0, fSa1 = 0 is detected, the failure information fSa0,
Since the search for fSa1 is terminated on the spot, it is not necessary to search for wasteful failure information fSa0, fSa1.

The processes of steps P1 to P7 are performed for all faults and all test data DT to be detected. For example, the test data DT in FIG.
When "1" changes to "0101" as shown in FIG. 8B, the output values of the logic gates LG1, LG2, LG3 under normal conditions become "0", "0", "0", and the input net A The fault information fSa1 assumed to be f1 is fSa1 = 1, and the logic gate LG1
To propagate. The failure information fSa0 and fSa1 assumed for the input net B are fSa0 = 0 and fSa1 = 0, and neither propagates through the logic gate LG1. Further, the failure information fSa1 assumed for the input net C becomes fSa1 = 1 and propagates through the logic gate LG2. Failure information fSa assumed for input net E
1 becomes fSa1 = 1 and propagates through the logic gate LG2. Further, the fault information fSa0 and fSa1 assumed for the input net D
Are fSa0 = 0 and fSa1 = 0, and neither propagates through the logic gate LG3. However, the fault information fSa1 assumed for the input net F becomes fSa1 = 1 and propagates through the logic gate LG3. Accordingly, the logic gates LG1 to LG3 having the fault information fSa1 = 1 are continuously arranged from the input unit IN to the output unit OUT of the LSI under test 16, so that the fault information fSa1 (1 stuck-at fault) assumed for the input net A is obtained. It can be seen that a fault propagation path (the thick line in the figure) that propagates is formed.
Further, the test data DT in FIG.
Changes to "0100" as shown in FIG. 8 (c), the normal output values of the logic gates LG1, LG2, LG3 do not change to "0", "0", "0".
The fault information fSa1 assumed for the input net A becomes fSa1 = 1, propagates through the logic gate LG1, and the fault information fSa0 and fSa1 assumed for the input net B are fSa0 = 0, fSa1 = 0.
, And none of them propagates through the logic gate LG1. Also,
The fault information fSa1 assumed for the input net C becomes fSa1 = 1, propagates through the logic gate LG2, and the fault information fSa1 assumed for the input net E also becomes fSa1 = 1, and the logic gate LG2
To propagate. However, the fault information fSa0 and fSa1 assumed for the input net D are fSa0 = 0 and fSa1 = 0, none of which propagates through the logic gate LG3, and the fault information fSa0 and fSa1 assumed for the input net F are also fSa0 =
0, fSa1 = 0, and neither propagates through the logic gate LG3. In the present embodiment, since the logic gate having the failure information fSa0 = 1 or fSa1 = 1 is searched from the output section OUT to the input section IN, FIG.
In the example of (c), the failure information fSa0 = 0 of the logic gate LG3
Moreover, when fSa1 = 0 is detected, it can be immediately detected that the failure propagation path is not formed. Thus, the logic gate LG1 = AND circuit, LG2 = OR circuit, LG3 = A
A failure simulation of the LSI under test 16 in which the ND circuit is incorporated is performed, and information such as a failure detection rate and undetected failures relating to all failure points targeted for failure detection can be obtained. In addition,
This failure simulation result is actually the LSI under test.
When a failure point exists inside the semiconductor device 16 at the time of manufacture, the test data DT can be supplied to confirm the existence of the failure point.

As described above, according to the circuit fault pseudo test method of the first embodiment of the present invention, as shown in the flowchart of FIG. 7, in step P1, the first and second single stuck-at faults M0 are generated. Information fSa0, f indicating failure propagation of M1, M1, etc.
Sa1 is defined, and test data DT is set in step P2.
Is supplied, and in step P3, each of the logic gates LG1, LG
2. Calculates and stores the failure information fSa0, fSa1 related to failure propagation at LG3.

Therefore, a plurality of logic gates LG1, LG2,
If a fault simulation is performed by setting a fault point FLT on the LSI under test 16 incorporating LG3, step P4
And signal output section OUT = fault detection judgment point G to signal input section I
The first failure information fSa0 = 1 or 0 indicating the propagation possibility of the first single stuck-at fault M0 toward the N and the second failure information indicating the propagation possibility of the second single stuck-at fault M1. By performing the detection process of fSa1 = 1 or 0, the LSI under test 16
It becomes possible to easily carry out the failure detection evaluation.

As a result, even if the LSI under test 16 becomes extremely highly integrated and highly dense, failure detection evaluation can be simplified and the design period of the logic gate can be shortened.

FIG. 9 shows a flow chart of the LSI logic design method according to each embodiment of the present invention. In FIG. 9, for example, when developing an ultra-high-integrated logic gate array or the like, first, a logic design is performed in step P1, and then a circuit fault pseudo test process according to the present invention is performed in step P2.

After that, in step P3, a process for judging whether the fault coverage is high or low is performed. At this time, when the failure detection rate is high (YES), the process proceeds to step P5 and the failure simulation is performed. If the fault coverage is low (NO)
In step S4, the process moves to step P4 to add or review the test pattern, and step P2 is executed again.

As a result, although it takes a longer time than the logic simulation, it becomes possible to evaluate the fault coverage with a small computer, and the ultra-high integration logic gate array in the design stage is compared with the conventional example in the test data. DT
Based on the above, the failure detection rate and the like can be easily obtained, and the failure detection evaluation can be easily performed. With this,
It is possible to design logic considering test.

(2) Description of Second Embodiment FIGS. 10 to 16 are explanatory views of a circuit fault pseudo test method according to the second embodiment of the present invention, and FIG. 10 is a process of the circuit fault pseudo test. 11 is a flowchart, and FIGS. 11 to 16 show supplementary explanatory diagrams thereof.

In FIG. 10, the second embodiment differs from the first embodiment in that when the failure information fSa0, fSa1 is calculated and stored in the second embodiment, the scheduled propagation time t associated with the failure information fSa0, fSa1 is calculated.
It includes a storage process of s1 and ts0 and a calculation process of validating the failure information fSa0 and fSa1 whose scheduled transmission times ts1 and ts0 have passed the present time tc.

This is because even if a signal change (hereinafter referred to as an event) occurs in the input net of the logic gate, the event may not occur in the output net D of the normal circuit due to the gate delay time td. The circuit fault pseudo test method according to the embodiment is supplemented. The scheduled transfer time ts1 is the scheduled time at which the "1" stuck-at failure will be transmitted, and the scheduled transfer time ts0 is the scheduled time at which the "0" stuck-at failure will be transmitted.

For example, as shown in FIG.
When 6 is a 3-input AND circuit (hereinafter simply referred to as a 3-input AND circuit) 26, a failure point FLT is set in the input net A, and the scheduled transfer time ts1 at which 1 stuck-at failure is transferred will be explained. For example, in the process flow chart of FIG. 10 which is a subroutine of step P3 of the process flow chart of FIG. 7, first, in step P1, normal / failure circuit case classification (mode) process is performed.

At this time, in the case of a normal circuit (YES),
Move to Step P2. In the case of a faulty circuit (N
For (O), the process proceeds to step P5. Therefore, in the case of a normal circuit (YES), the current time tc = 0 in step P2.
(Hereinafter referred to as event scheduling processing). At this time, in the state transition diagram (a) of the LSI under test shown in FIG. 11, the signal value of the input net (A,
(B, C) = (0, 0, 1) The signal value of the output net D = “0” is calculated and stored (see FIG. 12).

Next, in step P3, the event scheduling process for the current time tc = 5 is performed. At this time,
At time tc = 5 in FIG. 11B, the signal value of the input net B changes from “0” to “1”, and the signal value of the input net is (A, B, C) = (0, 1, 1 ). Note that "1"
When the stuck-at failure is transmitted, the scheduled transfer time ts1 is stored, and when the stuck-at failure is "0", the scheduled transfer time ts0 is stored. At this time, the signal value of the output net D remains "0" and does not change (see FIG. 12).

Next, at step P4, the current time tc = 13
Event scheduling processing according to. At this time, the signal value of the input net C changes from “1” to “0” at the time tc = 13 eight hours after the change of the input net in FIG. A, B,
C) = (0,1,0). At this time, the output net D
The signal value of is still "0" (see FIG. 12).

On the other hand, in the case of a faulty circuit at step P1 (N
For (O), the process proceeds to step P5. Here, 3 inputs A
Assuming that the gate delay time of the ND circuit is td = 10 and the stuck-at-1 fault = sa1 is set in the input net A, the current time tc passes the scheduled transmission time (hereinafter referred to as event schedule time) ts1, ts0. Explain the case where it is and the case where it has not passed.

Therefore, in step P5, the event scheduling process for the current time tc = 0 at which the failure is set is performed. At this time, in the state transition diagram of the LSI under test of FIG. 11A, the signal value (A, B, C) of the input net at time tc = 0, which is the first state, is (1, 0, 1). Is calculated and stored in the same manner as in the normal circuit (see FIG. 13).

Next, in step P6, an event scheduling process relating to the current time tc = 5 is performed. At this time,
At time tc = 5 in FIG. 11B, the signal value of the input net B changes from “0” to “1”, and the signal value of the input net is (A, B, C) = (1, 1, 1 ). At this time, the signal value of the output net D changes to “1”. This allows
The event schedule time ts1 = 15 obtained by adding the gate delay time td = 10 and the current time tc = 5 is stored (see FIG. 13).

Next, at step P7, the current time tc = 13
Event scheduling processing according to. At this time, the signal value of the input net C changes from “1” to “0” at the time tc = 13 eight hours after the change of the input net in FIG. A, B,
C) = (0,1,0). At this time, the output net D
The signal value of is still "0" (see FIG. 13).

Further, in step P8, the current time tc is compared with the event schedule time ts1. At this time, if the current time tc has passed the event schedule time ts1 (YES), the flow shifts to Step P9,
If it has not passed (NO), step P
Move to 10.

For example, when the current time tc has not passed the event schedule time ts1 (NO) as shown in the content transition diagram of the failure information memory of FIG. 13, the event schedule processing is invalidated in step P10.

This is because when the rising delay time td of the previously set logic gate is 10, the output net D
The signal value of “0” changes from “1” to the event schedule when the signal value of the output net D = “1” at the event schedule time ts1 = 15, which is 10 time behind the change of the input net B. It is based on what has been processed.

As a result, since the signal value of the output net D at the current time tc = 13 has not changed, the event schedule processing at the event schedule time ts1 = 15 becomes invalid. Note that FIG. 15 is a content transition diagram of the failure information memory under normal conditions.

When the current time tc has passed the event schedule time ts1 (YES) as shown in the content transition diagram of the failure information memory of FIG. 16, the event schedule processing is validated in step P9. Here, the failure information fSa0, fSa1 related to the event schedule time ts1 and the failure information fSa0, fSa1 related to the current time tc are compared. Further, a calculation process for validating the failure information fSa0, fSa1 in which the event schedule time ts1 has passed the current time tc is performed.

In the state transition diagram (b) of the LSI under test of FIG. 14, this is input at the current time tc = 17 12 hours after the event occurs in the input net B as shown in FIG. 14 (c). Assuming that an event in which the signal value changes from "1" to "0" occurs in the net C, the event occurrence of the input net B in FIG. 14 (b) has already occurred at the current time tc = 17 at this time. The event schedule time of the output net D = 1 set at the time, that is, the scheduled transmission time ts1
= 15 has passed, the previously set failure information fSa0, fSa1 is fSa0, f that the failure is transmitted.
Sa1 = 1 is valid. This is defined as failure information DSa0, DSa1 based on the scheduled delivery time ts1 and ts0 (see FIG. 16).

As described above, according to the circuit fault pseudo test method of the second embodiment of the present invention, the calculation storage process of steps P3 and P6 of the process flowchart of FIG.
The event schedule times ts1 and ts0 related to the failure information fSa0 and fSa1 are stored, and the current time t is set in Step P9.
The calculation processing for validating the failure information fSa0, fSa1 having passed c is executed.

Therefore, when the fault point FLT is set in the 3-input AND circuit 26, for example, even if a signal change (event) occurs in the input net, the output net D of the normal circuit is output.
If no event occurs in the three-input AN
In the case where a signal change is expected to be transmitted at a time after the gate delay time td of the D circuit 26, the current time tc is not the signal generation time of the input net, but the current propagation time ts1, t.
It becomes possible to detect failures that have passed up to s0.

In other words, when the influence of the fault point FLT is transmitted to the output net D after the gate delay time td, it is assumed that the fault information fSa0, fSa1 at that time is transmitted by the fault "DSa0, DSa1 =". 1 ”.

Thus, in the second embodiment, the failure information fSa0, fSa1 is set in consideration of the event schedule time in comparison with the first embodiment, so that the logic gates LG1, LG2, Gate delay time t of LGi ... LGn
It is possible to execute a failure simulation in accordance with an actual failed circuit including d with high accuracy. With this,
As in the first embodiment, it is possible to improve the practicality of the failure detection evaluation.

(3) Description of Third Embodiment FIGS. 17 to 22 are explanatory views of a circuit fault pseudo test method according to the third embodiment of the present invention, and FIG. 17 is a process of the circuit fault pseudo test. It is a flowchart and FIGS. 18-22 has shown the supplementary explanatory drawing.

In FIG. 17, the difference from the first and second embodiments is that in the third embodiment, when the failure information fSa0, fSa1 is calculated and stored, the final failure one cycle before the test data DT is concerned. The latest failure information fSa0, f related to the detection determination time T1
The storage process of the failure information fSa0 and fSa1 up to the failure detection determination time TX in the current cycle of the test data DT and the failure information fSa0 and fSa related to both times T1 and TX.
1 OR operation processing.

Note that, in order to simplify the explanation, this flowchart is based on steps P3 and P of the flowchart of FIG.
The sub-run processing according to No. 4 is shown, and the LSI under test 36 with a flip-flop (hereinafter referred to as FF circuit) circuit is shown.
The failure detection judgment time of is assumed to be set at only one place within one cycle of the test data DT, and the state change is
It is assumed that there is no state transition diagram other than the state transition diagrams (a) and (b) of the LSI under test 21 with an FF circuit.

For example, a buffer circuit B as shown in FIG.
1 to B5, LSI under test consisting of inverters IN1 and IN2
36 includes an FF circuit 36A as shown in FIG. 18,
In the process flow chart of FIG. 17, first, step P
1, the latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before the test data DT of the LSI under test 36 and the arbitrary failure related to the current cycle of the test data DT from the final failure detection determination time T1. The failure information fSa0, fSa1 up to the failure detection determination time TX is stored (see FIGS. 19 and 20).

FIG. 18 shows 27 kinds of outputs for the signal input states XPR (reset), D (data), CK (clock), XCL (clear), internal state M and output state Q of the FF circuit 36A. This is a summary of the states, and shows an output state involving an indefinite value "X" in addition to the input logic signals "1" and "0".

At this time, the LSI under test with the FF circuit of FIG.
In the state transition diagram (a) and the time chart of Fig. 21,
The input net (A,
The failure information fSa0, fSa1 of each net based on the signal values (1, 0, 1, 1) of (B, C, D) is stored in the failure information memory 23.

Further, in the state transition diagram (b) of the LSI under test with the FF circuit of FIG. 20, similarly, the signal value (1) of the input net (A, B, C, D) related to the arbitrary failure detection determination time T2 is also set. , 1, 0, 1) failure information fSa0 of each net based on
fSa1 is stored in the failure information memory 23.

Next, in step P2, the failure information fSa0, fSa1 from the last failure detection determination time T1 to an arbitrary failure detection determination time TX and the latest failure information fSa0, fSa1 relating to the last failure detection determination time T1. Performs a logical sum operation with.

For example, the latest failure information fsa1 and fsa0 at the failure detection determination time T1 and the failure detection determination times T1 to n
The fault information fsa1 and fsa0 is "1" even once during the fault detection determination time T2 related to the + 1st test pattern cycle.
The logical sum is calculated with the failure information fsa1 and fsa0 that have become.

Failure information fsa1 and fsa0 related to this logical sum
Is the final failure detection determination time T2 of the test data DT.
It is defined as failure information Msa1 and Msa0 related to. Similarly, the latest f at the failure detection determination time T1 is stored in the failure information memory 23 during the failure detection determination processing at the failure detection determination time T3.
Fault information Msa1 related to the logical sum of sa1 and fsa0 and the fault information fsa1 and fsa0 that has become “1” even once between the fault detection determination time T1 and the fault detection determination time T3.
Msa0 is stored.

In step P3, the first search processing from the signal output unit OUT of the LSI under test 36 to the FF circuit 36A is performed. At this time, for example, in the state transition diagram (b) of the LSI under test with the FF circuit of FIG. 20, assuming that the failure detection determination process is performed at the failure determination time T2 of FIG. 22B for explaining the detection processing of FIG. 22, the FF circuit 36A retrieves the latest failure information fsa1, fsa0 in the net on the external output terminal side A.

As a result, the stuck-at-1 fault sa1 existing in the nets J and K and the stuck-at-0 fault sa0 existing in the net L can be detected. Further, in step P4, the FF circuit 36
The second search processing from the input section of A to the signal input section IN of the LSI under test 36 is performed. At this time, for example,
22 is a state transition diagram (a) of the LSI under test with FF circuit 20 and assuming that the failure detection determination process is performed at the failure determination time T1 of FIG. 21, the second search process of FIG.
In the diagram (a) for explaining the detection processing of, the FF circuit 36A
For the net on the external input terminal (signal input unit IN) side B, the second search processing for detecting the latest and other than the latest failure information Msa1 and Msa0 held in the failure information memory 23 is performed.

For example, in the time chart of FIG.
Failure detection determination time T related to the n-th test pattern cycle
The latest and non-latest failure information fsa1 and fsa0 held in the failure information memory 23 in No. 1 are searched.

Then, in step P5, the latest failure information fSa0, fSa1 relating to the final failure detection determination time T1 one cycle before the test data DT and the current test data DT from the final failure detection determination time T1. Failure information MSa0, M until an arbitrary failure detection determination time TX related to a cycle is reached
Perform calculation processing to match with Sa1.

The contents of the failure information memory 23 at the end of the failure detection determination process at the failure detection determination time T3 are as follows:
It is used for the failure detection determination process related to the (n + 2) th test pattern cycle.

As a result, the latest failure information fsa1, fsa0 in the net on the external output terminal side A is retrieved, and by checking the failure information fsa1, fsa0, the first
In this embodiment, the 1 stuck-at fault sa1 existing in the undetected net B can be detected.

As described above, according to the circuit fault pseudo-test method of the third embodiment of the present invention, an arbitrary fault detection determination time TX from the last fault detection determination time T1 in step P2 of the flowchart of FIG. Failure information fSa up to
The logical sum operation processing with 0 and fSa1 is performed.

Therefore, the LSI to be tested 36 is provided with the FF circuit 36.
Even if A is included, it changes with time F
Regarding the internal state of the F circuit 36A, for example, the latest failure information fSa0, fSa1 relating to the final failure detection determination time T1 one cycle before the relevant test data DT and the current test data DT from the final failure detection determination time T1 Failure information fSa0, f up to an arbitrary failure detection determination time TX related to the cycle
Assuming that the failure of Sa1 is transmitted even once, "fSa0, fSa1 =
By performing the logical sum operation of
It becomes possible to judge the failure propagation property of the F circuit 36A.

In steps P3 and P4, FF
Failure information fSa0 of the LSI under test 36 including the circuit 36A,
fSa1 is executed by the first and second search processing, and after the detection processing, the latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before the test data DT is determined in step P5. Failure information MSa0, MSa at the final failure detection determination time T2 related to the current cycle of the test data DT
Matches 1

Therefore, depending on one calculation process, F
Even when the influence of the failure of the input net of the F circuit 36A is not reflected in the output net D, the "0" stuck-at fault M0 and the "1" stuck-at fault M1 remaining in the FF circuit 36A are not ignored. The faults M0 and M1 can be detected with good reproducibility.

As a result, the 1 stuck-at fault sa1 existing in the net B, which has not been detected in the first embodiment, can be detected. Therefore, the LSI 36 under test including the flip-flop circuit 36A and the like having the state memory can be detected. It becomes possible to perform a highly accurate failure simulation of.

[0145]

As described above, according to the apparatus of the present invention, the first, second and third storage means, the information detection means and the control means are provided, and each of them is based on the test data of the LSI under test. Failure information calculated regarding failure propagation in the logic gate is stored in the third storage means via the control means,
Failure information based on the failure mode information defined in advance is detected by the information detecting means.

Therefore, the output value at the output point of each logic gate with respect to the test data becomes the failure information which has been defined in advance when the failure is propagated. As a result, the burden on the control means is reduced to the storage processing of the failure information remaining at the input points of the respective logic gates. Further, with respect to the failure transfer from the failure point to the failure detection determination point, the determination of each failure point is not made for each output point of each logic gate, so that a large-capacity memory as in the conventional example is unnecessary.

By storing the expected transfer time relating to the failure information for each logic gate of the semiconductor device under test in the third storage means, a highly accurate failure simulation including the delay time of the logic gate is performed. It becomes possible.

Further, the calculation result based on the latest failure information related to the failure detection determination time of one cycle before the test data and the failure information from the failure detection determination time to the failure detection determination time of the current cycle. Based on the data, it becomes possible to perform a highly accurate failure simulation of the semiconductor device under test including the memory element having the state memory.

As a result, it is possible to reduce the use (occupancy) time of the control means and the memory capacity of the failure information memory as compared with the conventional example. Further, according to the first to third circuit fault pseudo test methods of the present invention, the definition process of the fault information indicating the fault propagation such as the first and second single stuck-at faults, the process of supplying the test data, Failure processing such as storage processing of scheduled time of failure related to failure information, judgment of validity of the failure information based on the current time, and OR operation processing of latest failure information and failure information related to past failure detection determination time I am doing the calculation and memory processing for Hata.

Therefore, when a failure point is set in the LSI under test in which a plurality of logic gates including memory elements are incorporated and a circuit failure simulation is carried out, the first failure detection judgment point is moved toward the signal input section. By detecting the final failure information 1 or 0 indicating the propagation possibility of the single stuck-at fault or any failure information 1 or 0 indicating the propagation possibility of the second single stuck-at fault, the failure is detected. It becomes possible to easily carry out the failure detection evaluation of the LSI under test based on the failure judgment.

Further, based on the storage processing of the scheduled transfer time relating to the failure information, the failure simulation in accordance with the actual failure circuit including the delay time of the logic gate is executed with the processing time of about 5 times that of the logic simulation. It becomes possible.

Furthermore, even when the semiconductor device under test includes a memory element, the validity judgment of the failure information based on the current time, the latest failure information, and the failure information relating to the past failure detection judgment time are performed. It becomes possible to judge the failure propagation property related to the memory element by executing the logical sum operation processing and the like. As a result, it becomes possible to perform a highly accurate failure simulation of the semiconductor device under test including the memory element using a small computer.

As a result, even when there is a demand for manufacturing a semiconductor integrated circuit device having several million gates including a memory element, failure detection and evaluation can be simplified, which contributes to shortening the design period of the logic gate. But big.

[Brief description of the drawings]

FIG. 1 is a principle diagram (1) of a circuit failure pseudo test apparatus according to the present invention.

FIG. 2 is a principle diagram (No. 2) of the circuit fault pseudo test apparatus according to the present invention.

FIG. 3 is a principle diagram of a circuit fault pseudo test method according to the present invention.

FIG. 4 is a configuration diagram of a failure simulation system according to each embodiment of the present invention.

FIG. 5 is an explanatory diagram of contents of a failure mode memory table according to each embodiment of the present invention.

FIG. 6 is an explanatory diagram of contents of a failure information memory table according to each embodiment of the present invention.

FIG. 7 is a process flowchart of a circuit fault pseudo test according to the first embodiment of the present invention.

FIG. 8 is a supplementary explanatory diagram of the circuit fault pseudo test method according to the first embodiment of the present invention.

FIG. 9 is a flowchart of an LSI logic design method according to each embodiment of the present invention.

FIG. 10 is a processing flowchart of a circuit failure pseudo test according to a second embodiment of the present invention.

FIG. 11 is a state transition diagram (part 1) of the LSI under test according to the second embodiment of the present invention.

FIG. 12 is a content transition diagram (part 1) of the failure information memory at a normal time according to the second embodiment of the present invention.

FIG. 13 is a content transition diagram (1) of a failure information memory at the time of failure according to the second embodiment of the present invention.

FIG. 14 is a state transition diagram (part 2) of the LSI under test according to the second embodiment of the present invention.

FIG. 15 is a content transition diagram (part 2) of the failure information memory at the normal time according to the second embodiment of the present invention.

FIG. 16 is a content transition diagram (part 2) of the failure information memory at the time of a failure according to the second embodiment of the present invention.

FIG. 17 is a processing flowchart of a circuit failure pseudo test according to a third embodiment of the present invention.

FIG. 18 is an explanatory diagram of a flip-flop circuit according to a third embodiment of the present invention.

FIG. 19 is a supplementary explanatory diagram of the circuit fault pseudo test method according to the third embodiment of the present invention.

FIG. 20 is a state transition diagram of an LSI under test with an FF circuit according to a third embodiment of the present invention.

FIG. 21 is a time chart illustrating a failure determination time according to the third embodiment of the present invention.

FIG. 22 is an explanatory diagram of a detection process of the LSI under test with the FF circuit according to the third embodiment of the present invention.

FIG. 23 is a configuration diagram illustrating a failure simulation according to a conventional example.

FIG. 24 is a processing flowchart of a comparison / determination editor according to a conventional example.

[Explanation of symbols]

11 ... First storage means, 12 ... Second storage means, 13 ... Third storage means, 14 ... Information detecting means, 15 ... Control means, LG1, LG2, LGi, LGn ... Logic gate, MEM ... Storage element DT: Test data, D1: Control data, Sa0, Sa1: Failure mode information, fSa0, fSa1, DSa0, DSa1, MSa0, MSa1: Failure information, FLT: Failure point, ts1, ts0: Scheduled transmission time, tc ... Current time, td ... Gate delay time, IN ... Signal input section, OUT ... Signal output section.

Claims (10)

(57) [Claims] 1. A device for simulating the propagation of a failure of the logic gate for a semiconductor device under test, which is formed by connecting a plurality of logic gates, wherein an input value of the logic gate is fixed to a logic 1 or a logic 0. First storage means for storing failure information indicating a failure, second storage means for storing test data of the semiconductor device under test, and the test data from the second storage means to the semiconductor device under test A first process of reading out and inputting, simulating a normal operation of the semiconductor device under test to obtain a normal output value of each of the logic gates, and targeting one of the logic gates is performed. From one of the first storage means, failure information of logic 1 or logic 0, which has a logic value opposite to the normal input value of the input terminal, is input to one input terminal of the target logic gate. A second process is performed, in which the output is input and the input value in the normal state is input to the remaining input terminals of the logic gate to simulate the operation of the logic gate at the time of failure to obtain the output value at the time of failure. The output value at the time of failure of the target logic gate obtained by the second processing is compared with the output value at the time of normal operation obtained by the first processing, and the output value at the time of failure of the logic gate is normal. When the logic value is opposite to the output value at the time, it means that "the fault propagates through the logic gate".
When the output value at the time of failure of the logic gate has the same logic value as the output value at the time of normality, identification information indicating that "the failure does not propagate through the logic gate" is added to the failure information of the logic gate. And a control unit that sequentially executes the second and third processes for all the input terminals of the logic gate for each of the logic gates, and the identification information is given by the control unit. The third storage means for storing the generated failure information, and the storage information of the third storage means for the failure information to which the identification information is added, and the “the failure propagates through the logic gate”. Information detecting means for detecting whether or not the logic gate having the failure information to which the identification information indicating that is continuous from the input section to the output section of the semiconductor device under test is provided. Circuit failure Pseudo-test equipment. 2. The third storage means stores scheduled transfer time information that defines the time until a fault reaching the input point of the logic gate reaches the logic gate of the next stage, and the control means. When the failure information when the signal change is applied to the test data is obtained, the failure information whose current time has elapsed is validated with reference to the scheduled transfer time information read from the third storage means. Claim 1 characterized by the above.
The circuit failure simulation test device described. 3. The third storage means stores failure information from a final failure detection determination time of one cycle before the test data to an arbitrary failure detection determination time of a current cycle, and the control means. 3. The circuit fault pseudo test apparatus according to claim 1, wherein the logical OR operation is performed on the fault information read from the third storage unit and the latest fault information at an arbitrary fault detection determination time of the current cycle. . 4. A method of simulating propagation of a failure of the logic gate in a semiconductor device under test having a plurality of logic gates connected, wherein an input value of the logic gate is fixed to logic 1 or logic 0. A first step of creating failure information indicating a failure, inputting test data to the semiconductor device under test, simulating normal operation of the semiconductor device under test, and obtaining output values of the respective logic gates under normal conditions. Processing, targeting one of the logic gates, one input terminal of the target logic gate has a logic 1 or a logic value opposite to the normal input value of the input terminal. The second failure information of 0 is input, the normal input values are input to the remaining input terminals of the logic gate, the operation at the time of failure of the logic gate is simulated, and the output value at the time of failure is obtained. Processing, comparing the output value at the time of failure of the target logic gate obtained by the second processing with the output value at the time of normal operation obtained by the first processing, and If the output value of is the opposite logic value to the output value at the normal time, it indicates that "the fault propagates through the logic gate".
When the output value at the time of failure of the logic gate has the same logic value as the output value at the time of normality, identification information indicating that "the failure does not propagate through the logic gate" is added to the failure information of the logic gate. The third process is performed, and for each of the logic gates, the second and third processes are sequentially executed for all the input terminals of the logic gate, and the failure information to which the identification information is added is searched for. And detects whether or not the logic gate having the failure information to which the identification information indicating that “the failure propagates through the logic gate” is provided is continuous from the input section to the output section of the semiconductor device under test. A circuit failure pseudo test method characterized by the above-mentioned. 5. The failure mode information has a first single stuck-at fault and a second single stuck-at fault, and the first single stuck-at fault sets a failure point in the semiconductor device under test. In this case, the output signal or the input signal of the logic gate is a first stuck-at fault which is fixed at logic “0”, and the first stuck-at fault is present in the semiconductor device under test only once. The second single stuck-at fault is a second stuck-at fault in which an output signal or an input signal of the logic gate is fixed to logic “1” when a failure point is set in the semiconductor device under test. 5. The second stuck-at fault is defined as the case where only one semiconductor device under test exists.
Circuit failure pseudo test method described. 6. The failure information has first failure information and second failure information, and the first failure information is transmitted to the logic gate of the next stage by the first single stuck-at failure. The second failure information is defined as a case where the second single stuck-at failure is
5. The circuit fault pseudo test method according to claim 4, wherein each is defined as a case of indicating whether or not to propagate to a logic gate of a next stage. 7. A signal change is applied to the test data for the failure simulation when the time until the failure reaching the input point of the logic gate reaches the logic gate of the next stage is defined as the scheduled transfer time information. 5. The circuit failure pseudo-testing method according to claim 4, wherein the failure information whose current time has elapsed is validated with reference to the scheduled transfer time information when determining the failure information when the failure occurs. 8. The latest failure information detected at the final failure detection determination time one cycle before the test data when the semiconductor device under test includes a memory element, and the final failure detection determination time. 5. The circuit fault pseudo test method according to claim 4, wherein a logical sum operation is performed from the fault information up to the fault detection determination time of the present cycle. 9. When the semiconductor device under test includes a memory element, a first search from the signal output section of the semiconductor device under test to the memory element and the input section of the memory element is performed. 5. The circuit fault pseudo test method according to claim 4, wherein the second search up to the signal input section of the test semiconductor device is executed. 10. When the semiconductor device under test includes a memory element, after the detection of the failure information, an arbitrary failure detection determination of a current cycle from a final failure detection determination time of one cycle before the test data is performed. 5. The circuit fault pseudo test method according to claim 4, wherein all the fault information up to the time is matched with the latest fault information at the final fault detection determination time of the current cycle of the test data.