JP3145199B2 - Circuit fault pseudo test apparatus and circuit fault pseudo test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Contents] Industrial application field Conventional technology (FIGS. 14 to 17) Problems to be solved by the invention Means for solving the problems (FIGS. 1 and 2) Action Embodiment (FIGS. 3 to 13) Effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit failure simulation test apparatus and a circuit failure test method, and more particularly, to a method for testing a semiconductor device under test (hereinafter referred to as an LSI under test) in which a failure point is set. The present invention relates to an improvement of an apparatus and a method for performing a failure simulation by supplying data.

In recent years, ultra-high integration of semiconductor integrated circuit devices,
In the field of LSI automatic design along with ultra-high density, a failure simulation of an LSI under test in which a logic gate is assembled is being performed using a large computer.

According to this, a fault simulation is performed for each fault on a logic gate including a fault set inside the LSI under test on the basis of test data, so that the fault detection rate and the undetected fault and the like are determined. Information is obtained. Further, a simple circuit failure pseudo test apparatus for performing a failure simulation of an LSI under test in which a plurality of logic gates including a storage element are incorporated has been developed.

However, since the actual operation state of the storage element of the LSI under test has not been sufficiently incorporated in the circuit failure pseudo test, there is a problem that the accuracy of failure detection of a plurality of logic gates including the storage element is reduced. .

Therefore, an apparatus capable of improving the fault detection accuracy of a plurality of logic gates including the storage element while sufficiently considering the actual operation state of the storage element while simplifying the fault detection evaluation. And methods are desired.

[0007]

2. Description of the Related Art FIGS. 14 to 17 are explanatory views according to a conventional example. FIG. 14 is an explanatory diagram of a circuit failure pseudo test apparatus according to a conventional example, FIGS. 15 and 16 are processing flowcharts (parts 1 and 2) of a circuit failure pseudo test, and FIG. 17 is a supplementary explanatory diagram thereof. ing.

For example, a LS under test in which a plurality of logic gates LG1, LG2, LGi...
As shown in the "circuit failure pseudo test device" of the present inventors' patent application (Japanese Patent Application No. 3-193005), a circuit failure pseudo test unit 1 shown in FIG. And a memory unit 2.

The function of the device is, for example, when performing a failure simulation of the LSI under test 12 during design.
A plurality of logic gates LG1 and LG including the storage element MEM based on the control data D, the test data DT, the failure mode information Sa0 and Sa1 defined in advance, and an arbitrarily set failure point.
2. Calculation is performed on the failure propagation at LGi ... LGn.

In this case, the calculation relating to the fault propagation held in the storage element MEM is performed at the scheduled propagation time ts0, fs0, fSa1 for each of the failure information fSa0, fSa1 of the logic gates LG1, LG2, LGi. ts1, the latest failure information fSa0, fSa1 relating to the last failure detection determination time T1 one cycle before the test data DT, and the last failure detection determination time T
1 to failure information fSa0, fSa1 from an arbitrary failure detection determination time TX related to the current cycle of the test data DT.
And failure information MSa0 and MSa1 based on the above.

As a result, it is possible to perform a failure simulation for all the failure points to be detected in the LSI 12 to be detected set in the LSI under test 12, and to obtain information such as the failure detection rate and the undetected failure of the LSI 12 to be tested. can get.

[0012] In addition, for a circuit failure pseudo test method according to a conventional example, for example, an LSI under test incorporating a plurality of logic gates LG1, LG2, LGi ... LGn including a storage element MEM.
In the case of performing the failure simulation of No. 12, as shown in the “simulation test method of circuit failure” previously filed by the present inventors in Japanese Patent Application No. 3-193005, in FIG. Failure mode M0, M1 of LSI 12
Is set and the failure information fSa0, fSa1 indicating the failure propagation is set.

Here, the input net A of the LSI under test 12
A fault point FLT [fSa1 = 1] is set in the
0, M1 and fault information fSa0, fSa1 indicating fault propagation are defined.

Next, in step P2, the test data DT is supplied to the signal input section IN of the LSI under test 12 and then, in step P3, the last failure detection judgment of one cycle before the test data DT of the LSI under test 12 is performed. The latest failure information fSa0, fSa1 at time T1 and failure information fSa0, f from the last failure detection determination time T1 to any failure detection determination time TX according to the current cycle of the test data DT.
The storage process of Sa1 is performed (see FIG. 17A).

At this time, in the time chart of the LSI under test in FIG. 17B, the signal values (1, 0, and 0) of the input net (A, B, C, and D) relating to the last failure detection determination time T1 are shown.
The failure information fSa0, fSa1 of each net based on (1, 1) is stored in the memory unit 2, and the failure detection determination time T
The signal value (1, 1) of the input net (A, B, C, D) according to
Failure information fSa0, fSa1 of each net based on (1, 0, 1)
Is stored in the memory unit 2.

Next, in step P4, the failure information fSa0, fSa1 from the last failure detection determination time T1 to an arbitrary failure detection determination time TX and the latest failure information fSa0, fSa1 relating to the last failure detection determination time T1. And OR operation with For example, the latest failure information f at the failure detection determination time T1
The fault information fsa1 and fsa0 in which the fault information fsa1 and fsa0 have become “1” at least once between sa1 and fsa0 and the fault detection determination time T2 related to the (n + 1) th test pattern cycle from the fault detection determination time T1. Calculate the logical sum with

The failure information fsa1 and fsa0 relating to the logical sum
Is the last failure detection determination time T2 of the test data DT.
Similarly, the memory unit 2 at the time of the failure detection determination processing at the failure detection determination time T3 stores the latest fsa1 and fsa at the failure detection determination time T1.
sa0 and failure detection determination time T1 to failure detection determination time T3
Failure information fsa that has been "1" at least once between
The fault information Msa1 and Msa0 relating to the logical sum with 1 and fsa0 are stored.

In step P5, a first search process from the signal output OUT of the LSI under test 12 to the FF circuit 12A is performed. At this time, assuming that the failure detection determination processing has been performed at the failure determination time T2 in the time chart of the LSI under test in FIG. The latest failure information fsa1 and fsa0 in the net A is searched.

Thus, the stuck-at-1 fault sa1 existing in the nets J and K and the stuck-at-0 fault sa0 existing in the net L can be detected. Further, at step P6, the FF circuit 12
A second search process from the input section A to the signal input section IN of the LSI under test 12 is performed. At this time, FIG.
Assuming that the failure detection / determination processing is performed at the failure determination time T1 in the time chart of the LSI under test described above, the network on the external input terminal (signal input section IN) side B of the FF circuit 12A is obtained by the second search processing. Are the latest and other than the latest failure information Msa1 and Msa held in the failure information memory 23.
A second search process for detecting sa0 is performed.

For example, in the time chart of the LSI under test in FIG. 17B, the latest and non-latest failure information fsa1 and fsa0 stored in the memory unit 2 at the failure detection determination time T1 relating to the nth test pattern cycle. Search for.

Thereafter, in step P7, the latest failure information fSa0, fSa1 relating to the last failure detection determination time T1 one cycle before the test data DT and the current time of the test data DT from the last failure detection determination time T1. Failure information MSa0, M up to a failure detection determination time TX related to the cycle
Perform calculation processing to match with Sa1. Note that the contents of the memory unit 2 at the end of the failure detection determination processing at the failure detection determination time T3 are used for the failure detection determination processing relating to the (n + 2) th test pattern cycle.

Next, in step P8, the failure information fSa0, f
It is determined whether any one of Sa1 is "1" and both fSa0 and fSa1 are "1", or whether both fSa0 and fSa1 are "0" and reach the signal input unit IN.
At this time, if any one of the failure information fSa0, fSa1 is "1" and both fSa0, fSa1 are "1" (YES), the process shifts to Step P9.

If both of the failure information fSa0 and fSa1 reach "0" and reach the signal input section IN (NO), the process shifts to step P10 to interrupt the detection processing of the failure information fSa0 and fSa1. It is determined that “failure cannot be detected with test data DT”. As a result, the latest fault information fsa1 and fsa0 in the net on the external output terminal side A is searched, and by checking the fault information fsa1 and fsa0, the 1 stuck-at fault sa1 existing in the net B can be detected.

[0024]

According to the conventional example, since the actual operation state of the storage element MEM of the LSI under test 12 has not been sufficiently incorporated in the circuit failure pseudo test, a plurality of logic elements including the storage element MEM are required. Gates LG1, LG2,
There is a problem that the accuracy of detecting LGi... LGn is reduced.

That is, in step P 1 of the processing flowchart of FIG. 15, the failure modes M 0,
M1 is defined, and failure information fSa0, fSa indicating the failure propagation thereof.
At the time of setting 1, based on the state where the input part of the storage element MEM of the LSI under test 12 is always fixed to Sa0 or Sa1, it is used as the basis for calculating the fault propagation.

However, the failure of the logic gate LGn from the input section of the storage element MEM to the external signal input section IN, for example, the effect of the stuck-at fault, does not always affect the input section of the storage element MEM. . Thereby, the storage element MEM
Of the fault propagating from the input unit to the output unit of the storage element MEM may differ from the actual operation.

This is because when the logic gate on the input side of the storage element MEM is fixed at Sa0 or Sa1,
Input of the fault information fSa as the effect of the fault.
0, fSa1 propagates. However, the failure of the net from the logic gate on the input side to the external signal input portion IN depends on whether it propagates to the input portion of the storage element MEM or not.

Further, in step P4 of the processing flowchart of FIG. 15, the failure information fSa0, fSa1 from the last failure detection determination time T1 to any failure detection determination time TX and the latest failure detection determination time T1 Failure information fSa
The logical OR operation with 0, fSa1 is performed.

However, the failure information f set at another time
Sa0 and fSa1 are also stored in the same memory unit 2,
This may cause a case where the setting of the fault propagation between the gates is different from the actual operation.

Further, in step P7 of the processing flowchart of FIG. 16, the latest failure information fSa0, f relating to the last failure detection determination time T1 one cycle before the test data DT.
Sa1 and any failure detection determination time TX related to the current cycle of the test data DT from the last failure detection determination time T1.
Is performed to make the failure information MSa0 and MSa1 coincide with each other.

However, the latest failure information fSa0 and fSa1 of the storage element MEM at the failure detection determination time T1 is only stored in the memory unit 2 of the circuit failure simulation test apparatus for one cycle of the test pattern. , The storage element M
Failure information fSa0, f that stays in the internal state of EM for more than one cycle
Sa1 cannot be detected.

This is considered to be a cause of lowering the fault detection accuracy of the plurality of logic gates LG1, LG2, LGi... LGn including the storage element MEM. The present invention has been made in view of the problems of the conventional example, and while taking into account the actual operation state of the storage element while simplifying the fault detection evaluation, a plurality of storage elements including the storage element are provided. It is an object of the present invention to provide a circuit failure pseudo test device and a circuit failure test method that can improve the detection accuracy of a failure of a logic gate.

[0033]

FIG. 1 is a diagram showing the principle of a circuit fault pseudo test apparatus according to the present invention, and FIG. 2 is a diagram showing the principle of a circuit fault test method according to the present invention.

In the circuit failure pseudo test apparatus of the present invention, as shown in FIG. 1, a failure signal propagates from an input portion of a storage element MEM in a semiconductor device under test 12 to an internal state set in the storage element. First failure information indicating whether or not a failure signal propagates from an internal state set in the storage element to an output section of the storage element; and The third failure information and whether at least one of the first failure information, the second failure information, or the third failure information indicates whether a failure signal propagates from the input unit to the output unit of the storage element. Storage means 11 for storing failure mode information (Sa0, Sa1) indicating whether or not there is a failure in the storage element, which is determined based on the one failure information, and the failure mode information (Sa0, Sa1) Based characterized by observing the propagation of failure.

In the above-described circuit failure pseudo test apparatus,
The observation of the propagation of the fault is performed by detecting the fault mode information from the output unit to the input unit of the semiconductor device under test.

[0036]

[0037]

Further, the circuit failure pseudo test method of the present invention
As illustrated in FIG. 1 and FIG.
From the input of the storage element MEM
The first failure information indicating whether the failure signal propagates to the internal state set in the storage element MEM is stored in the storage unit 11, and the failure signal is output from the internal state set in the storage element MEM to the output unit of the storage element. The second indicates whether or not
Is stored in the storage means 11, and third failure information indicating whether or not a failure signal propagates from the input of the storage element MEM to the output of the storage element is stored in the storage means 11. Detecting whether or not there is a failure in the storage element based on at least one of the first failure information, the second failure information, and the third failure information, and providing failure mode information ( (Sa0, Sa1) in the storage means 11, and stores the failure mode information (Sa
0, Sa1), the propagation of a fault is observed from the output to the input of the semiconductor device under test 12.

In the circuit failure pseudo test method of the present invention, at the time of the calculation and storage processing, the internal state M from the data input unit DT of the storage element MEM of the semiconductor device under test 12 is determined in step P3A of the processing flowchart of FIG. And the failure mode information Sa0 and Sa1 propagated to the output section Q of the storage element MEM.
The first calculation storage process for calculating and storing
A second calculation and storage process for calculating and storing the failure mode information Sa0 and Sa1 propagating from the control signal input section CK of the storage element MEM of the semiconductor device under test 12 to the internal state M and the output section Q of the storage element MEM. It is characterized by doing.

Further, in the circuit failure pseudo test method of the present invention, at the time of the detection processing, the storage element M of the semiconductor device under test 12 is determined in step P4A of the processing flowchart of FIG.
It is characterized by performing a process of determining the presence or absence of EM.

In the circuit failure pseudo test method of the present invention, the semiconductor device under test 12
Does not include the storage element MEM, the failure information fSa0, fSa1 is detected from the signal output unit OUT of the semiconductor device under test 12 toward the signal input unit IN in step P4B of the processing flowchart of FIG. Perform the information retrieval process of 1.
If the semiconductor device under test 12 includes the storage element MEM, a second information search process for detecting the failure mode information Sa0 and Sa1 relating to the storage element MEM of the semiconductor device under test 12 in step P4C. To achieve the above object.

[0042]

According to the circuit failure pseudo test apparatus of the present invention, FIG.
As shown in the figure, the failure information fSa0, fSa1, mfSa0, mfSa1,
A storage means 11 comprising first to third storage means 11A to 11C for storing failure mode information Sa0 and Sa1 held in the storage element MEM of the semiconductor device under test 12 based on qfSa0 and qfSa1 is provided.

For this reason, a plurality of logic gates LG1, LG2,
When a fault point FLT is set in the semiconductor device under test 12 into which LGi... LGn are incorporated and a circuit fault simulation is performed, the failure mode information Sa0, Sa1, control data D and test data of the predefined semiconductor device 12 under test are defined. Based on the data DT, the calculation and storage of the failure information fSa0, fSa1 relating to the failure propagation at each of the logic gates LG1, LG2, LGi... LGn and the failure mode information Sa0, Sa1 held in the storage element MEM are performed. The fault detection accuracy of the plurality of logic gates LG1, LG2, LGi... LGn including the storage element MEM can be improved as compared with the conventional example.

For example, failure mode information Sa0 and Sa1 propagating from the input sections DT and CK of the storage element MEM of the semiconductor device under test 12 to the internal state M are stored in the first storage means 11A, and stored from the internal state M. The failure mode information Sa0 and Sa1 propagating to the output section Q of the element MEM are stored in the second storage unit 11.
The failure mode information Sa0 and Sa1 stored in B and transmitted directly from the input sections DT and CK of the storage element MEM to the output section Q of the storage element MEM are stored in the third storage means 11C.

At this time, the failure mode information Sa0, Sa1 held in the storage element MEM of the semiconductor device under test 12 is stored in the storage means 11 for each storage element MEM, or the storage mode of the semiconductor device 12 under test is stored. The failure mode information Sa0 and Sa1 stored in the storage means 11 are written / read / copied based on the state change of the element MEM.

As a result, it is possible to perform a failure simulation of the semiconductor device under test 12 while sufficiently considering the actual operation state of the storage element while simplifying the failure detection evaluation.

Further, according to the circuit fault pseudo test method of the present invention, as shown in the processing flowchart of FIG. 2, each logic gate LG based on the test data DT in step P3.
1, LG2, LGi ... Fn failure information fS on failure propagation at LGn
a0, fSa1 and the failure mode information Sa0, Sa1 held in the storage element MEM are calculated and stored. For example, in step P3A of the processing flowchart of FIG.
The failure mode information Sa0 and Sa1 propagating from the data input section DT of the second storage element MEM to the internal state M and the output section Q of the storage element MEM are calculated and stored (first calculation and storage processing), or received in step P3B. Storage element M of test semiconductor device 12
Failure mode information Sa0, Sa1 propagated from the control signal input CK of the EM to the internal state M and the output Q of the storage element MEM.
Is calculated and stored (second calculation storage processing).

For this reason, a failure of the logic gate LGn from the data input section DT or the control signal input section CK to the external signal input section IN of the storage element MEM of the semiconductor device 12 under test, for example, a stuck-at fault thereof, causes a failure of the storage element MEM. Propagation of a fault that propagates to the storage element MEM, including a case where the fault always affects the data input portion DT, a case where the fault affects the data input portion DT intermittently, and a case where the fault affects the control signal input portion CK. It is possible to simulate and grasp the characteristics in a form closer to the actual operation state.

In step P4, the semiconductor device under test 1
The failure information fSa0, fSa1 and the failure mode information Sa0, Sa1 are detected and processed from the second signal output OUT to the signal input IN.

For example, if the presence / absence of the storage element MEM of the semiconductor device under test 12 is determined in step P4A of the processing flowchart of FIG. 2, if the storage element MEM is not included in the semiconductor device under test 12, In step P4B of the processing flowchart of FIG. 2, the failure information fSa0,
If fSa1 is detected (first information search processing), and the semiconductor device under test 12 includes the storage element MEM,
In step P4C, the storage element MEM of the semiconductor device under test 12
Is detected (second information search process).

For this reason, the data input section D of the storage element MEM
Since the failure of the logic gate LGn from T or the control signal input unit CK to the external signal input unit IN is held in the storage element MEM, the data input unit DT of the storage element MEM or the control signal input unit CK to the storage element MEM By searching for the failure mode information Sa0 and Sa1 propagating to the output unit Q, the memory device MEM is included in the semiconductor device under test 12 as in the conventional example. It is possible to omit a search process from the data input unit DT and control signal input unit CK of the MEM to the signal input unit IN of the semiconductor device under test 12.

Thus, as compared with the conventional example, the storage element MEM
, It is possible to perform a highly accurate failure simulation of the semiconductor device 12 under test.

[0053]

Next, an embodiment of the present invention will be described with reference to the drawings. FIGS. 3 to 13 are diagrams illustrating a circuit fault pseudo test apparatus and a circuit fault test method according to an embodiment of the present invention, and FIG. 3 is a configuration diagram of a fault simulation system according to the embodiment of the present invention. 4 and 5 show supplementary explanatory diagrams thereof.

For example, an apparatus for simulating a failure of a semiconductor device under test (hereinafter referred to as LSI under test) 12 incorporating a plurality of logic gates LG1 to LG4 as shown in FIG. Simulation control memory 21, test data file memory 22, failure information memory 23, data search editor 24, CPU 2
5, a display 26, a keyboard 27, and a system bus 28 for transmitting data therebetween.

That is, the failure simulation control memory 21 stores the failure mode information Sa0, Sa1, the failure information fSa0, fSa1, mfSa0, mfSa1, qfSa0, q of the LSI under test 12 defined in advance based on the failure modes M0, M1.
fSa1 and control data D are stored.

The test data file memory 22 stores test data DT for performing a failure simulation of the LSI under test 12. The failure information memory 23 is an embodiment of the storage unit 11 and stores failure mode information Sa0 and Sa1 held in the storage element MEM of the LSI under test 12. For example, the failure information memory 23 stores
Failure mode information S held in storage element MEM of SI12
a0 and Sa1 are stored for each storage element MEM.

In the failure information memory 23, a PM table 23A (hereinafter also simply referred to as PMTBL), an MQ table
23B (hereinafter simply referred to as PQTBL) and PQ table
23C (hereinafter simply referred to as MQTBL) is provided.

The PMTBL is an example of the first storage means 11A, and the data input section DT of the storage element MEM of the LSI under test 12 is based on preset failure information mfSa0 and mfSa1.
And a memory area for storing failure mode information Sa0 and Sa1 propagated from the control signal input unit CK to the internal state M.

MQTBL is an example of the second storage means 11B, and based on failure information qfSa0 and qfSa1 set in advance, failure mode information Sa0, which propagates from the internal state M of the storage element MEM to its output Q. Sa1 is stored.

MQTBL is an example of the third storage means 11C, and failure mode information Sa0, Sa1 which propagates directly from the input section of the storage element MEM to its output section Q based on preset failure information mfSa0, mfSa1. Is a memory area for storing. The PMTBL, MQTBL and MQTBL are written / read / copied based on a change in the state of the storage element MEM of the LSI under test 12.

The data search editor 24 outputs failure information mfSa0, mfSa1, qfSa0, qfSa1 relating to the storage element MEM.
And fault information fSa0, fSa1 calculated for the fault propagation at each of the logic gates LG1, LG2, LGi... LGn.

The CPU 25 controls the input and output of the failure simulation control memory 21, the test data file memory 22, the failure information memory 23, the data search editor 24, the display 26 and the like.

The display 26 displays the display data D3.
The LSI 12 to be tested is displayed during the design based on the above. The keyboard 27 is used by an operator or the like to input input data D2 related to the failure point FLT when performing a failure simulation. For example, the logic gate LG1
The fault point FLT is set to the signal input unit IN of the first embodiment.

FIGS. 4A to 4C are explanatory diagrams of the failure information held in the storage element according to the embodiment of the present invention. 4A, the failure mode information Sa0 and Sa1 stored in the storage element MEM have different storage contents due to the influence of a failure caused by the data input unit DT and the control signal input unit CK.

That is, the logic gate preceding the memory element MEM is a normal circuit, and its signal value is
, Failure information fSa0, fSa1 = 0, mfSa0 = 0, m
fSa1 = 1 is set, and the fault information fSa0 = 0, fSa1 = 1, mfSa0 = 0, mfSa1 =
When 1 is set, failure mode information Sa0 and Sa1 are set in each of the input units DT and CK and the internal state M, and when this is calculated, the failure propagation information of the storage element MEM is shown in FIG.
Is obtained.

Here, if the output value of the output section Q of the storage element MEM is different from the output value of the normal circuit connected in front of the storage element MEM, the failure information mfSa0, m
fSa1, qfSa0, and qfSa1 are set to "1", and if the signal value of the internal state M is different from that of the normal circuit, only the failure information mfSa0 and mfSa1 relating to the storage element MEM is set to "1".

This is because the memory element M shown in FIG.
The effect of the failure of the logic gate in the previous stage of EM is
This may be caused by the control signal input unit CK. Note that the failure of the logic gate in the preceding stage of the storage element MEM is caused by the same timing as in the normal circuit at the data input section DT
→ internal state M → output section Q → external output section OUT (the influence of delay is not considered).

When the influence of the failure of the logic gate at the preceding stage of the storage element MEM is caused via the control signal input unit CK, three failure propagation states are considered as shown in FIG.

That is, in FIG. 4C, when data is taken into the memory element MEM via the control signal input unit CK or when it is output, the influence of the failure is controlled by the same timing as in the normal circuit. At the time of output, the signal propagates from the internal state M to the output section Q at a timing different from that of the normal circuit.

The influence of the fault is transmitted to the control signal input unit CK at a timing different from that of the normal circuit.
At the time of the output, it propagates from the internal state M to the output section Q at the same timing as the normal circuit. Further, the influence of the fault is propagated to the control signal input unit CK at a timing different from that of the normal circuit, and at the time of its output, it propagates from the internal state M to the output unit Q at a timing different from that of the normal circuit. State is possible.

Therefore, the failure mode information Sa0 and Sa1 propagating from the input section of the storage element MEM to the internal state M are
The failure mode information Sa0 and Sa1 stored in the BL and propagated from the internal state M of the storage element MEM to the output Q thereof are stored in the MQTBL. Further, the failure mode information Sa0 and Sa1 are directly transmitted from the input of the storage element MEM to the output Q thereof. Propagating failure mode information Sa0,
By storing Sa1 in PQTBL, the storage element MEM
The effect of a fault propagating through the input unit can be searched by the fault detection determination time.

As described above, according to the failure simulation system according to the embodiment of the present invention, as shown in FIG. 3, a failure simulation control memory 21, a test data file memory 22, a failure information memory 23, a data search editor 24, The failure information memory 23 includes a PMTBL, a PQTBL, and an MQTBL.

For this reason, a plurality of logic gates LG1, LG2,
LGi ... A failure point F is present in the LSI under test 12 in which LGn is incorporated.
When performing circuit failure simulation by setting LT,
Failure mode information Sa of the LSI under test 12 defined in advance
0, Sa1, the control data D, and the test data DT, the failure information fSa0, fSa1 relating to the failure propagation at each of the logic gates LG1, LG2, LGi... LGn and the failure information fSa0, fSa1, held in the storage element MEM. mfSa0, mfSa1, qfSa0,
By performing the calculation storage processing of qfSa1, the storage element MEM
., LGn, the plurality of logic gates LG1, LG2, LGi... LGn can be improved as compared with the conventional example.

For example, a plurality of logic gates LG1, LG2, L
Gi… LGn built-in LSI under test 12 with fault point FLT
Is set and the failure simulation is performed, the failure mode information Sa0, Sa1 of the LSI under test 12 defined in advance is set.
Is stored in the failure simulation control memory 21, and test data DT for performing a failure simulation of the LSI under test 12 is stored in the test data file memory 22.

Further, the failure information fSa0, fSa1 output from each of the logic gates LG1, LG2, LGi... LGn based on the test data DT is stored in the fourth storage means of the failure information memory 23 via the CPU (see FIG. Failure information (fSa0, fS
a1, mfSa0, mfSa1, qfSa0, qfSa
1) is detected by the data search editor 24.

In FIG. 5A, for example, the input signals of the input nets A, B, C, and D of the LSI under test 12 change from (0, 1, 1, 1) to (0, 1, 1, 0). ), The failure information fSa0, fSa1 of each net and the failure information fSa0, fSa1, mfSa held in the storage element MEM.
0 and mfSa1 are shown in FIG. 5A, and if a fault point has been set before the search processing, the internal state M from the data input section DT and the control signal input section CK of the storage element MEM of the LSI under test 12 will be described. Mode information H (SaO), G (SaO), and D (SaO) of nets D, H, and G propagated to PMTBL
Is stored.

Since the input section of the storage element MEM has changed, the failure mode information H (S) stored in the PMTBL with the internal state M as the observation point for each input section.
a), G (SaO), and D (SaO) search are started. At this time, the failure mode information stored in the PMTBL after the search processing indicates H
(Sa1), E (Sa1), A (SaO), G (SaO, Sa
1), D (SaO, Sa1). In the case of the failure mode information SaO, Sa1 relating to the data input unit DT,
Failure mode information H (SaO) stored in PMTBL
Is cleared once.

In FIG. 5B, it is assumed that the input signals of the input nets A, B, C, and D have changed from (0, 1, 1, 0) to (0, 1, 1, 1). For example, FIG. 5B shows the fault information fSa0, fSa1 of each net and the fault information qfSa0, qfSa1 relating to the storage element MEM,
The failure mode information G (SaO) and D (SaO) of the nets G and D transmitted from the data input section DT and the control signal input section CK of the twelve storage elements MEM to the internal state M are stored in the MQTBL.

Since there is a change in the input section of the storage element MEM, the output section Q of the storage element MEM is changed for each input section.
, The search for the failure mode information G (SaO) and D (SaO) stored in the PMTBL is started. At this time, the failure information qfSa1 of the internal state M is, for example,
When it becomes "1", the failure mode information G (SaO) and D (SaO) stored in the PMTBL are copied to the PQTBL.

Thus, the first fault information fSa0 = 1 or 0 indicating the possibility of transmission of the single stuck-at fault M0 from the signal output OUT to the signal input IN, and the transmission of the single stuck-at fault M1 can be performed. A fault simulation of the LSI under test 12 in which the actual operation state of the storage element is sufficiently taken into consideration while simplifying the fault detection evaluation by performing the detection processing of the second fault information fSa1 = 1 or 0 indicating the fault property. It becomes possible to do.

Next, a circuit failure pseudo test method according to an embodiment of the present invention will be described while supplementing the operation of the apparatus. 6 and 7 are processing flowcharts (parts 1 and 2) of the circuit failure pseudo test according to the embodiment of the present invention, and FIGS. 8 and 9 are supplementary explanatory diagrams of the fault propagation caused by the data input unit (part 1). 1, 2), and FIGS. 10 to 12 are supplementary explanatory diagrams (parts 1 to 5) of the fault propagation caused by the control signal input unit.
FIG. 13 shows an example of the configuration of the LSI under test and an explanatory diagram of the failure information search.

For example, the test LS in which the storage element MEM is incorporated in the logic gates LG1 to LG5 as shown in FIG.
In the case of performing the failure simulation of I12, in FIG. 6, failure information fSa0, which indicates failure propagation by defining failure modes M0 and M1 of the LSI under test 12 in step P1 in advance.
A setting process of fSa1, mfSa0, mfSa1, qfSa0, qfSa1 is performed. In the embodiment of the present invention, the LSI under test 12
A fault point FLT [fSa1 = 1] is set in the input net B of FIG.

Here, failure modes M0,
M1 is classified into two single stuck-at faults. The single stuck-at fault M0 is generated when the fault point FLT is set in the LSI under test 12 and the logic gates LG1, LG2, LGi,.
n whose output signal or input signal is fixed to logic “0”.
Of the LSI under test 1
2 means a failure mode that exists only once.

For example, the first stuck-at fault is the logic gate LGi
Is a mode in which the output value is fixed to logic "0", and this failure mode information is defined as SaO. Further, fSaO is failure information indicating the propagation property of the single stuck-at fault M0. For example, a case where the single stuck-at fault M0 does not propagate to the next-stage logic gate LGi is defined as fSaO = 0, and a case where the single stuck-at fault M0 propagates to the next-stage logic gate LGi is defined as fSaO = 1. Define.

Further, the single stuck-at fault M1 is the LS under test
When the fault point FLT is set in I12, the logic gate L
This is a second stuck-at fault in which the output signal or input signal of G1, LG2, LGi... LGn is fixed to logic "1", and refers to a failure mode in which only one second stuck-at fault exists in the LSI under test 12. For example, the output value of the logic gate LGi is logic “1”.
The failure mode information is defined as Sa1.

Further, fSa1 is failure information indicating the propagation property of the single stuck-at fault M1. For example, a case where the single stuck-at fault M1 does not propagate to the next-stage logic gate LGi is defined as fSa1 = 0, and a case where the single stuck-at fault M1 propagates to the next-stage logic gate LGi is defined as fSa1 = 1. Define. It should be noted that control data D such as predefined failure mode information Sa0 and Sa1 of the LSI under test 12 and first and second failure information fSa0 and fSa1 are stored in the failure simulation control memory 21.

The process of defining the fault information mfSa0, mfSa1, qfSa0, qfSa1 indicating the fault propagation related to the storage element MEM is performed for the single stuck-at fault M0 by the data input section DT and the control signal input section of the storage element MEM. The fault information indicating the propagability from CK to the internal state M is defined as mfSa0 = 1 or 0. Further, for the single stuck-at fault M1, fault information mfSa1 = 1 indicating the propagating property from the data input unit DT or the control signal input unit CK of the storage element MEM to the internal state M.
Or, it is defined as 0.

Further, with respect to the single stuck-at fault M0, the fault information indicating the propagation from the internal state M to the output unit Q is q
fSa0 = 1 or 0, and for a single stuck-at fault M1, fault information indicating the propagation from the internal state M to the output unit Q is defined as qfSa1 = 1 or 0, respectively.

Next, in step P2, a process of supplying test data DT to the signal input section IN of the LSI under test 12 is performed.
At this time, test data DT for performing a failure simulation of the LSI under test 12, for example, “0, 1, 1, 1” is read by the test data file memory 22 via the CPU 25.

Next, in step P3, a selection calculation process is sequentially performed on the storage element MEM and the logic gate LGi of the LSI under test 12 from the signal input section IN to the signal output section OUT. At this time, when performing the calculation and storage process related to the logic gate LGi (NO), the process proceeds to step P4, and when performing the calculation and storage process related to the storage element MEM (YES), the process proceeds to steps P5 and P6. I do.

For example, in the case of performing the calculation and storage processing relating to the logic gate LGi (NO), the failure information fSa0 and fSa1 relating to the failure propagation is calculated and stored in each of the logic gates LG2 to LG5 based on the test data DT in step P4. To process. At this time, each of the logic gates LG1,
The failure information fSa0, fSa1 calculated by LG2, LG3 is
The stored information is stored in the failure information memory 23 through the memory 25.

If the calculation and storage processing relating to the storage element MEM is to be performed (YES), in step P5, for example, a failure calculation of a failure propagation property caused by the data input section DT of the storage element MEM is performed. Here, failure mode information Sa0, Sa1 propagated from the data input section DT of the storage element MEM of the LSI under test 12 to the internal state M and the output section Q of the storage element MEM.
(First calculation storage processing).

In FIG. 8A, in the initial state, PMTBL and MQTBL in the failure information memory 23 are cleared, and when the failure mode information Sa0 and Sa1 of the storage element MEM is copied (traced), the LSI under test 12 Storage element M
The failure mode information Sa0 and Sa1 propagating from the data input section DT of the EM to the internal state M propagates from the DT → M → Q → external output OUT at the same timing as the signal propagation of the normal circuit.

Therefore, the timing at which the storage element MEM of the normal circuit takes in the signal value of the data input section DT and the fault point FLT
Is set, the timings at which the failure mode information Sa0 and Sa1 propagate from the data input unit DT to the internal state M are the same.

It should be noted that the PMTBL
After clearing the failure mode information Sa0 and Sa1, the logic circuit LG3 performs a search (hereinafter referred to as a back trace) on the signal input section IN, and outputs the failure mode information Sa0 and Sa1 transmitted from the data input section DT to the internal state M. Stored in PMTBL.

In FIG. 8C, the storage element MEM
Are propagated from the internal state M to the output unit Q of the normal circuit, the failure mode information Sa0, Sa0,
The timing at which Sa1 propagates to the output unit Q is the same as the timing at which the failure mode information Sa0, Sa1 propagates to the internal state M propagates to the output unit Q (the effects of the delay are not considered).

Therefore, when the internal state M of the normal circuit is output, the failure mode information Sa0 and Sa1 stored in the PMTBL are copied to the MQTBL as shown in FIG. 8C. As a result, the failure mode information Sa0 and Sa1 propagates from the data input unit DT to the output unit Q.

When the failure mode information Sa0, Sa1 propagates to other than the data input section DT, for example, a preset,
The failure mode information S is input to the control signal input section CK such as a clear pin.
When a0 and Sa1 are propagated, the failure mode information Sa0 and Sa1 propagated to the internal state M are cleared.
Clear the contents of MTBL and MQTBL.

Returning to the processing flow chart of FIG. 6, after that, in step P6, a fault propagation fault due to the control signal input portion CK of the storage element MEM is calculated. Here, the internal state M and the output Q of the storage element MEM of the storage element MEM of the LSI under test 12 are transmitted from the control signal input section CK of the storage element MEM.
Of the failure mode information Sa0 and Sa1 propagated to the second memory (second calculation storage processing).

In FIG. 10A, in the initial state, PMTBL, PQTBL, M
QTBL is cleared. Further, the failure mode information Sa0 and Sa1 propagating from the control signal input section CK of the storage element MEM of the LSI under test 12 to the internal state M are different between the normal circuit and the failed circuit.

For example, in FIG.
FIG. 11 shows a case where the control signal input unit CK of the EM changes.
As shown in the test pattern clear cycle time chart of (a), at time A, failure mode information Sa0, Sa1 (failure A) propagates from an input pin other than the data input unit DT to the internal state M, and the storage element MEM thereof. Trace every time,
If the failure mode information Sa0, Sa1 propagates from the input pins other than the data input unit DT to the internal state M even at the next time B, the failure mode information Sa0, Sa1 stored in the PMTBL at the time A (fault A) Is not cleared, and failure mode information Sa0, Sa1 (failure B) to be stored in PMTBL at time B is simultaneously stored in PMTBL (overwriting).
I do.

The stored failure mode information Sa0, Sa1
(Fault A + Fault B) is cleared by the failure mode information Sa of the internal state M of the normal circuit in FIG.
Since 0 and Sa1 are the times C when they propagate to the output unit Q,
From the time D to the time C, the failure mode information Sa0 and Sa1 propagating to the internal state M is stored in the PMTBL until the time C.

In FIG. 11B, the state of propagation from another control signal input portion PR to the internal state M of the storage element MEM is described from the control signal input portion CK of the storage element MEM of the LSI under test 12 to the internal state. Since the failure mode information Sa0, Sa1 propagating to M differs between the normal circuit and the failure circuit, the failure mode information Sa0, Sa1 propagating to the other control signal input unit PR is stored in the PQTBL. At this time, the failure mode information Sa0 and Sa1 already stored are cleared.

Further, in FIG. 12A, the storage element M
As for the state propagating from the internal state M of the EM to the output section Q, the failure mode information Sa0 and Sa1 stored in the PMTBL are output to the MQTBL when the internal state M of the normal circuit is output, as in the case of the data input section DT. Make a copy at
The clearing operation of the stored contents is different from the case of the data input section DT, in which the failure mode information Sa0 and Sa1 stored in the PMTBL are simultaneously cleared. As a result, the failure mode information Sa0 and Sa1 propagates from the control signal input unit CK or another control signal input unit PR to the output unit Q.

Returning to the processing flowchart of FIG. 6, at step P7, the storage element M
Based on the determination processing of the presence / absence of EM, information search processing of failure information fSa0, fSa1, mfSa0, mfSa1, qfSa0, qfSa1 of the LSI under test 12 is sequentially executed from the signal output unit OUT to the signal input unit IN.

At this time, if the storage element MEM is not included in the information search area (NO), the processing shifts to Step P8,
If the storage element MEM is included therein (YES), the flow shifts to Step P9.

For example, if the storage element MEM is not included in the information retrieval area (NO), the LS
Detection processing of the failure information fSa0, fSa1 is performed from the signal output OUT of I12 to the signal input IN (first information search processing). At this time, the failure information f based on the definition process
Sa0 and fSa1 are detected by the data search editor 24.

At this time, it is checked whether or not a signal change exists in the circuit at a preset failure detection determination time, and failure information fSa0, fSa1 is output for each net from a signal output unit OUT serving as a failure detection determination point. Tracking is started. For example, when the observation point is set to the external signal output unit B in the configuration example of the LSI under test shown in FIG. The fault information fSa0, fSa1 is detected from the logic circuit LG4 → LG5 → signal input unit IN.

Thereafter, the flow shifts to step P10, where any of the failure information fSa0, fSa1 is "1" and both fSa0, fSa1 are "1", or both fSa0, fSa1 are "0" and the signal input A determination process is performed to determine whether or not to reach the unit IN. At this time, if any one of the failure information fSa0, fSa1 is "1" and both fSa0, fSa1 are "1" (YES), the routine goes to Step P12.

If both of the failure information fSa0 and fSa1 reach "0" and reach the signal input unit IN (NO), the flow shifts to step P13 to interrupt the detection processing of the failure information fSa0 and fSa1. It is determined that “failure cannot be detected with test data DT”.

In Step P12, it is determined that "the influence of the fault point FLT can be observed by the test data DT". That is, the test data DT shown in FIG.
“0, 1, 1, 1” makes it possible to observe “0” stuck-at faults or the like of the input nets A, B, C, D from the fault detection determination point.

If the memory element MEM is included in step P7 (YES), the LSI under test 1
The failure mode information Sa0 and Sa1 relating to the second storage element MEM are detected (second information retrieval processing). Here, in FIG. 9A and FIG. 13, regarding the failure caused by the data input unit DT of the storage element MEM, the signal output unit OUT of the LSI under test 12
, The failure information fSa0, fSa1, mfSa0, mfSa1 is tracked.

In FIG. 9B and FIG. 13, when the LSI under test 12 includes two storage elements MEM1 and MEM2, when the storage element MEM1 of the LSI under test 12 is traced, When passing through the storage element MEM2,
The backtrace from the other storage element MEM2 to the signal input unit IN is not performed, and each of the PMTBs of the other storage element MEM2 is not traced.
Faults E stored in L, MQTBL, PQTBL,
B and C are stored in PMTBL, MQTBL, and P of the storage element MEM1.
Overwrite failure A stored in QTBL.

Further, in the case where the data passes through the storage element MEM in step P11, the failure mode information Sa is stored in the MQTBL.
It is confirmed whether 0 and Sa1 are stored. At this time, if the failure mode information Sa0 and Sa1 are stored in the MQTBL (YES), the back trace from the storage element MEM to the signal input unit IN is not performed, and the failure mode stored there is not performed. The information Sa0 and Sa1 are directly set as detection failures.

Further, in FIG. 12B, as for the failure caused by the control signal input portion CK and the reset terminal PR, the storage element MEM is used as in the case of the data input portion DT.
Thereafter, the back trace to the signal input section IN is not performed,
The failure mode information Sa0 and Sa1 stored in the MQTBL and PQTBL are directly detected failures.

Therefore, the failure mode information Sa is stored in the MQTBL.
If 0 and Sa1 are stored, it is determined in step P12 that "the influence of the failure point FLT can be observed by the test data DT", and the failure mode information Sa0 and Sa1 is set to M.
If it is not stored in the QTBL (NO), the process shifts to step P13 to interrupt the process of detecting the failure information fSa0, fSa1, and determines that "failure cannot be detected with the test data DT".

Thereafter, in step P14, the LSI under test 12
It is determined whether or not the failure calculation has been completed for all the circuits. At this time, if the failure calculation has not been completed for all the circuits (NO), the process returns to step P7 to execute steps P8 to P13, respectively, and if all of them have been completed (YES), the circuit failure has occurred. The dummy test ends.

As a result, it is possible to perform a failure simulation of the LSI under test 12 in which the memory elements MEM are included in the logic gates LG1 to LG5. Information is obtained.
It should be noted that this failure simulation result indicates that the existence of a failure point can be confirmed by supplying the test data DT when a failure point exists inside the LSI under test 12 when it is actually manufactured. It becomes possible.

As described above, according to the circuit failure pseudo test method according to the embodiment of the present invention, as shown in the processing flowchart of FIG. 6, in step P4, based on the test data DT, each of the logic gates LG1, LG2, LGi: Failure information fSa0, fSa1 relating to failure propagation at LGn and steps P5, P6
In the process of calculating and storing the failure mode information Sa0 and Sa1 held in the storage element MEM, for example, in step P5, the data input section DT of the storage element MEM of the LSI under test 12 outputs the internal state M and the output section of the storage element MEM. The failure mode information Sa0 and Sa1 propagating to the Q are calculated and stored (first calculation and storage processing), or the internal state M and the storage state of the storage element MEM of the storage element MEM of the LSI under test 12 are transmitted from the control signal input unit CK of the storage element MEM of the LSI under test 12 in step P6. Failure mode information Sa propagated to the output unit Q
0 and Sa1 are calculated and stored (second calculation storage processing).

Therefore, the memory element M of the LSI under test 12
If a failure of the logic gate LGn from the data input section DT or the control signal input section CK of the EM to the external signal input section IN, for example, its stuck-at fault always affects the data input section DT of the storage element MEM, this is If it ’s intermittent,
Including the case of affecting the control signal input unit CK,
It is possible to simulate and grasp the propagability of a fault that propagates to the storage element MEM in a manner closer to the actual operation state.

At the failure detection determination time, the L
The failure information fSa0, fSa1 and the failure mode information Sa0, Sa1 are detected and processed from the signal output OUT of the SI 12 to the signal input IN.

For example, when the presence or absence of the storage element MEM of the LSI under test 12 is determined in step P7 of the processing flowchart of FIG.
Is not included, the test target L
Failure information fSa0, fSa1 is detected from signal output OUT of SI12 toward signal input IN (first information search processing).
Is done.

If the LSI under test 12 includes the storage element MEM, the LSI 12 under test
Failure mode information Sa0, Sa1 held in the storage element MEM
Is detected (second information search process).

For this reason, the data input section D of the storage element MEM
Since the failure of the logic gate LGn from T or the control signal input unit CK to the external signal input unit IN is held in the storage element MEM, the data input unit DT of the storage element MEM or the control signal input unit CK to the storage element MEM By retrieving the failure mode information Sa0 and Sa1 propagating to the output section Q, the data input of the storage element MEM of the LSI under test 12 is performed in a case where the storage element MEM is included in the LSI under test 12 as in the conventional example. It is possible to omit a search process from the section DT or the control signal input section CK to the signal input section IN of the LSI under test 12.

For example, in FIG. 13, when the observation point is set to the external signal output unit B, the LSI under test 12 is set in accordance with steps P8 and P10 of the processing flowchart.
The fault information fSa0, fSa1 is detected from the external signal output section B to the logic circuit LG4 → LG5 → signal input section IN.

In the case where the observation point is set to the external signal output unit A and the failure detection relating to the logic circuit LG1 is performed, the logic circuits LG2 to LG5 are further subjected to steps P8 and P10 in the processing flowchart. For such failure detection, the storage element MEM is performed according to steps P9 and P11.
The information retrieval process of MQTBL and PQTBL according to.

Note that, for the failure detection related to the logic circuits LG2 and LG4, information retrieval processing of the failure information fSa0 and fSa1 is performed in accordance with steps P8 and P10, and for the failure detection related to the logic circuit LG3, the processing proceeds to steps P9 and P11. Therefore, MQTBL or PQTB to be held by the storage element MEM2
An information search process of the failure mode information Sa0 and Sa1 stored in L is performed. Also, for the logic circuit LG5, step P
8, P10, and failure mode information Sa0, Sa1 stored in MQTBL or PQTBL to be held by the storage element MEM2 according to steps P9, P11.

As a result, the failure mode information Sa0 and Sa1 propagated at an arbitrary failure detection determination time is stored in, for example, PM
Since the data is copied from the TBL to the MQTBL, it is possible to set the fault propagation between the gates simulating the actual operation state, and from the final failure detection determination time as in the conventional example to an arbitrary failure detection determination time. Fault information fSa0, fSa1 between
And the latest failure information fSa0,
The OR operation with fSa1 can be omitted.

The storage element M related to the failure detection determination time
The latest failure information fSa0, fSa1 of EM is not only for one cycle of the test pattern, but also for times D, A, B,
The failure mode information Sa0 and Sa1 relating to C are PMTBL and PQ.
The failure information fSa that is stored in the internal state of the storage element MEM for at least one cycle because it is stored in the TBL and the MQTBL.
It is possible to search for information of 0, fSa1.

For this reason, the latest failure information fSa relating to the last failure detection determination time one cycle before the test data DT.
This eliminates the need for a calculation process that matches 0, fSa1 with the failure information MSa0, MSa1 as in the conventional example from the last failure detection determination time to any failure detection determination time according to the current cycle of the test data DT. Become.

Thus, as compared with the conventional example, the storage element MEM
, It is possible to perform a highly accurate failure simulation of the LSI under test 12.

[0132]

As described above, according to the circuit failure pseudo test apparatus of the present invention, the first to third memories for storing the failure mode information held in the storage element of the semiconductor device under test based on the failure information. Is provided.

For this reason, when a failure point is set in a semiconductor device under test in which a plurality of logic gates are incorporated and a circuit failure simulation is performed, failure mode information, control data and test data of the semiconductor device under test defined in advance are set. Based on the data, calculate and store failure information relating to failure propagation in each logic gate and failure mode information held in a storage element, and write / read / copy them to first to third storage means. Accordingly, it is possible to improve the fault detection accuracy of a plurality of logic gates including the storage element as compared with the conventional example.

Further, according to the circuit fault pseudo test method of the present invention, the failure mode information propagating from the data input portion to the internal state or the output portion of the storage element of the semiconductor device under test is calculated and stored (the first calculation and storage process). ) Or the failure mode information transmitted from the control signal input section to the internal state or the output section of the storage element MEM is calculated and stored (second calculation storage processing).
Is done.

For this reason, the failure of the logic gate from the data input portion or the control signal input portion of the storage element to the external signal input portion always affects the data input portion of the storage element by the first and second calculation storage processes. In the case where the fault is intermittently affected or the control signal input section is affected, the fault propagation property to the storage element is increased in a manner closer to the actual operating state. It becomes possible to simulate and grasp.

When fault information is detected from the signal output unit to the signal input unit of the semiconductor device under test,
If the storage device is not included in the semiconductor device under test, failure information is detected from the signal output section toward the signal input section (first information search processing), and the storage element is included therein. In this case, the failure information held in the storage element of the semiconductor device under test is detected (second information search processing).

For this reason, since the failure of the logic gate from the data input portion or the control signal input portion of the storage element to the external signal input portion is held in the storage element, the storage element is connected to the data input portion or the control signal input portion. By searching for fault information that propagates to the output unit of the semiconductor device under test, search processing from the data input unit or control signal input unit to the signal input unit of the storage element of the semiconductor device under test as in the conventional example is omitted. Becomes possible.

As a result, it is possible to perform a highly accurate failure simulation of the semiconductor device under test with sufficient consideration of the actual operation state of the storage element using a small computer. As a result, even when there is a request for manufacturing a semiconductor integrated circuit device having several hundred thousand gates including a memory element, the failure detection evaluation can be simplified, which greatly contributes to shortening the design period of the logic gate. .

[Brief description of the drawings]

FIG. 1 is a principle diagram of a circuit failure pseudo test apparatus according to the present invention.

FIG. 2 is a principle diagram of a circuit failure pseudo test method according to the present invention.

FIG. 3 is a configuration diagram of a failure simulation system according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of failure mode information held in a storage element according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of storage contents of a failure information memory according to the embodiment of the present invention.

FIG. 6 is a flowchart (part 1) of a circuit failure pseudo test according to the embodiment of the present invention.

FIG. 7 is a flowchart (part 2) of a circuit failure pseudo test according to the embodiment of the present invention.

FIG. 8 is a supplementary explanatory diagram (part 1) of the fault propagation caused by the data input unit according to the embodiment of the present invention.

FIG. 9 is a supplementary explanatory diagram (part 2) of fault propagation caused by the data input unit according to the embodiment of the present invention.

FIG. 10 is a supplementary explanatory diagram (part 1) of the fault propagation caused by the control signal input unit according to the embodiment of the present invention.

FIG. 11 is a supplementary explanatory diagram (part 2) of the fault propagation caused by the control signal input unit according to the embodiment of the present invention.

FIG. 12 is a supplementary explanatory diagram (part 3) of the fault propagation caused by the control signal input unit according to the embodiment of the present invention.

FIG. 13 is an explanatory diagram of a configuration example of an LSI under test according to an embodiment of the present invention and a search for failure information thereof.

FIG. 14 is an explanatory diagram of a circuit failure pseudo test apparatus according to a conventional example.

FIG. 15 is a processing flowchart (part 1) of a circuit failure pseudo test according to a conventional example.

FIG. 16 is a flowchart (part 2) of a circuit failure pseudo test according to the conventional example.

FIG. 17 is a supplementary explanatory diagram of the circuit failure pseudo test method according to the conventional example.

[Explanation of symbols]

11: storage means, 11A: first storage means, 11B: second storage means, 11C: third storage means, LG1, LG2, LGi, LGn: logic gate, MEM: storage element, DT: test data, D: control data, Sa0, Sa1: failure mode information, fSa0, fSa1, mfSa0, mfSa1, qfSa0, qfSa1: failure information, FLT: failure point, IN: signal input unit, OUT: signal output unit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hidetaka Tsuda 3-2-1 Sakado, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu LSI Technology Co., Ltd. (72) Inventor Sachiko Tada 3-chome Sakado, Takatsu-ku, Kawasaki-shi, Kanagawa No. 2 Fujitsu LSI Technology Co., Ltd. (56) References JP-A-3-286260 (JP, A) JP-A-3-179565 (JP, A) JP-A-5-151300 (JP, A) JP-A-2-204842 (JP, A) JP-A-2-114338 (JP, A) JP-A-1-140245 (JP, A) JP-A-63-75576 (JP, A) JP-A-63-739 (JP-A) JP, A) JP-A-60-43755 (JP, A) JP-A-58-92045 (JP, A) Yasushi and three others, "High-speed failure simulator of sequential circuit including bidirectional elements", Electronic Information Communication Study Technical Report (SDM91- 50), Institute of Electronics, Information and Communication Engineers, 1991, V ol. 91, No. 100, p. 19-26 (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 670 JICST file (JOIS)

Claims (10)

(57) [Claims] 1. A circuit fault simulation test apparatus for performing a fault simulation of a semiconductor device under test, wherein a fault signal propagates from an input section of a storage element in the semiconductor device under test to an internal state set in the storage element. First failure information indicating whether or not a failure signal propagates from an internal state set in the storage element to an output unit of the storage element; and The third failure information and whether at least one of the first failure information, the second failure information, or the third failure information indicates whether or not the failure signal propagates from the input unit to the output unit of the storage element. Storage means for storing failure mode information indicating whether or not there is a failure in the storage element, which is obtained based on one piece of failure information; and observing propagation of the failure based on the failure mode information. Circuit failure pseudo test apparatus characterized by. 2. The circuit according to claim 1, wherein the observation of the propagation of the fault is performed by detecting the fault mode information from an output unit to an input unit of the semiconductor device under test. Failure simulation test equipment. 3. A fourth signal indicating whether a fault signal propagates from an input of an element other than a storage element to an output of the element.
3. The circuit failure pseudo test apparatus according to claim 1, further comprising a storage unit that is different from the storage unit and stores the failure information. 4. The method according to claim 1, wherein the failure mode information is transmitted from an input unit of the storage element to an input unit of the semiconductor device under test.
The second failure information, the third failure information, or the fourth failure information;
4. The circuit failure pseudo test apparatus according to claim 3, wherein the failure information is obtained by detecting at least one of the pieces of failure information. 5. The fault signal is a signal based on a first stuck-at fault where an input signal of an element is fixed to 0 or a second stuck-at fault where an input signal of an element is fixed at 1. Any one of claims 1 to 4
The circuit failure pseudo test device according to the paragraph. 6. A first failure information indicating whether a failure signal propagates from an input portion of a storage element in a semiconductor device under test to an internal state set in the storage element is stored in storage means, A second failure information indicating whether or not a failure signal propagates from an internal state set to the storage element to an output unit of the storage element is stored in the storage unit, and an input unit of the storage element stores the second failure information. A third failure information indicating whether or not a failure signal propagates to an output unit is stored in the storage unit, and the first failure information, the second failure information, or the third failure information is stored in the storage unit.
Detecting whether there is a failure in the storage element based on at least one of the pieces of failure information, storing the failure in the storage unit as failure mode information, and storing the semiconductor device under test based on the failure mode information. A circuit fault simulated test method characterized by observing propagation of a fault from an output unit to an input unit of a device. 7. A fourth signal indicating whether a fault signal propagates from an input of an element other than a storage element to an output of the element.
The failure mode information is stored in a storage unit separate from the storage unit, and the failure mode information is stored in the second failure information from the input unit of the storage element toward the input unit of the semiconductor device under test. 7. The circuit failure pseudo test method according to claim 6, wherein the circuit failure is determined by detecting at least one of the failure information of the third and fourth failure information. 8. A first failure information indicating whether a failure signal propagates from an input portion of a storage element in a semiconductor device under test to an internal state set in the storage element is stored in storage means, A second failure information indicating whether or not a failure signal propagates from an internal state set in the storage element to an output unit of the storage element is stored in the storage unit. Storing in the storage means third failure information indicating whether or not a failure signal is propagated to an output unit of the first failure information, the second failure information, or the third failure information.
Detecting whether there is a failure in the storage element based on at least one of the pieces of failure information, and storing the same in the storage means as failure mode information; Fourth failure information indicating whether or not a failure signal propagates to an output section of the element is stored in a storage unit separate from the storage unit, and the failure information is stored based on the failure mode information or the fourth failure information. A circuit fault pseudo test apparatus for observing propagation of a fault from an output section to an input section of a test semiconductor device. 9. The method according to claim 1, wherein the failure mode information is transmitted from an input section of the storage element to an input section of the semiconductor device under test, from the second failure information, the third failure information, or the fourth failure information. 9. The circuit fault simulation test method according to claim 8, wherein the circuit fault is determined by detecting at least one piece of fault information. 10. The fault signal is a signal based on a first stuck-at fault where an input signal of an element is fixed to 0 or a second stuck-at fault where an input signal of the element is fixed at 1. Any one of claims 6 to 9
The circuit failure simulation test method described in the paragraph.