JP3126833B2 - Fault diagnosis device for integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for diagnosing a failure in an integrated circuit, and more particularly to a device for diagnosing the time required for failure diagnosis.

[0002]

2. Description of the Related Art With the increase in the scale of integrated circuits, the diagnosis of their failures has become more and more difficult, and the work for the diagnosis has taken a great deal of time. Analyzing the failure operation of an integrated circuit is not easy even for designers who are familiar with the operation inside the circuit. With the increase in scale, failure diagnosis methods relying on the knowledge of designers are reaching the limit.
Therefore, there is a need for a means for performing diagnosis in a short period of time without knowledge of the internal operation of the integrated circuit. One method for realizing this is a failure diagnosis device using a guided probe based on an EB (electron beam) prober.

FIG. 4 is a diagram for explaining a failure diagnosis method using the failure diagnosis device. The procedure of diagnosis will be described below with reference to FIG. When a failure is detected at the external terminal 41 by an LSI tester or the like, the propagation path of the failure signal is traced toward the input side using this terminal as a starting point (referred to as a back trace), and the preceding gate A is detected. Next, the input side net p1 of the gate A is probed by the EB prober, and the waveform is observed. The waveform obtained by probing is immediately compared with an expected value waveform prepared in advance by logic simulation. FIG. 4B shows a comparative example of the waveform. Since the measured waveform of p1 and the expected value waveform do not match, this net is regarded as a fault, and the input side nets p2 and p3 of the preceding gate B of p1 are sequentially blown. FIG.
In (c) and (d), the measured waveform and the expected value waveform match at p2, and do not match at p3. So, let p3 be a failure,
The input side net of the preceding gate C is probed.
This process is repeated, and when the input pins finally reach the logic gate D in which all the pins become normal, this is regarded as a fault gate and the fault tracking ends.

As a fault diagnosis apparatus for an integrated circuit for realizing such a fault diagnosis method, there is a conventional one having a configuration as shown in FIG. Guided probe failure diagnosis means 2
1 determines an internal circuit net to be probed based on the circuit connection design information 22 and the name of the external terminal at which a failure is detected, in the same manner as described with reference to FIG. E
The B prober 23 directly probes the wiring pattern on the integrated circuit corresponding to the internal circuit net, and measures the waveform. On the other hand, the logic simulator 25 determines in advance the expected value waveforms of all the circuit nets in the integrated circuit based on the circuit connection design information 22 and outputs them to the expected value waveform file 26. The waveform comparing means 24 reads out the expected value waveform from the expected value waveform file 26, compares it with the measured waveform, and sends the result to the guided probe fault diagnosis means 21. The means determines whether or not a failed gate has been identified based on the comparison result of the waveforms and the circuit connection design information 22, and if not, determines the next internal circuit net whose waveform is to be measured. Thereafter, this process is repeated until a failure point is specified. As described above, since the present fault diagnosis apparatus has the support means for tracing the fault path inside the integrated circuit based on the circuit connection design information 22 and the expected value waveform obtained by the logic simulation, the operation relating to the design is performed. There is a feature that even a test engineer without knowledge can easily diagnose a failure.

References describing this kind of technology include, for example, Yamaguchi, et al., “Study of Guided Probe Method Using Logic Electron Beam Tester”, Japan Society for the Promotion of Science, 132nd Committee, 117th Meeting Research meeting materials, 53-5
8, December 1991.

[0006]

On the other hand, in order to perform a fault diagnosis of an integrated circuit by the present apparatus, it is necessary to prepare in advance an expected value waveform of an internal circuit net along a fault tracing path by a logic simulation. Absolute condition. In the logic simulator, a net from which such an expected value waveform is to be output is called a “log point”. In a conventional device, it is customary to set a net of the entire circuit to be output as a log point in one logic simulation.
The reasons are considered as follows.

[0007] 1) Nets for which waveform comparisons are actually performed in guided probe diagnosis are eventually limited to nets on the fault tracking path. Before the fault tracking, which net is on the fault path. It is unknown in advance, and there is a possibility that all nets are on the same route.

2) In a normal logic simulator, the logic simulation processing time does not depend on the number of log points, and even if all the nets are log points, the processing time does not change much.

Therefore, a large number of expected waveforms of log points not used in the process of failure tracking are prepared, and there is much waste in logic simulation data. Further, assuming that the processing time T is constant for a test pattern length,

[0010]

(Equation 1)

Therefore, when the scale of the integrated circuit increases,
The processing time and data volume by the computer become enormous,
It has been very difficult to apply this type of conventional fault diagnosis apparatus to fault diagnosis of large-scale integrated circuits.

On the other hand, Verilog (Cadence, USA)
In recent logic simulators such as KK, event processing can be optimized by capturing log points before compiling, and the entire logic simulation can be performed within a practical time even with a 100k gate class integrated circuit. It has become possible. The processing time T of such a logic simulator is almost determined by the number of log points with a fixed test pattern length.

[0013]

(Equation 2)

Is given by As the circuit scale increases and the data overflows from the real memory of the computer executing the simulation, the value of m approaches 2, and the processing time dramatically increases. Therefore, reducing the number of log points is an essential condition for executing a logic simulation in a short time.

However, as described above, in the conventional failure diagnosis apparatus, there is no means for supporting the execution of the simulation by limiting the number of log points to a certain number or less, and all circuit nets are used as log points. For this reason, the simulation time is rapidly increased with an increase in circuit scale, and even if such a latest logic simulator is used, there is no change in that it is difficult to perform a simulation within a practical time range. Therefore, there has been a problem that the guided probe diagnosis is interrupted due to waiting for the result of the logic simulation.

Although the logic simulation time can be reduced by shortening the test pattern length, the test pattern length tends to increase with the scale of the integrated circuit. Is generally difficult even for designers. As a result, the amount of simulation data increases with the scale of the integrated circuit, further reducing the overall efficiency.

An object of the present invention is to solve the above-mentioned problems in the prior art and to reduce the logic simulation time and the amount of simulation data in the course of fault diagnosis by the guided probe method. It is an object of the present invention to provide an integrated circuit fault diagnosis apparatus capable of greatly reducing the time required for fault diagnosis as a whole as compared with the conventional guided probe method.

[0018]

In order to achieve the above object, an apparatus for diagnosing a failure in an integrated circuit according to the present invention is provided.
Probing the internal circuit of the chair directly and measuring the internal waveform
Prober means and the most recently detected fault
Logic operation directly or indirectly on the fault logical value of the net
The number of circuit nets that can affect
Circuit connection design information that includes the following circuit parts
Circuit net extracting means for extracting the circuit net from
The circuit net included in the circuit part extracted by the means is
Logic based on the above circuit connection design information
Logic simulation to obtain expected value waveform by simulation
The expected value waveform and the prober means.
Waveform comparison means for comparing the measured waveform with
The faulty gate can be identified based on the
Judge whether or not the next probe is possible.
Determine the internal circuit net to be output to the prober
Repeat the steps until the failure point is identified.
Characterized by having an idle probe failure diagnosis means.
I do.

[0019]

In the prior art, the logic simulation is performed using all the internal circuit nets as log points. On the other hand, in the device of the present invention, the log points are narrowed down to the circuit portion extracted by the above method, and the logic simulation is divided into a plurality of times. They differ in that they do.

[0020]

FIG. 1 is a view for explaining an embodiment of the present invention.
A circuit net extracting means is newly added to the conventional fault diagnosis device. The operation of the device of the present invention will be described below with reference to FIG. First, the guided probe diagnostic means 21
Determines the next net to be probed based on the circuit connection design information 22 and the information on the faulty external terminal or faulty net detected in advance. The EB prober 23 directly probes the wiring pattern on the integrated circuit corresponding to the determined net and measures the waveform. The waveform comparing means 24 reads out the expected value waveform from the expected value waveform file 26, compares the waveform with the measured waveform, and returns the result to the guided probe fault diagnosis means. If there is no waveform corresponding to the net to be referred to in the expected value waveform file, the circuit net extracting means 27 applies the influence on the logical operation to the fault logical value of the most recently detected faulty circuit net. A circuit portion including a given number of nets or less is cut out, and the circuit net included in the circuit portion is output to the log point file 28 as a log point. At this time, the scale of the circuit block to be cut out is set so that the number of internal nets falls within the range of the number of log points determined by the equation (2) with respect to a preset simulation time. Next, the logic simulator 25 performs a logic simulation based on the log point information of the file, and additionally registers the result in the expected value waveform file 26. Next, the guided probe diagnostic means 21 determines whether or not a failed gate has been specified based on the comparison result and the circuit connection design information 22, and if not, determines the next probing point. Thereafter, this process is repeated until a failure point is specified.

FIG. 2 shows a first embodiment for extracting a circuit portion including a predetermined number or less of nets which can influence the logical value of a faulty circuit net on the logical operation by the circuit net extracting means. . When the fault external terminal A is set as a starting point for fault tracking, 1 is assigned to this terminal, and then 2 is applied to all input terminal nets of all logic cells outputting a signal to this terminal.
Is given. Next, 3 is assigned to all nets of all input terminals of all logic cells that output signals to the net to which 2 is assigned. Such a numbering procedure is called numbering by horizontal search. This search procedure is repeated, and the search is stopped when the number of numbered nets reaches a predetermined number.
Outputs the net name of the numbered circuit part as a log point to a file. If the fault tracking path passes through the circuit part and reaches the internal circuit net B, and if this net is determined to be faulty, a log point is obtained in order to obtain an expected value waveform required on the fault tracking path beyond this. Needs to be newly set and the logic simulation needs to be performed again. At this time, the numbering is performed by the horizontal search starting from the net B, and the search is stopped when the number of the numbered nets reaches a predetermined number. Outputs the net name of the numbered circuit part as a log point to a file. Thereafter, the same process is repeated until a faulty gate is specified.

FIG. 3 shows a second embodiment for extracting a circuit portion including a predetermined number or less of nets which can influence the logical value of a faulty circuit net on the logical operation by the circuit net extracting means. . First, assuming that the fault external terminal A is a starting point of fault tracking, a block X in which the number of nets included therein is within a predetermined range among functional blocks of each design hierarchy including a logic cell that outputs a signal to this terminal. A file is cut out as a circuit part, and a file is generated using all the internal nets as log points. In the course of the failure diagnosis, the failure tracking path passes through the block X and reaches the net B on the input side. If it is determined that the net B has failed, it is necessary to set a new log point and perform a logic simulation. In this case, a signal is output to the net B, the block Y in which the number of nets is within a predetermined range is cut out as a circuit portion, and a file is generated using all the internal nets as log points. Thereafter, this process is repeated until a failure point is specified.

As described above, in the device of the present invention, a circuit portion including a predetermined number or less of the number of nets that can affect the logical operation of a faulty logical value of an arbitrary faulty circuit net is extracted. There is a simulation log point generating means for outputting the internal circuit net as a log point to a file. Therefore, it is possible to perform a logic simulation in which the number of log points of the logic simulation in the course of the failure tracking by the guided probe method is minimized, and the logic simulation time per operation is greatly reduced. Assuming that the total number of logic simulations when one fault is traced is 3 and the number of log points is S1, S2, S3, the total logic simulation processing time T1 is

[0024]

(Equation 3)

On the other hand, when all the internal nets of the integrated circuit are log pins, the processing time T2 is

[0026]

(Equation 4)

## EQU1 ## In a large-scale integrated circuit, since m is close to 2,

[0028]

(Equation 5)

## EQU1 ## In other words, by dividing log points, the logic simulation can be performed multiple times,
The computer processing time of the logic simulation as a whole will be greatly reduced. Further, since the data amount of the logic simulation is proportional to the number of log points, it is reduced by E.

[0030]

As described above, in the device of the present invention, it is expected that the logic simulation time and the amount of simulation data can be significantly reduced in the course of failure diagnosis by the guided probe method. In particular, there is an effect that the failure diagnosis period of a large-scale integrated circuit is greatly reduced as a whole as compared with the conventional guided probe method.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a device of the present invention.

FIG. 2 is a diagram illustrating a method for calculating a simulation log point by a horizontal search performed by the apparatus of the present invention.

FIG. 3 is a view for explaining a method of calculating a simulation log point for each functional block according to the apparatus of the present invention.

4A and 4B are diagrams for explaining a fault diagnosis method for an integrated circuit by a conventional guided probe method, wherein FIG. 4A is a diagram illustrating a diagnosis procedure, and FIGS. 4B, 4C, and 4D each show a waveform comparison example. FIG.

FIG. 5 is a diagram showing a configuration of a conventional integrated circuit failure diagnosis device.

[Explanation of symbols]

 Reference Signs List 21 Guided probe diagnostic means 22 Circuit connection design information 23 EB prober 24 Waveform comparison means 25 Logic simulator 26 Expected value waveform file 27 Circuit net extraction means 28 Log point file

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28 G06F 15/60

Claims (1)

(57) [Claims] A prober means for directly probing an internal circuit of an integrated circuit device to measure an internal waveform, and detecting a fault logical value of an internal net in which a fault has been detected most recently.
Circuits that can directly or indirectly affect logical operation
The number of times that the net contains a specified number or less
A circuit net that extracts road sections from circuit connection design information
Extraction means , included in the circuit portion extracted by the circuit net extraction means
The above circuit connection design using the circuit net as a log point
Expected value waveform by logic simulation based on information
Logic simulator means for calculating the expected value waveform and the waveform measured by the prober means.
A waveform comparing means to be compared, and a fault gate based on the comparison result and the circuit connection design information.
It is determined whether or not the port has been identified.
Determine the internal circuit net to be robbed and
Steps to be output to the backup
And a guided probe failure diagnosis means .