JP3161345B2 - Fault block identification method having Iddq abnormality - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS (complementary M
OS) Regarding a technology for detecting a fault location in a semiconductor integrated circuit (LSI), in particular, extracting a faulty block by comparing a logic state of an internal circuit in a test vector for the presence or absence of a quiescent power supply current and displaying the fault location The present invention relates to a method for specifying a failure point by using a method.

[0002]

2. Description of the Related Art A conventional method of narrowing down a faulty part of an LSI based on a simulation using CAD (computer-aided design) estimates a faulty part based on information on occurrence of an abnormality at an output terminal of the LSI. Was something.

The first method is a fault dictionary (Fault Dict).
In this method, a fault is defined in each block of the internal circuit of the LSI, and an output terminal at which an abnormality is detected, an output value, and the like are defined.
Then, by comparing the test pattern number with the data of the actual faulty product, the fault location is estimated.

[0004] More specifically, as shown in FIG.
By comparing the logic defined by the logic simulation between the normal circuit and the circuit in which the failure is defined in the blocks constituting I, the abnormality output terminal, the output value, and the test pattern number of the actual failed product are compared. Thus, the fault definition position is extracted. That is, referring to FIG. 22, the logical connection information 1503 of the LSI into which the failure definition 1502 is introduced.
, A logic simulation 1501 is performed by inputting a test vector 1504, a logic simulation 1501 ′ is performed by inputting the same test vector 1504 to the logical connection information 1505 of a normal LSI, and the results of both logic simulations are obtained. The comparison is performed by the comparing means 1506.
The fault defined in 1502 is detected.

[0005] The second method is called a "back trace method", and traces the logic in the reverse direction from the output terminal to the input terminal based on the output terminal where the abnormality is detected, the output value, and the test pattern number. How to That is,
When a predetermined signal is input from the input terminal of the LSI and the signal output from the output terminal is different from the expected value, the difference between the output value and the expected value is used to shift from the output terminal side to the input terminal side. A signal that propagates a fault is extracted from the signals that are diffused toward the inside, a fault location is estimated, a fault is defined at that location, and a logic simulation is performed again to determine the actual fault. Is a method of verifying the match.

In order to identify a faulty portion of an LSI, it is general to investigate a plurality of output faulty portions of the LSI and narrow down the faulty portion by limiting a pseudo fault signal by a combination of these. Met.

[0007]

However, in any of the above-mentioned conventional methods, the fault location cannot be narrowed down unless the logical configuration of the electric circuit in the LSI to be detected is understood. There was a problem.

First, a fault model that can be handled by the fault simulation method by creating a fault dictionary, which is the first method, is as follows:
Since only stuck-at faults (Stuck-at-0, Stuck-at-1) cannot be simulated, and multiple stuck-at faults or open faults cannot be simulated, it is not general from the point of specifying a fault mode (ie, detection The possible fault range is only a single stuck-at fault, and the versatility is poor.

This is because the only faults handled in the fault simulation are modeled logical faults.

Further, in the first method, LS
Faults must be defined for all signal lines constituting the circuit of I, resulting in a huge amount of data, which is not practical.

That is, the number of faults (V0) to be defined is LS
It is said that it is proportional to the third to fourth power of the number (L) of circuit elements constituting I.

[0012]

(Equation 1)

Further, the back tracing method, which is the second method, uses only the information on the output terminal abnormality as data, and therefore cannot determine how many failures have occurred in the circuit. Failure cannot be handled.

Even if the multiple values are found, it is impossible to determine which output information corresponds to each fault location from only the information at the output terminal, so that only a large number of simulated faults due to the back trace are detected. In other words, narrowing down is completely impossible.

Further, in the back trace method, the existence of a sequential circuit inside the circuit is a serious problem.

The logic circuit is roughly composed of two circuits. That is, a sequential circuit and a combinational circuit.

The combinational circuit sandwiched between the sequential circuits is denoted by 1
Although it is possible to extract a signal that seems to be propagating a fault while back tracing from the output to the input side in the independent system by considering it as two independent circuits, it is possible to extract to some extent by simulation, but the sequential circuit Since the loop must be considered, it is difficult to extract the signal that propagates the fault.

That is, in the sequential circuit, since the output logic at a certain time is a circuit that depends on input information applied at an earlier time, the signal input to the sequential circuit is configured as a feedback loop. When that happens, it becomes a problem.

More specifically, referring to FIG. 23, for example, when the timing of the signal output to the output terminal of the sequential circuit SC1 is (n), the input signal of the sequential circuit SC1 is The signal at (n-1) is input, and the input signal is dependent on the output of the sequential circuit SC1 forming the feedback loop. Further, the input signal of the sequential circuit SC1 has a complicated relationship that also depends on the input signal at the timing (n-2).

Therefore, even if a failure is detected in the combinational circuit 1 at the timing (n), the state depends on the pattern at the (n-1) corresponding to the input timing of the sequential circuit. Again depends on the sequential circuit itself via the preceding combinational circuit.

That is, in the back trace verification focusing on the logic, when there are a plurality of feedback combinations as described above, the combinational circuits existing between the sequential circuits repeat the propagation of the fault many times. Propagation tracking becomes difficult, and practical use is considered impossible at present.

For this reason, the back tracing method has given up giving up the narrowing down of the faulty part or the faulty block only by the method, and has been linked with a physical analysis method such as an EBT (Electron Beam Tester). In fact, it is necessary to adopt a method of erasing a pseudo failure location from failure candidates by acquiring a potential contrast image or a logic operation waveform by non-contact.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a CMOS LSI with a failure location which can specify a failure location regardless of the presence or absence of an output terminal abnormality. It is to provide a specification method.

Further, the present invention makes it possible to narrow down a fault location having various fault modes and irrespective of the magnitude of a leak current value, and furthermore, it is possible to instantaneously identify the finally narrowed fault built-in block position. It is another object of the present invention to provide a failure location specifying method capable of quickly analyzing the cause of a failure.

[0025]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention generally provides an extracting means for extracting a faulty block having an Iddq abnormality generated in an LSI, and the extracted faulty block. Means for displaying the position of In the present invention, an input terminal of an LSI
The LS, which changes according to a test vector input from the
Logical operation of basic logic circuit unit (block) constituting I
Operation information and the test vector to the input terminal of the LSI.
Test vector number at which Iddq abnormality was detected when applied
It is possible to perform arithmetic processing for each block using
With the above, the fault block candidates are narrowed down,
The position of the fault block on the LSI is standardized by
Displays the position of the lock.

[0026]

Embodiments of the present invention will be described below. First, the principle of the present invention will be described. CMOS
When a logic circuit has a physical defect inside the circuit, a general tendency is “Iddq (Quiesent Vdd Supply Curr).
An abnormal value appears in the quiescent power supply current referred to as “ent)”. The Iddq abnormality can be regarded as a signal (signal) that manifests a physical failure inside the LSI circuit to the outside. Details of the Iddq are, for example, A paper by the present inventor (M. Sanada, “Evaluation and Detection of C
MOS-LSI with Abnormal Iddq "Microelectro
nics and Reliability, Vol. 35, No. 3, pp. 619-629,
1995). The present invention has been completed by utilizing the above-described properties of the CMOS logic circuit.

Usually, ASI represented by a gate array product
C (Application Specified Integrated Circuits)
Is realized by configuring a desired electric circuit (electronic circuit) by combining circuits constituting basic logic called "blocks" prepared in advance.

In a preferred embodiment of the present invention, the above-described design method is used for a method of narrowing down a failure portion in a CMOS LSI.
The logic operation information, which changes in accordance with a test vector input from the input terminal of the SI, in units of basic logic circuits constituting the LSI called "block", and the static operation of the LSI called "Idddq" for each test vector By using a test vector number in which the value of the leakage current in the state exceeds a predetermined value, a faulty block containing an Iddq error is extracted by performing an arithmetic process described later on each block for each block, and the faulty block is extracted. , Are displayed at corresponding locations in the entire LSI image.

The logic operation state of each block is obtained by extracting the logic of each block, which changes in synchronization with the test vector input from the input terminal of the LSI, by simulation. Consists of a combination of logic.

The logic operation processing for extracting a failed block for each block differs depending on the type of circuit, that is, the combinational circuit and the sequential circuit.

First, as for the arithmetic processing in the combinational circuit, for each block, a test vector number in which an Iddq error occurs and a test vector in a test vector number in which an Iddq error does not occur are compared with each other. By extracting a block in which no block is found as a failed block, a failed block is extracted.

The arithmetic processing in the sequential circuit includes, for each block, a test vector group in a test vector number in which Iddq errors detected continuously occur in each test vector and an arbitrary continuous test vector number in which no Iddq errors occur. In the comparison between the test vectors in the above, a block in which the test vector group does not match is extracted as a faulty block.

Further, in the preferred embodiment of the present invention, the extraction of the faulty block separates the combinational circuit and the sequential circuit, and for a large-scale circuit, keeps the separation of the combinational circuit and the sequential circuit. Meanwhile, by dividing the data into layers, the defective block candidates are narrowed down to a large-scale to a medium-scale and to a basic logic circuit unit.

Next, according to a preferred embodiment of the present invention, as a display method for displaying a failed block at a corresponding arrangement position in an entire image of an LSI, a circuit element group in a block constituting an LSI, and The smallest rectangle surrounding all the wirings connecting these circuit element groups is set as the size of the block, and the origin coordinates of each predetermined block are made to match the physical coordinates of each block arranged on the LSI. As a result, the failed block extracted by the above-described arithmetic processing is displayed at a corresponding location on the LSI.

[0035]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

As described above, when a CMOS logic circuit has a physical defect inside the circuit, the general tendency is "Idd".
An abnormal value appears in the power supply current when the logic called "q (Quiesent Vdd Supply Current)" is at rest.

FIG. 1 is a diagram schematically showing a situation in which a through current occurs due to the presence of a physical failure in an LSI. That is, if a physical failure exists inside the LSI,
Through-current from the higher power supply Vdd to the lower power supply GND is generated by the logic set by an arbitrary test vector via the physical failure or under the influence of the physical failure.

The logic via the physical fault propagates to the output terminal with the progress of the test vector, and there are two modes, a mode in which an output error occurs and a mode in which no output error occurs.

This difference depends on whether the output logic of the circuit at the location of the Iddq abnormality occurring due to the physical failure is higher or lower than the threshold value (Vth), as shown in FIG. is there. That is, as shown in FIG. 2B, the voltage value (low-level output voltage VOL) of the output (OUT) of the Iddq abnormal circuit (see FIG. 2C) is different from the expected value of the output “L”. Threshold value (Vt
h), it propagates to the output as normal logic and
If the low-level output voltage value (VOL) of the ddq abnormality circuit is higher than the threshold value (Vth), it propagates as a logic abnormality to the output terminal and is detected as an output abnormality.

As shown in FIG. 2A, the output "H"
Iddq abnormal circuit for expected value (see FIG. 2 (c))
If the output value (high-level output voltage VOH) is lower than the threshold value (Vth), it propagates to the output terminal as a logic abnormality, is detected as an output abnormality, and the high-level output voltage value (VOH) of the Iddq abnormal circuit. ) Is higher than the threshold value (Vth), the signal is normally propagated to the output as normal logic.

In the present embodiment, a method for narrowing down the effective fault locations is realized for both of these modes, and the fault occurrence locations are specified using this Iddq abnormal phenomenon.

Normally, ASI represented by a gate array product
C (Application Specified Integrated Circuits)
Is a design method for realizing a desired electric circuit by combining circuits constituting basic logic called "blocks" prepared in advance.

The narrowing down of the fault location existing in the CMOS circuit of the ASIC is performed by using the logic simulation information of each block that changes for each test vector and the Idd.
It becomes possible by using a test vector number that causes q abnormality. This will be described in detail below.

FIG. 3 is a diagram showing an Idd according to an embodiment of the present invention.
It is the figure which showed typically the display method of the faulty block which has q abnormality. Personal computer ("PC") or engineering workstation ("EW
S) is displayed on a screen 34 of a display device such as a CRT of a computer system 35 of the computer system 35. By inputting logical information and test vector information described below, test vector information The pseudo-failed blocks are standardized and displayed according to the logical information that changes synchronously in accordance with the change of the blocks.The candidates for the pseudo-failed blocks are narrowed down as the test vector progresses. You can monitor your progress.

The standardized display of each block constituting the internal circuit will be described with reference to FIG.

First, as for the size of each block constituting the LSI, the semiconductor element group constituting the block and the outermost region of the wiring, which constitutes an electric circuit by connecting these element groups, are enclosed as a rectangle. Size. Since the origin of each standardized block is determined at an arbitrary position in the design policy, and in the LSI design, the arrangement information of each block is determined. It can be easily allocated on an LSI. FIG. 4B shows a minimum rectangle (corresponding to a standardized block) surrounding all the circuit element groups in the block and the wiring connecting these circuit element groups in FIG. 4A.

FIG. 5 is a diagram schematically showing a processing flow for narrowing down a defective block in one embodiment of the present invention.

Referring to FIG. 5, a test vector 501 prepared for testing the logical operation of LSI 510
Is logical information for each block constituting the LSI 510 and Iddq for each test vector, which change for each test vector.
It is used to detect the presence / absence information of the abnormality.

First, logic information of each block that changes for each test vector is extracted by a logic simulation 502 for verifying an LSI circuit. The logic simulation 502 is a tool for logic verification that verifies an expected value output to an output terminal corresponding to a test vector 501 input from an input terminal of an LSI.

In the verification process by the logic simulation, the logic of each block operating simultaneously with the input test vector is also verified.

Therefore, by specifying the text name (simulation result information by logic simulation) of each block constituting the LSI called "dump processing", the logic information of each block for each test vector can be output ( (See 503 in FIG. 5).

At this time, the LSI tester 506
A test pattern is applied to the SI 510 to measure Iddq, detect an Iddq abnormal test pattern, extract a dump list of a logic simulation result based on this information, and perform an arithmetic process on the extracted result ( A defective block is extracted (see 504 in FIG. 5) (50 in FIG. 5).
5) As a result of narrowing down the defective blocks, the position of the defective block on the LSI is displayed on the screen of the display device (FIG. 5).
509). In FIG. 5, the outer periphery of each layer 508 schematically shows an LSI.
A rectangle of × 6 represents a standardized block, and the plurality of layers schematically represent an LSI for each test vector.

Conventionally, the circuit verification to be executed generally simulates the time change of the logic output from each block together with the logic of the internal circuit of the LSI.
For this reason, the input logic of each block constituting the internal circuit of the LSI has received little attention.

In the embodiment of the present invention, a faulty block is specified by simulating how the input logic of each block constituting the internal circuit of the LSI changes for each test vector, and It is extracted as input logic information and used for arithmetic processing described later. Here, the reason for using the input logic information of each block is shown in FIG.
Description will be made using an input NAND circuit.

Referring to FIG. 6A, the two-input NAND circuit includes two P-type MOS transistors PM1 and PM2 connected in parallel between power supply terminal VDD and output terminal OUT and having inputs IN1 and IN2 as gate inputs. And the output terminal OUT
N-type MOSs connected in series between the power supply and a ground terminal GND
And transistors NM1 and NM2.
As is clear from the truth table of FIG. 6B, FIG.
There are four combinations of inputs of the two-input NAND circuit of which the three combinations of inputs (IN1, I2
N2) = (H, L), (L, H) and (L, L) have the same output at "H".

As far as the expected value of the output is concerned, the change is not known. However, when looking at the input, the internal logic is clearly changed with respect to the change of the input value, and the input logic information of each block is important. It can be seen that it is.

FIG. 7 shows Idd for each test vector described above.
5 is a graph showing q abnormality presence / absence information, in which an X axis indicates a test vector number (hereinafter, referred to as “TVno.”) and a Y axis indicates an Iddq value. The Iddq value of a normal LSI is equal to or less than a standard value (for example, 1 μA or less when a through current does not occur in a circuit in a normal state), whereas an Iddq abnormal product has hundreds to thousands times the standard value. An abnormal through current flows. FIG.
Then, Iddq anomaly test vector numbers are a, b, c
Indicated by. In FIG. 7, TV no.
In (a), (b), and (c), an Iddq abnormality having the same value has occurred.

Next, a method for narrowing down a defective block according to an embodiment of the present invention will be described.

FIG. 8 is a diagram schematically showing a principle for narrowing down a failed block according to one embodiment of the present invention.
Referring to FIG. 8, a plurality of blocks B1, B2, B3,
, Bn,..., A test vector 802 is input from an input terminal of an LSI 801. The input logic reaches the output terminal while developing the logic in these blocks.

The above-described dump processing (see 503 in FIG. 5)
Thus, the logic state of each block for each test vector is extracted. This situation is shown in FIG. 8 as dump lists 810 _{1 to} 810 _n for each block. In the dump list 810 _{1 to} 810 _{n for} each block, the TV
1, TV2,... Indicate a test vector number and a vector of the number.

The Iddq value detected for each test vector in the LSI is the Iddq value generated in each block (B1, B2, B3,..., Bn,...) For each test vector.
This is the sum of the q values and usually falls within the standard value.

However, if there is a block having a built-in physical failure, an abnormal current value generated in the block is detected as an Iddq value abnormality in the LSI.

The test vector numbers TVno. (A), (b) and (c) where the above-mentioned Iddq value abnormality has occurred are indicated by T in the dump list 810 _{1 to} 810 _n for each block.
Vno. (A), (b) and (c) are also supported.

Therefore, in each block, the input logic of the test vector in which the Iddq is abnormally displayed and the test vector in the normal state are compared (this will be described later).
This makes it possible to extract a block containing the Iddq abnormality.

Next, in one embodiment of the present invention, Idd
A method of extracting a block containing a q abnormality will be described.

The blocks making up the ASIC are roughly classified into two types of circuits. A combinational circuit and a sequential circuit.
Among these, the combinational circuit is a circuit type in which when a signal is applied to the input terminal of the block, the logic is directly output via an internal circuit, and the combinational circuit has a basic gate (AND, O
R, NAND, and inverter circuits) to large-scale circuits such as ALU (arithmetic logic operation unit) and ADDER (addition) circuit.

The sequential circuit is of a circuit type in which data is temporarily stored in the circuit in synchronism with a clock signal, and is output by the next clock signal, and includes a flip-flop, a register circuit, a latch circuit, and the like. is there. In one embodiment of the present invention, the fault diagnosis of these two types of circuits is performed in different ways, as described below.

First, a method of extracting a failed block from a combinational circuit will be described with reference to FIGS. FIGS. 9 and 10 are diagrams showing an example of contents extracted as a dump list in a combinational circuit having nine input terminals. For simplicity, it is assumed that an Iddq abnormality has occurred only in one test vector having a test vector number a.

The test vector number a (this is referred to as “TVno.
(A)) is input logic information (01111).
0001), and the following operation is performed to check whether a physical failure is built in this block.

As shown in FIG. 9, in test vectors other than TV no.
When there is the same input logic (011110001) as in o. (a), it is determined that this block does not incorporate a physical failure. This is because the combinational circuit always allows only one internal logic for any input logic. Therefore, when the same input logic as TV no. (A) exists in the normal test vector, the block is determined to be normal.

Further, this judgment is made based on whether a block has a built-in physical fault or not, and a normal test vector having the same input logic as TV no. (A) has a normal logical state. Is derived from the fact that the fact that

From the above, although the test vector at TV no. (A) has an Iddq abnormality,
If the test vector indicating the ddq value includes the same vector as TV no. (a), it is determined that the block does not include a physical failure.

Next, as shown in FIG.
In test vectors other than (a) having a normal Iddq value, the same input logic (01111000) as TV no. (A) is used.
When 1) does not exist, this block is extracted as containing a physical fault. This is because, similarly to the above, the combinational circuit always allows only one internal logic for an arbitrary input logic, and only the test vector has an Iddq abnormality, and This is because there is no fact to deny.

Similarly, even when a plurality of test vectors having the same input logic state are generated in different test vectors, the determination as to whether or not a physical fault is contained is the same as the case illustrated in FIGS.

FIGS. 11 and 12 show a combination circuit having nine input terminals in which an Iddq abnormality has occurred in three test vectors TV no. (A), (b) and (c). Their input logic is, in order:
(011110001), (001110001),
It is assumed that the states are different from each other as (000110001).

Investigation as to whether or not this block has a built-in physical failure is basically the same as in the case of occurrence of an Iddq error in a single test vector described with reference to FIGS. 9 and 10. is there.

That is, TV no. (A), TV no.
(B), TVno. (C) is determined as an independent test vector by checking whether the same input logic as those test vectors exists in a normal test vector.

First, as shown in FIG. 11, each test vector TVno. (A), (b),
For each of (c), a test vector having a normal Iddq value has each test vector TVno. (A), (b),
The same input logic as (c) (011110001), (00
When at least one of (1110001) and (000110001) exists, it is determined that this block does not include a physical failure. What happens
As described above, the combinational circuit always allows only one internal logic for any input logic. Therefore, when the same input logic as the Iddq abnormal test vector is present in the normal test vector, the block is determined to be normal. Because it is done.

That is, in a certain block, a test vector having three different input logics causes an Iddq abnormality for one fault (see the same Iddq abnormal value in FIG. 7).
Is generated.

This is apparent from the relationship between the test vector and the fault location, as schematically shown in FIG.
Test vectors TVno. (A), (b), corresponding to input logics that cause three different Iddq abnormalities in SI
(C) means that the same logic that causes an Iddq abnormality is set for one fault location in the internal circuit configuring the block. In FIG. 13,
FIG. 3 schematically shows a test vector and a signal propagation path in a block when an Iddq abnormality occurs in a single fault location (indicated by a black star) by a plurality of different test vectors.

Therefore, the fact that at least one of the three input logics described above is the same as the normal input logic of the test vector means that the logic set for the fault location indicates that the Iddq error has occurred. Means that it has not occurred, and furthermore, I
Since it is interpreted that no ddq abnormality has occurred, a contradiction occurs to the above assumption.

For this reason, when there is at least one input logic which is the same as the input logic, it is determined that this block does not contain a physical failure.

Next, as shown in FIG. 12, in a test vector having a normal Iddq value, each test vector TVno.
When there is no input logic identical to any of the input logics (a), (b), and (c), this block is determined to have a built-in physical failure.

Further, this data is very important data in narrowing down a failure level at the transistor level in the block, which will be described later.

Next, a method of extracting a defective block from a sequential circuit will be described with reference to FIGS.

FIGS. 14 and 15 show dump lists extracted in a sequential circuit having five input terminals.

In FIG. 14, TV no. (41),
In the continuous test vector (42), Iddq
An error has occurred. When the same input logic group as the input logic group exists in the normal test vector, it is determined that this block does not include a physical failure.

Further, as shown in FIG. 15, when the same input logic group TVno. (41), (42) does not exist in a normal test vector, a physical fault is built in this block. Is determined.

FIGS. 16 and 17 show dump lists extracted in a sequential circuit having five input terminals.

As shown in FIG. 16, ΔTVno. (4
(1), (42)} and {TV no. (51), (5)
2), (53), (54)}, Iddq abnormality has occurred in two consecutive test vectors. For one or more of these input logic groups, when the same input logic group exists in a test vector indicating a normal Iddq value (the test vectors 102 to 105 having the same input logic as the test vectors 51 to 54 having Iddq abnormality). Is Iddq normal),
This block is determined not to have a built-in physical failure.

Further, as shown in FIG. 17, when the same input logic group as these input logic groups does not exist in a normal test vector, it is determined that this block has a built-in physical fault.

The reason for this determination is that the D-type flip-flop (“D-type F / F”) which is a basic sequential circuit shown in FIG.
F "for short).

FIG. 18 shows a configuration of a D-type flip-flop having a two-input and two-output terminal group composed of one inverter circuit, two two-input AND circuits, and two two-input NOR circuits. Is shown. D is the data terminal, C
LK indicates a clock terminal, Q and Q ^* indicate output terminals, and complementary output terminals. FIG. 19 shows a truth table of the D-type flip-flop shown in FIG.

In this D-type F / F, when the Q output-side two-input NOR circuit NOR1 outputs "H", Iddq
Assuming that an abnormality has occurred, the abnormality is determined by the test vectors TVno. (6), (7),
Id in (10), (11), (12) and (13)
A dq abnormality occurs.

Of these, TV nos. (7), (11),
When focusing on (13), the same input logic is used when TV no.
This is also set in (3), (5), and (9). However, in the input logic of these TV Nos. (3), (5) and (9), no Iddq abnormality has occurred.

The reason for this is that the sequential circuit has a circuit format in which data is temporarily stored in the circuit in synchronization with a clock signal and output with the next clock signal.

That is, as is clear from the logic table shown in FIG. 19, test vectors TVno. (7), (1)
In the logics held in 1) and (13), the two-input NOR circuit NOR1 on the non-inverting output Q side outputs "H" and the two-input NOR circuit NOR2 on the inverted output Q ^* side outputs "L". Test vector (3),
The logic held in (5) and (9) is that the 2-input NOR circuit NOR1 on the non-inverting output Q side outputs "L" and the inverted output Q ^* -side 2-input NOR circuit NOR2 outputs "H". This is because it is logical.

Accordingly, the two-input NOR circuit NOR on the Q output side
When “1” becomes “H” output, the state where the Iddq abnormality occurs is determined by the test vectors TVno. (7), (11), (1)
An abnormality is detected in the holding state in 3).

As described above, the method of detecting a fault location in the sequential circuit is to set the logic of the D-type F / F and the input logic of the holding state by using one combination group test vector {TVno.
(6), (7)} and {TV no. (10), (11),
(12), (13) must be investigated.
In other words, the method of detecting a fault location in a sequential circuit is based on the fact that if a group of combinations with the previous input logic does not check whether it exists in the input logic of a normal test vector, the fault exists in that block. Is not determined.

FIG. 20 shows an embodiment of the present invention.
It is a figure which shows typically the method of dividing | segmenting SI according to a hierarchy and narrowing down a faulty block.

The hierarchical block configuration generally uses a method called “library” used at the time of design, in which analysis is performed in units of blocks prepared in advance and configured with basic circuits. In a scaled LSI,
It is expected that the number of blocks will be enormous.

Therefore, it is subdivided into an arbitrary size, and LS
It is necessary to change the block configuration inside I. At this time, what should be noted in the block configuration is that the combinational circuit and the sequential circuit must be divided into layers in one layer unit.

The reason is that, as described above, the arithmetic processing method is different between the combinational circuit and the sequential circuit.

Referring to FIG. 20, since the combinational circuit and the sequential circuit are mixed in the hierarchical division A, the combinational circuit is easily divided at the sequential circuit as a boundary (a
The fault locations are narrowed down as 1, a2, a3).

Next, in the hierarchical block a1 extracted as having a failure, the failure location is narrowed down in the hierarchical configuration (b1, b2, b3) constituting the hierarchical block a1.

Finally, the block b2, which is the “basic circuit configuration”, which is the minimum unit, is extracted.

As described above, in one embodiment of the present invention, extraction of a faulty block is performed by LS for each test vector.
From the change information of the input logic of the circuit unit having the basic logic called “block” constituting I and the test vector number information of the presence or absence of the Iddq abnormality of the LSI having the Iddq abnormality, Blocks can be extracted.

In an embodiment of the present invention, in the method of extracting a faulty block, as shown in FIG. 21, an efficient method is to use all or some test vectors in which Iddq abnormality is detected. From the input logic information of each block, a pseudo block having an input logic common to these test vectors is extracted, and then a block having an input logic common to the input logic of each block in a normal test vector is removed. By doing so, it is possible to quickly specify a failed block. This situation can be monitored on the screen by the above-described position display method of the faulty block on the LSI in the display device (see FIG. 5).

[0109]

As described above, according to the present invention,
At the time of identifying the failure location of the CMOS LSI, the failure location candidate is directly narrowed down by using the phenomenon that the Iddq abnormality has occurred. This method has the following six major effects.

(1) The first effect is that a failure location can be narrowed down irrespective of the presence or absence of an output terminal abnormality. This is the most prominent effect of the present invention.

(2) The second effect is that it is possible to easily narrow down a failure location.

That is, according to the present invention, when specifying a faulty block of an LSI, a dump list for each block based on a logic simulation used as a verification tool in an LSI design stage, and a test vector number in which an Iddq error has occurred Since it is sufficient to prepare only data, a failure location can be easily narrowed down without knowing the circuit.

Further, the above-mentioned data is obtained from the ID of the defective product.
Since only the test vector number where the dq abnormality has occurred is sufficient,
There is also an advantage that failure analysis can be performed without an actual failure.

(3) The third effect is that, together with a single stuck-at fault, a physical fault such as a multiple stuck-at fault or an open fault can be detected.

When a plurality of Iddq abnormalities, which are multiple faults, occur, first, since the through current flowing through each fault location is constant, just by reading the Iddq value for the test vector, how many fault locations occur. Can be identified, and furthermore, arithmetic processing can be performed on each of them, so that multiple faults can be easily detected.

Further, an open fault that is detected as an Iddq error causes a through current to occur through the open fault, and in the present invention, the presence or absence of the Iddq error is determined by the applied logic. This is because they can be easily analyzed as described above.

(4) The fourth effect is that the processing can be speeded up. The method of the present invention can be performed at high speed because it can be performed only by computational processing that a computer is good at. In addition, even if the LSI becomes large-scale, the operation can be performed in block units obtained by dividing the LSI, and there is an advantage that the capacity of the computer is not affected.

(5) The fifth effect is that the feedback loop of the sequential circuit, which is a problem in the analysis of a normal LSI, has no problem in the present invention.

In other words, according to the present invention, it is possible to automatically narrow down a fault location by searching a basic logic circuit unit only from the phenomenon that an Iddq abnormality has occurred. This is because the feedback loop of the sequential circuit and the repetition loop of the adder need not be particularly problematic in the present invention.

(6) The sixth effect is that the application of the present invention provides
That is, it is not related to the magnitude of the ddq outlier.

That is, in the present invention, the data required for the failure analysis is the test vector number in which the Iddq abnormality has occurred and is not related to the magnitude of the Iddq abnormality value. Also,
It is possible to narrow down the location of occurrence.

(7) The seventh effect is that, in the sequential circuit,
The identification of the failure location by detecting the Iddq abnormality may be performed by extracting the test vector in which the abnormality has occurred. Further, when the internal logic setting depends on the previous test vector, the test vector and the Iddq abnormality test may be performed. Since the combination of input logic in a vector can be used as a unit and the presence or absence of the combination can be searched from the combination of logic in other test vectors, the conventional method of narrowing down failure points by back tracing starting from output terminal abnormality You don't need to worry about repetition of logic at all.

(8) An eighth effect is that the arithmetic processing for extracting the block containing the fault location can be sequentially monitored according to the change of the test vector by the standardized display of each block. .

Furthermore, the position of the fault-incorporated block finally narrowed down can be instantaneously identified, and the data can be transferred to the fault analysis device, whereby the navigation can be performed instantaneously and the cause of the fault can be analyzed quickly.

(9) The ninth effect is that the specification of the faulty block can be executed by a calculation process using complete software.
Do not use faulty samples directly. In the present invention, the sample is mounted on the failure analysis device, and when the result is output, the coordinates can be transferred or input to the analysis device to quickly narrow down the cause of the failure. That's what it means.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining one embodiment of the present invention;
FIG. 4 is a diagram schematically illustrating a state of generation of a through current due to the presence of a physical failure.

FIG. 2 is a diagram for explaining one embodiment of the present invention;
FIG. 4 is a diagram schematically illustrating an influence of an Iddq abnormal point generated through a physical failure on an output terminal of an LSI.

FIG. 3 is a schematic diagram showing a display method of a failed block having an Iddq abnormality in one embodiment of the present invention.

FIG. 4 is a diagram for explaining one embodiment of the present invention;
It is a figure for explaining typically a standardization display (block and minimum rectangle) of each block which constitutes an internal circuit.

FIG. 5 is a diagram schematically showing a processing flow for narrowing down a failed block in one embodiment of the present invention.

FIG. 6 is a diagram for explaining one embodiment of the present invention.

FIG. 7 is a diagram for explaining an embodiment of the present invention, and is a graph showing a state in which an Iddq abnormality occurs with respect to a test vector number.

FIG. 8 is a diagram schematically illustrating a principle for narrowing down a failed block in one embodiment of the present invention.

FIG. 9 is a diagram for explaining a method of extracting a failed block from a combinational circuit according to one embodiment of the present invention;
FIG. 13 is a diagram illustrating an example of a dump list when an Iddq error occurs in one test vector in a combination circuit having 9 input terminals, and is a diagram for describing an example in which a block does not include a failure; .

FIG. 10 is a diagram for explaining a method of extracting a faulty block with respect to a combinational circuit in one embodiment of the present invention, where an Iddq abnormality has occurred in one test vector in a combinational circuit having 9 input terminals. FIG. 7 is a diagram illustrating an example of a dump list in a case, and is a diagram for describing an example in which a block has a built-in failure.

FIG. 11 is a diagram for explaining a method of extracting a faulty block for a combinational circuit in one embodiment of the present invention, in a case where an Iddq abnormality occurs in three different test vectors in a combinational circuit having an input terminal. It is a figure which shows an example of a dump list, and is a figure for demonstrating the example in which a block does not contain a failure.

FIG. 12 is a diagram for explaining a method of extracting a faulty block with respect to a combinational circuit in one embodiment of the present invention, where an Iddq abnormality occurs in three different test vectors in a combinational circuit having 9 input terminals. FIG. 9 is a diagram illustrating an example of a dump list in the case where a block has a built-in failure.

FIG. 13 is a diagram for explaining an embodiment of the present invention, in which a single fault is identified by Id at three different test vectors.
FIG. 9 is a diagram for explaining a failure occurrence phenomenon with respect to an example in which a dq abnormality is detected.

FIG. 14 is a diagram for explaining a method of extracting a defective block from a sequential circuit in one embodiment of the present invention;
FIG. 11 is a diagram illustrating an example of a dump list when an Iddq abnormality occurs in two consecutive test vectors in a sequential circuit having five input terminals, and is a diagram for describing an example in which a block does not have a built-in failure; It is.

FIG. 15 is a diagram for explaining a method of extracting a faulty block with respect to a sequential circuit in one embodiment of the present invention, where an Iddq abnormality has occurred in two consecutive test vectors in a sequential circuit having five input terminals. FIG. 7 is a diagram illustrating an example of a dump list in a case, and is a diagram for describing an example in which a block has a built-in failure.

FIG. 16 is a diagram for explaining a method of extracting a defective block from a sequential circuit in one embodiment of the present invention;
FIG. 11 is a diagram illustrating an example of a dump list when an Iddq abnormality occurs in two different test vector groups that are consecutive in a sequential circuit having five input terminals, and illustrates an example in which a block does not include a failure. FIG.

FIG. 17 is a diagram for explaining a method of extracting a defective block from a sequential circuit in one embodiment of the present invention;
FIG. 11 is a diagram illustrating an example of a dump list when an Iddq abnormality occurs in two different test vector groups that are consecutive in a sequential circuit having five input terminals, and illustrates an example in which a block has a built-in failure; FIG.

FIG. 18 is a diagram for explaining one embodiment of the present invention, and is a diagram showing a circuit configuration of a two-input D-type flip-flop.

FIG. 19 is a diagram for explaining an embodiment of the present invention, and is a diagram for explaining a feature of narrowing down a fault location of a sequential circuit represented by a two-input D-type flip-flop;
It is a table of the output logic with respect to the test vector input into the type flip-flop.

FIG. 20 is a diagram schematically illustrating a state in which a failure location is narrowed down while an LSI is divided according to a hierarchical structure in one embodiment of the present invention.

FIG. 21 is a diagram for explaining an embodiment of the present invention, in which a pseudo block having a common input logic of a test vector group in which an Iddq abnormality is detected is input into a test vector group having a normal Iddq; FIG. 9 is a diagram for describing an efficient extraction method for removing a block having input logic common to logic.

FIG. 22 is a diagram for explaining a conventional fault simulation method by creating a fault dictionary.

FIG. 23 is a diagram illustrating an example of a circuit configuration in which a signal input to a sequential circuit forms a feedback loop.

[Explanation of symbols]

 501 Test Pattern 502 Logic Simulation 503 Dump List Extraction 504 Operation Processing 505 Fault Block Extraction 506 LSI Tester 507 Iddq Abnormal Test Pattern Detection 508 Position Display of Fault Block on LSI 510 LSI

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G01R 31/28 G06F 17/50 H01L 21/822 H01L 27/04

Claims (8)

(57) [Claims] 1. A device for displaying an extraction means for extracting a fault block having a Iddq abnormality generated in the LSI, the extracted location of the fault blocks der
Therefore , in the blocks constituting the LSI,
Circuit elements in the rack and the wiring connecting the circuit elements
Origin coordinates of each block in advance with the smallest rectangle surrounding all
To the physical coordinates of each block arranged on the LSI
Matching and extracting the rectangle of the faulty block ,
A means for displaying a failure block having an Iddq abnormality in a specified portion on an LSI . 2. The logic operation information of a basic logic circuit unit (block) constituting the LSI, which changes in accordance with a test vector input from an input terminal of the LSI, and a logic vector when the test vector is applied to an input terminal of the LSI. By using the test vector number information in which the Iddq abnormality has been detected, and by performing an arithmetic process for each block, narrowing down the defective block candidates, standardizing the position of the defective block, and A method for identifying a failed block having an Iddq abnormality, wherein a position of the failed block is displayed. 3. The LSI according to claim 1, wherein said extracting means changes according to a test vector input from an input terminal of said LSI.
Logic operation information of a block which is a basic logic circuit unit constituting a test vector number, and a test vector number in which the value of Iddq which is a leakage current in a static state of the logic operation of the LSI exceeds a predetermined value for each test vector. 2. A method for identifying a faulty block having an Iddq abnormality according to claim 1, wherein a predetermined logical operation is performed using the above, and the faulty block having the Iddq abnormality is extracted. 4. The method according to claim 1, wherein the logic operation information of each block is extracted by simulation from a logic of each block which changes in synchronization with a test vector input from an input terminal of the LSI. 3. A combination of input logics of
2. A method for specifying a failed block having an Iddq abnormality according to the embodiment. 5. When extracting a faulty block by performing a logical operation for each block, a test vector number at which an Iddq abnormality occurs is generated for each block;
3. A test vector having an Iddq error according to claim 2, wherein a block in which no match is found between the test vectors is extracted as a faulty block in a test vector comparison with a test vector number in which no dq error occurs. Specification method of the faulty block. 6. A test in a test vector number in which Iddq abnormalities detected for each test vector occur continuously for each of said blocks when a faulty block is extracted by performing a logical operation for each of said blocks. In a comparison between test vectors in a vector group and an arbitrary continuous test vector number in which Iddq abnormality does not occur, a block in which the test vector group does not match is extracted as a failed block. The method for specifying a faulty block having an Iddq abnormality according to claim 2. 7. When a faulty block is extracted by performing a logical operation for each block, a test at a test vector number in which Iddq abnormalities detected for each test vector occur continuously for each block. When the vector group is detected as a combination group of a plurality of different test vectors, a block in which the test vector groups do not match in any of the test vector groups at any consecutive test vector numbers where no Iddq abnormality occurs Is extracted as a faulty block. The method of specifying a faulty block having an Iddq abnormality according to claim 2, wherein 8. An Iddq abnormality according to claim 2, wherein a combinational circuit and a sequential circuit are separated when a faulty block is extracted by performing a logical operation for each of said blocks. Specification method of the faulty block.