JP3112263B2 - Wiring short point detection method and its inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit (L).
The present invention relates to a method and an apparatus for detecting a short-circuited portion of an SI) using an abnormal power supply current phenomenon and a logic simulation, and more particularly to a method and an apparatus for visualizing and displaying a short-circuited portion.

[0002]

2. Description of the Related Art As a method of detecting a short-circuited wiring portion using software, there has conventionally been a method using an abnormal phenomenon of an expected value of an output value output from an output terminal of an LSI.

[0003] The first method is a failure simulation method by creating a failure dictionary. In this method, when a short-circuit fault is defined between individual wirings inside an LSI, an output terminal, an output value and a test pattern number relating to the fault when the fault appears are determined by the fault in the fault condition of the actual faulty product. This is a method of estimating a fault location by comparing the output terminal, the output value, and the test pattern number. Specifically, as shown in FIG. 24, the normal logic value at the output terminal when a test vector is input to the input terminal of the lower normal LSI, and the upper fault which defines a fault between the wires of the internal circuit. A failure definition position is extracted by comparing a failure definition result, which is a comparison result with a logical value at an output terminal when the same test pattern is input to an input terminal of the LSI, with a failure result of an actually failed LSI. Is the way.

[0004] The second method is called a back trace method. When an abnormality is detected, a direction from an output terminal to an input terminal is determined based on an output terminal, an output value, and a test vector number relating to the abnormality. This is a method of tracing the logic in reverse. That is, as shown in FIG. 25, when a predetermined signal is input to an input terminal of an LSI and a signal output to an output terminal is different from an expected value, a difference between the output value and the expected value is used. A signal that propagates a fault is extracted from signals that are diffused inward from an output terminal to an input terminal, a fault location is estimated, a fault is defined at that location, and a logic simulation is performed again. Is a method for verifying the coincidence with the actual failure. Usually, it is common to investigate a plurality of output abnormal locations and narrow down the fault locations while limiting the pseudo failure signal by a combination thereof.

[0005] Further, as one of the methods for detecting a short-circuited wiring using software, as a more reliable diagnosis method, a wiring short-circuit failure is detected by IDDQ (Quiescent VDD S).
A software narrowing down method called “upply current” is used, which utilizes a phenomenon in which a power supply current in a logic quiescent state usually increases on the order of mA compared to a normal value. Details of this can be found, for example, in the literature (M. Sanada; "ACAD-b
ased Approach to Fault Diagnosis of CMOS LSI with
Single Fault using Abnormal IDDQ ", 23rd Internatio
nal Symposium for Testing and Failure Analysis, pp
15-24, 1997). This method is IDDQ
This is a method of diagnosing each block of the circuit based on an algorithm for checking whether or not the same input logic as the input logic accompanied by the IDDQ abnormality exists in a normal state using the test vector number in which the abnormality has occurred. When this IDDQ abnormal phenomenon occurs, abnormal heat generation and abnormal photons due to leakage current abnormality due to wiring short-circuit failure occur. Therefore, analysis methods using those physical phenomena have been developed and put into practical use.

A related prior art is disclosed in Japanese Unexamined Patent Application Publication No.
"LSI test data generation device" described in JP-A-194418, and "C
Failure diagnosis apparatus and diagnosis method for MOS integrated circuit "and" Failure diagnosis apparatus and diagnosis method for CMOS integrated circuit "described in JP-A-10-19986.

[0007]

SUMMARY OF THE INVENTION In the above-mentioned conventional method,
All of the methods using the abnormal output phenomenon have a huge amount of simulation data and are not practical.

First, the first method, which is a fault simulation method based on the creation of a fault dictionary, can handle only single stuck-at faults (Stuck-at-0, Stuck-at-1). Since simulation was not possible, it was not common in terms of specifying failure modes. This is because the fault handled in the fault simulation is a modeled logic fault, and the short-circuit fault between signal wirings is because the logic is not determined. Further, since faults must be sequentially defined for all signal lines constituting a circuit, the number of faults to be defined is enormous. Specifically, the number of faults (V0) to be defined is said to be proportional to the third to fourth power of the number of circuit elements (L) constituting the LSI (ln (V0) ∝ (3 to 4) · ln ( L)). Therefore, the first method was not practical.

In the back tracing method which is the second method, the location where a failure occurs is limited only when a plurality of output abnormal terminals exist. The second method presupposes only the case of a single stuck-at fault, and the short-circuit fault between signal wires is different for each wire because the signal path that propagates through the signal wires is different. The diagnosis must be considered, and furthermore, the direction from the output terminal to the internal circuit in the diagnosis is the direction in which the signal expands, so a huge number of false faults are detected and narrowing down is impossible. There were drawbacks. Therefore, it is becoming difficult to narrow down the fault location purely by the back trace method.
Recently, by linking with physical analysis methods such as EBT (Electron Beam Tester), a method of eliminating pseudo-failure spots that become apparent by acquiring potential contrast images and logical operation waveforms by non-contact from failure candidates has been adopted. Tend to be. However, the method of linking the EBT is L
Even if the SI has a multilayer wiring structure, the detection region is limited to the uppermost wiring layer. Further, since the uppermost wiring layer is used as a wiring layer or a power supply wiring layer having a wider width than the lower wiring, it is becoming difficult to observe the potential of the signal wiring which is not in the uppermost wiring layer. In addition, the second method is originally intended for failure L
The greatest advantage is that the fault location can be narrowed down using only the SI output abnormality data.
Has to be newly prepared.

By a software narrowing down method utilizing the IDDQ abnormal phenomenon, a fault occurring inside a basic logic circuit block unit or a limited circuit area is eliminated.
It is possible to diagnose whether a fault is built-in based on the logic as a set of these, but in further detailed analysis, it is necessary to disassemble it into transistors and each wiring that constitutes a logic circuit block circuit etc. Diagnosis must be made using the truth table of each element to be used and the logical value of each test vector. Furthermore, an analysis method using physical phenomena requires preparation of a faulty LSI, and this analysis method requires a recent multilayer wiring structure of an LSI or a BGA (Ball Gr.
It has become difficult to detect physical phenomena due to the development of package forms such as the use of (id Array).

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and a device for detecting a short-circuited wiring portion, which can detect a short-circuited wiring portion at a high speed with a small amount of data.

[0012]

When a physical defect exists in an LSI circuit, an abnormal value appears in a power supply current in a logic quiescent state, which is generally called IDDQ. Details of this can be found, for example, in the literature (M. Sanada, "Evaluation
and Detection of CMOS-LSI with Abnormal IDDQ ", Mi
croelectronics and Reliability, vol.35, No.3, pp 6
19-629, 1995). The present invention has been made based on the finding that the above-described properties can be effectively used in detecting a short-circuited wiring portion. That is, the IDDQ abnormal phenomenon used for narrowing down the wiring short-circuited portion is a signal that makes the wiring short-circuited portion inside the LSI circuit obvious. The present invention uses a test vector when an abnormal power supply current occurs,
A method for detecting a short-circuit portion of a wiring inside I using a simulation, wherein a logical value of each wiring inside the LSI when an arbitrary test vector is set to an input terminal of the LSI is obtained by simulation, and each obtained wiring is obtained. The short circuit is characterized by displaying an image on the wiring layout of each wiring by coloring the logical value of the wiring, and detecting the wiring shorting part by the layout image in which the presence or absence of abnormal power supply current and the logical value of each wiring are color-coded. This is a location detection method. That is,
The following test vectors are used for detecting a short-circuited portion.

A test vector when an abnormal power supply current is generated. A test vector when an abnormal power supply current is not generated and a test vector when an abnormal power supply current is generated. Combination of test vector when abnormal power supply current occurs When the power supply current changes from a state where abnormal power supply current does not occur to a test vector when abnormal power supply current occurs This is a combination of test vectors or a combination of test vectors when no abnormal power supply current is generated.

The wiring for displaying the logical value for each color is as follows. In other words, all or a part of the specified signal wiring is a wiring in an area of an arbitrary size centered on an abnormality detection point in an arbitrary specified area.

The abnormal detection points are the abnormal power supply current generation points detected by the physical analysis and the appearance abnormal points detected by the appearance inspection device, and the wiring points for displaying the logical values for each color are arbitrary. Layer wiring.

A method of detecting a wiring short-circuited portion by displaying logical values classified by color on a wiring layout is as follows.
Using a computer, adjacent wires having different colors or intersecting wires are performed by using image processing.

The above-described system for detecting a short-circuited wiring portion includes: a basic logic circuit group which is a data file for designing an LSI; means for extracting arrangement information of wiring connecting the basic logic circuits; Logic simulation means for verifying the LSI internal logic that changes when a fault is input, a test system for detecting an abnormal power supply current of a faulty LSI using the test vector, a visual inspection device for each process for detecting a faulty external appearance, and a faulty LSI. It is an inspection system for detecting a short-circuited wiring, which has means for detecting a short-circuit failure by physical analysis, and computer means for processing the above information to detect a short-circuited wiring. These devices are connected on a net. Using a computer that performs the processing of Manipulating a test system for detecting short-circuit of the wiring portion.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 2, when a physical defect exists in the circuit of an LSI, IDD is a general tendency.
An abnormal value appears in the power supply current in a logic quiescent state called Q. This physical defect failure has an ID as shown in FIG.
In the test vector where the DQ error occurs, the voltage between the power supplies
By observing the state of the current characteristics (VI characteristics), various failure modes can be estimated. For details, see, for example, Japanese Patent Application No. Hei 07
No. 186973, entitled "Method and Apparatus for Identifying Failure Mode". Therefore, by observing the VI characteristics in the test vector indicating the IDDQ abnormality, it is possible to easily identify whether or not the wiring short-circuit fault is contained.

FIG. 1 is an explanatory diagram of a flow of detecting a short-circuited line by software. The short-circuited portion of the wiring is detected by preparing two pieces of data and performing computer processing. First, a test vector number at which an IDDQ error occurs is extracted from the faulty LSI. As shown in FIG. 4, the abnormal power supply current value (△ I) is obtained by inserting a resistor (r) between a power supply terminal of an LSI and an externally supplied power supply, and calculating a potential difference (△ V) generated between the resistors. It is calculated by measuring and dividing by resistance (△ I
= △ V / r). Usually, this measurement is performed inside the tester. The power supply terminal of the LSI is provided with a sense force countermeasure so that the potential drop due to the IDDQ abnormality does not affect other characteristics of the LSI circuit. The logical value of each wiring corresponding to the test vector and the layout position of each wiring inside the LSI are extracted from the connection information and the layout information of the blocks constituting the LSI and the wiring between blocks as another data. ASI generally represented by a gate array
The C-LSI is an LSI in which a desired electric circuit can be designed in a short time by extracting necessary blocks from a block library in which various circuits are registered in units of a basic logic called a block and combining them. CAD (Computer Aided Desig) when designing such an LSI
n) The above-described connection / arrangement information of the wiring is extracted from the data, and the logic information of the wiring inside the LSI for each test vector is extracted by simulation. As for the wiring information inside the block, since the internal pattern structure is designed in advance, knowing the origin coordinates and the placement direction of the block from the block placement information, the layout of the internal wiring layout of the block placed at an arbitrary position Simultaneously with the extraction, the logic information of the wiring in the block for each test vector can be extracted by simulation. The above data is input to a computer, and a logical value of a wiring (described later) at an arbitrary position in an arbitrary test vector (described later) is extracted and displayed as an image for each wiring layout. Since a wiring short occurs only in a certain shape (described later), the shape is stored in advance, and a search is performed by paying attention to the shape, and a short-circuit portion between the wires is detected.

<Test Vector> As shown in FIG.
Method using test vector in which Q abnormality has occurred, FIG.
As shown in FIG. 8, a method using a test vector when the IDDQ value changes from a normal vector to a test vector in which an IDDQ error occurs, and as shown in FIG. There is a method of using a test vector when it changes. The detection of a short-circuited portion occurring between wirings having different logical values is performed. Further, it is also possible to detect a short-circuited portion occurring between wires having different logics in wires other than the wires. Further, it is possible to detect a short-circuit point by a combination of the above-described test vectors. 5, 6, and 8 are portions where IDDQ abnormalities are continuous.

A portion between wirings having different logic values when an IDDQ abnormality has occurred is a candidate for a short-circuit portion.
Further, it is possible to narrow a short-circuited portion to a portion excluding an inter-wiring portion having a different logical value from an inter-wiring portion having a different logical value when an IDDQ abnormality has occurred. .

FIG. 7 is a diagram showing the logical value of each wiring when the IDDQ changes from normal to abnormal. By comparing the two, it is determined that the combination of the location wirings (l1, l6), (l1, l8), (l2,
17), (11, GND) and (14, 17) are narrowed down to intersections or adjacent locations.

FIG. 9 is a diagram showing the logical value of each wiring when the IDDQ changes from abnormal to normal. By comparing the two, it is found that the location where the short circuit is suspected is the combination of wirings (l1, l8), (l9, l10), (l1).
2,18) are narrowed down to intersections or adjacent locations.

By combining the results of FIG. 7 and the results of FIG. 9, the locations where a short circuit is suspected are narrowed down to the locations where the combinations (11, 18) of the wiring locations intersect as shown in FIG.

<Logical Value Display by Color> In the present invention, C
Regarding color coding of logic values in MOS LSI, see "L
The "ow" level is designated as white and the "High" is designated as black because the same color as the potential contrast image in the EBT (Electron Beam Tester) is used to analyze the LSI linked to the EBT. This is because, for example, in the case of a circuit such as an ECL (Emitter Coupled Logic) circuit in which the logic is divided into multiple stages, 2
Use more colors than colors.

<Shape of Wiring Short> Wiring short fault is a phenomenon in which a different logical line is short-circuited due to some physical fault, and an abnormal current flows between power supplies through the short-circuited portion as a path. As shown in FIG. 11, a short-circuited portion may occur at a place where logic lines of different wiring layers intersect via an insulating film, and as shown in FIG. It may occur in an adjacent part.

<Computer Processing> There are two methods for computer processing. One method is a method of performing software processing without using an image, and according to this method, a wiring short candidate location (the above-described characteristic) for all wirings in a diagnostic area (arbitrary area) is used. The computer can discriminate the matching location (elements that have been previously disassembled in the vertical and horizontal directions from all the wirings and registered as coordinates) from the LSI and from the layout. This is a method of detecting a wiring short-circuit point by extracting a crossing point between wirings or a point matching an adjacent point) and verifying a combination of different logics at the matching point. The other is a method of diagnosing by image processing, in which the above-described characteristic wiring short shape is stored in advance as an image, and a wiring is performed by searching for a target location corresponding to a test vector. This is a method for detecting a short-circuit point.

<Additional condition of wiring for displaying logical value by color>
As described above, in a system in which two data, that is, a test vector number at which an IDDQ error occurs, connection information and arrangement information of LSI internal wiring are input to a computer, and a wiring short-circuit location is diagnosed by image processing. Efficient detection is possible by restricting the wiring to be displayed by adding various conditions. Such conditions can be added only by computer simulation.

The first additional condition is a method of displaying only an arbitrary signal wiring. That is, ATPG (Automatic
Test patterns created by a tool called Test Pattern Generator) that automatically creates a test vector with high detection sensitivity while recognizing the LSI circuit structure are LSI
Inspection is performed in detail for each circuit function that constitutes. Therefore, for such a test vector, a diagnosis focusing on only the logic signal propagation in the test vector in which the IDDQ abnormality has occurred is effective. Therefore, by designating a signal propagation system in advance, only a region including a portion where the wiring is arranged is displayed, and a short-circuit portion can be detected. FIG.
Is an example of this method, and is a wiring system of interest input as output data.

The output terminal 03A of the block M006 and the signal M0 to which the signal output from the output terminal 03A is input.
10 / FCV block H02 input terminal and M013 / F
When the H02 input terminal of the BT block is designated and input, a list of the coordinates of the wiring between the output terminal and the input terminal (hereinafter referred to as “designated wiring”) and the connection relationship is output below the input. As shown in FIG. 14, the layout of the designated wiring is displayed as coordinates on the LSI, and at the same time, other wirings in the entire region surrounding the designated wiring are also displayed. The display of other wirings in the entire surrounding area is omitted). Detecting a short-circuited point in the designated wiring in this way can eliminate unnecessary searching,
This is a very efficient method.

Since the ATPG generates a pattern in one-to-one correspondence with the location to be tested, if an IDDQ abnormality occurs in the ATPG program, the location where the IDDQ abnormality occurs can be limited.
Based on the information, a short check is performed by designating an area where an IDDQ abnormality is considered to have occurred.

In the following example, in an LSI having a portion where an external appearance abnormality is detected, I / O is performed on a limited wiring detected by a test pattern generated by ATPG.
This is an example in which a DDQ abnormality has occurred. Since the diagnostic region is limited, an internal wiring focused on the region is extracted (for this method, refer to a second additional condition described later). FIG.
FIG. 5 is a display diagram according to the present invention in which a logical value is displayed in a test vector in which an IDDQ error has occurred in the entire wiring in the region. What path (L2, L3, L1
At 0), it cannot be determined whether an abnormality has occurred.

FIG. 16 is a display diagram in which a logical value is displayed in color by paying attention to a specific wiring system. By adding this additional condition, it was diagnosed that L3 and L10 in the figure clearly coincided with the cause of the short circuit. In FIG. 15, L3 is black, L1
Although 0 is white, L3 is white and ATPG is used.
If L10 is changed to black and a leak occurs, that location becomes a candidate for a short-circuit location.

The second additional condition is a method of displaying only wiring in an arbitrary area. This condition is employed, for example, when detecting a short-circuited wiring of an LSI in which a failure is narrowed down in advance. This case is, for example, a case of an abnormal appearance portion in each process by an appearance inspection device inspected in a manufacturing process. Only the coordinates of the abnormal location detected during the manufacturing process are used. Although the results of the appearance inspection at the time of the completion of the manufacturing may be used, mainly the data during the manufacturing process is used. The data of the appearance abnormality is obtained for each LSI, and in the case of a defective product, the data is reviewed and the process is evaluated.

In the case of FIG. 15, a specific circuit portion is detected, and the entire portion constituting the circuit and a region focusing only on a path through which a signal is transmitted to the circuit are designated.
In the method using the second additional condition, diagnosis is performed by designating an area centered on an abnormal location from data indicating that an abnormal location has occurred during the manufacturing process. Even if unrelated circuits are adjacent to the area, the diagnosis is performed on those circuits.

A large number of abnormal points are detected in one LSI, but only some of them grow into killer defects (defects that cause a circuit to fail), and most of the others are defective. Removed. In other words, all the abnormal appearance spots checked for each manufacturing process by the appearance inspection device do not cause any failure, and due to the advancement of cleaning technology,
Most of the detection anomalies are eliminated. However, some abnormal appearance parts may become fatal with the progress of the manufacturing process, and this is called growth. This is effective for inspecting an abnormal appearance portion that causes a wiring short-circuit failure in such an LSI.

FIG. 17 shows an example of the present method, in which it is diagnosed whether or not an abnormal point detected on the LSI is a true wiring short-circuit point. However, in the figure, only one appearance abnormality is shown). The abnormal appearance portion on the LSI is an abnormal portion detected by the appearance inspection device inspected in the manufacturing process. Normally, the coordinates of the inspection apparatus and the LSI layout are shifted by a maximum of 30 microns (the chip size of the LSI is 10 mm).
(× 10 mm), an inspection area of 30 μm × 30 μm centered on the coordinates of the abnormal appearance location is defined, and the wiring within that area is diagnosed. It is a very useful method to limit the diagnostic area for a fault whose location is limited in advance and to detect a short-circuited portion in the diagnostic area because unnecessary search can be omitted.

The other is a case where a through current flows between power supplies even in a normal state inside the LSI.

As described above, the abnormal leakage current is accompanied by the occurrence of physical abnormal phenomena such as abnormal heat generation and abnormal photons. Each of such abnormalities can be easily observed by a liquid crystal coating method or an emission microscope. However, in an LSI that has a through current even in a normal state, a through current occurrence location is also accompanied by abnormal heat generation and an abnormal photon similarly to a leak current abnormal location, and thus a through current occurrence location is detected as a pseudo failure location. I will. In such a situation, the present invention is used to detect a true failure location. That is, the diagnosis definition region is determined by observation using a liquid crystal coating method or an emission microscope.

FIG. 18 shows another example of the present system, in which a short-circuit portion of a wiring detected by a liquid crystal coating method is detected. Since an abnormal leakage current involves abnormal heat generation, it can be easily observed using a liquid crystal coating method. However, when a short-circuit fault occurs in a lower wiring portion of an LSI having a multilayer wiring structure, heat generated by the fault is transmitted while propagating through each layer to the uppermost layer, and is called a hot spot detected in the uppermost layer. Since the change in the range spreads over a large range centered on the short-circuit failure, it has been conventionally impossible to detect the failure occurrence location. On the other hand, according to the present invention, an area surrounding a hot spot is defined as a diagnostic definition area, and a wiring short-circuit point can be efficiently detected by diagnosing a wiring in the area.

The third additional condition is a method of displaying an arbitrary wiring layer. This condition is an LSI having a multilayer wiring structure.
This is a very important method for diagnosing the wiring short-circuited point. The multilayer wiring structure adopted in recent LSIs will be described. In the lower layer, the wiring of the basic circuit is configured using the wiring rule of the minimum design size. In the uppermost power supply layer, a power supply wiring having an even wider width is formed, and the power supply wiring covers the entire surface of the LSI. For such a multilayer wiring structure, it is necessary to select a wiring layer of interest and diagnose a short-circuited portion on the wiring layer. Furthermore, for example, in the case of an abnormal appearance location for each process by the appearance inspection device inspected in the manufacturing process,
Since the generation process is clear, it is not necessary to diagnose a different process (wiring layer). In such a case, it is necessary to select the wiring layer in which the appearance abnormality has been detected and diagnose the short-circuited portion. FIGS. 19 to 22 show examples in which a third additional condition is added.
This is an example of diagnosing an arbitrary area where an external appearance abnormality of I is detected. FIG. 20 shows an example in which all wiring layers constituting the region are displayed. FIG. 20 shows that IDDQ
This is an example in which a logical value in a test vector in which an error has occurred is specified for each color by specifying "Low" level as white and "High" as black. Although abnormal appearance parts are detected, L2, L
It cannot be determined in which combination of L3 and L10 a short-circuit fault has occurred. FIG. 21 is an example in which only the first layer is displayed in different colors. When the abnormal appearance is detected in the single-layer wiring process, the wiring layer is limited to the first layer as described above, and the logical value is displayed in the wiring pattern of that layer in different colors. From the image shown in FIG. 21, it can be seen that a short-circuit failure has occurred between L3 and L10. FIG. 22 shows an example in which an abnormal appearance is detected in the two-layer wiring process. By limiting the wiring layer to the second layer and displaying the wiring pattern in different colors by logical values, it can be found that a short-circuit fault has occurred between L2 and L10.

FIG. 23 is a schematic diagram of a system for detecting the short-circuited wiring portion described above, and is roughly composed of five elements.

Means for extracting basic logic circuit group information and wiring arrangement information for connecting the basic logic circuits in a data file when designing an LSI, logic for verifying the LSI internal logic that changes when a test vector is input A simulator, an LSI tester that detects an abnormality in the IDDS of the failed LSI using a test vector, an appearance inspection device that detects an appearance abnormality in each process, or a device that detects a short failure of the failed LSI by physical analysis. A main computer that processes the obtained information and displays and outputs images such as a list of wiring short points and a layout diagram of the short points for detecting wiring short points.These elements are connected by a network, and the main computer is Controls the exchange of data between elements on the network.

In the present embodiment, mainly the CMO
Although the description has been given with respect to SLSI, the scope of application is EC
It is also possible to apply to a bipolar circuit such as L. Furthermore, although the present invention relates to the detection of a short-circuited portion of a wiring, the basic invention is not limited to this, and it is apparent that the present invention can be applied to any failure diagnosis.

[0045]

As described above, the present invention is a method and an apparatus for detecting a short-circuited portion of a wiring generated inside an LSI, detects a failed portion using an IDDQ abnormal phenomenon, and visually displays the cause of the short-circuit. Is what you do.
According to the present invention, it is possible to detect a wiring short-circuit failure, which has been difficult to detect by the conventional diagnosis method using the expected output value abnormality. In addition, the present invention changes the diagnostic location to an image display once and then performs a diagnosis centered on the image, so that it is about 100 times faster than a method of detecting only an arithmetic operation without using image processing. Processing became possible. Further, the present invention defines a fault condition in which a wiring short-circuit occurs,
By storing the pattern, an abnormal portion can be detected by image recognition. Therefore, complicated processing is eliminated, and a short-circuit portion of the wiring can be detected at high speed and with high accuracy. With this concept, if the characteristics of the basic failure mode are defined for other failure modes (open failure, failure of semiconductor device (transistor, resistor, etc.), etc.), it is possible to easily detect the failure having that form. It is. According to the present invention, quick diagnosis according to the form can be performed by adding three additional conditions (arbitrary signal wiring, arbitrary area, and arbitrary wiring layer) according to the form of the wiring short-circuit failure. In particular, it is important to visually understand and explain the pattern configuration of the lower wiring in order to detect a wiring short-circuit failure caused by the lower wiring in the multilayer wiring structure. It has become an important method for LSI analysis that will progress in the future.

[Brief description of the drawings]

FIG. 1 is a flowchart of a wiring shorting point detection method according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing that an IDDQ abnormal value is detected when a physical defect exists inside a circuit of an LSI according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing estimation of various failure modes from voltage-current characteristics in a test vector in which an IDDQ abnormality occurs according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a method for measuring an IDDQ abnormal value according to an embodiment of the present invention.

FIG. 5 shows tester vector numbers and I according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating a relationship with DDQ and an output image when an IDDQ abnormality has occurred.

FIG. 6 shows tester vector numbers and I according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a relationship with DDQ and an output image when transitioning to a state where no IDDQ abnormality has occurred;

FIG. 7 is a diagram showing a location where a short circuit is detected from FIG. 6;

FIG. 8 shows tester vector numbers and I according to the embodiment of the present invention.
FIG. 7 is a diagram illustrating a relationship with DDQ and an output image when transitioning to a state where an IDDQ abnormality has occurred and a state where no IDDQ has occurred.

FIG. 9 is a diagram showing a location where a short circuit is detected from FIG. 8;

10 is a diagram showing a portion where a short circuit is suspected as shown in FIG. 7 and a portion where a short circuit is suspected as shown in FIG.

FIG. 11 is a diagram illustrating a state in which wirings of different wiring layers are short-circuited.

FIG. 12 is a diagram illustrating a state in which adjacent wirings in the same wiring layer are short-circuited.

FIG. 13 shows an output terminal and an input terminal when one output terminal of one circuit block and an input terminal of another circuit block for inputting a signal output from the output terminal are input according to the embodiment of the present invention. FIG. 9 is a diagram illustrating a manner in which coordinate values of a wiring between ends are output.

14 is a layout image corresponding to the coordinate values of the wiring described in FIG.

FIG. 15 is an image example in which the logical value of each wiring corresponding to a tester vector at the time of occurrence of an IDDQ abnormality in a diagnostic definition region centered on an appearance abnormality portion is displayed in different colors according to the embodiment of the present invention.

FIG. 16 is an example of an image in which logical values of wiring of only a specific wiring system are displayed in different colors in the example shown in FIG.

FIG. 17 is an example of a method of displaying only wiring in an arbitrary area for efficiently performing a diagnosis according to the embodiment of the present invention, and defining an area centered on an abnormal point detected on an LSI; FIG.

FIG. 18 is another example of a method of displaying only wiring in an arbitrary area for efficiently performing a diagnosis according to the embodiment of the present invention, and detecting a short-circuited wiring portion detected by a liquid crystal coating method. FIG. 9 is a diagram defining an area to be performed.

FIG. 19 is an example in which all wiring layers forming a definition area are displayed in the example shown in FIG.

20 is an example of an image in which logical values corresponding to test vectors in which an IDDQ abnormality has occurred are displayed in different colors for wiring in all layers in the example illustrated in FIG. 18;

21 is an example of an image in which logical values corresponding to a test vector in which an IDDQ abnormality has occurred are displayed in different colors for only the first layer wiring in the example shown in FIG. 18;

FIG. 22 is an example of an image in which, in the example shown in FIG. 18, a logical value corresponding to a test vector in which an IDDQ abnormality has occurred is displayed by color for only the second layer wiring.

FIG. 23 is a schematic diagram showing a configuration of a wiring short-circuit point detecting device according to an embodiment of the present invention.

FIG. 24 is one of the conventional examples, and is a failure simulation method by creating a failure dictionary.

FIG. 25 is another example of the conventional example, which is a back tracing method for tracing the logic in the reverse direction from the output terminal to the input terminal.

[Explanation of symbols]

 201 LSI placement information and logic information 202 Logic simulator 203 Tester 204 Visual inspection device 205 Physical analysis device 206 Main computer 207 Network

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28 G06F 15/60

Claims (12)

(57) [Claims] An extraction step of extracting layout information of wiring included in an LSI from design data; a simulation step of calculating a logic level of each wiring for each test vector of the LSI; and a simulation step based on the layout information and the logic level. An image generation step of generating, for each test vector, an image in which each wiring is color-coded by voltage; an abnormal power supply current detection step of detecting an abnormal power supply current of each test vector of the LSI; A wiring shorting point detecting step of detecting a wiring shorting point using image processing based on an image and information on the presence or absence of an abnormal power supply current. 2. The method according to claim 1, further comprising an abnormal point detecting step of detecting an abnormal point of the LSI, wherein in the wiring short point detecting step, candidates for the wiring short point are narrowed down to the abnormal point. 2. The method for detecting a short-circuited wiring portion according to item 1. 3. The method according to claim 2, wherein the abnormal location detecting step is an external appearance abnormal location detecting step. 4. The method according to claim 2, wherein the abnormal location detecting step is a physical abnormal location detecting step. 5. The wiring according to claim 1, wherein in the image generating step, an image for each wiring layer is generated, and in the wiring shorting point detecting step, a wiring shorting point is detected for each wiring layer. Short-circuit detection method. 6. The wiring shorting point detecting step includes detecting a shorting point between adjacent wirings having different logic levels when there is an abnormal power supply current and having the same logical level when there is no abnormal current. 2. The method for detecting a short-circuited wiring portion according to claim 1, wherein 7. In the wire shorting point detecting step, a crossing between wires having different voltages when there is an abnormal power supply current and having the same voltage when there is no abnormal current is detected as a shorting point. Claim 1 characterized by the following:
The method for detecting a short-circuited portion of a wiring described in (1). 8. An extracting means for extracting wiring layout information of an LSI from design data, a simulator for calculating a logical level of each wiring for each test vector of the LSI, and a simulator based on the layout information and the logical level. Image generating means for generating, for each test vector, an image in which each wiring is color-coded by voltage; abnormal power supply current detecting means for detecting abnormal power supply current for each test vector of the LSI; and image for each test vector. And a wiring shorting point detecting means for detecting a wiring shorting point using image processing based on information on the presence or absence of an abnormal power supply current. 9. The semiconductor device according to claim 8, further comprising an abnormal location detecting means for detecting an abnormal location of the LSI, wherein the wiring shorting location detecting / detecting means narrows the candidates for the wiring shorting location to the abnormal location. 2. A wiring short-circuit detection device according to claim 1. 10. The apparatus according to claim 9, wherein the abnormal location detecting means is an external appearance abnormal location detecting means. 11. The apparatus according to claim 9, wherein the abnormal point detecting means is a physical abnormal point detecting means. 12. The wiring according to claim 8, wherein said image generating means generates an image for each wiring layer, and said wiring shorting point detecting means detects a wiring shorting point for each wiring layer. Short-circuit detection device.