JP2800755B2 - Fault diagnosis device and diagnosis method for CMOS integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure diagnosis apparatus for a CMOS integrated circuit, and more particularly to a failure diagnosis apparatus and a failure diagnosis method for an integrated circuit for estimating a failure location of an integrated circuit from power supply current abnormality information based on Iddq test results.

[0002]

2. Description of the Related Art Conventionally, this type of CMOS integrated circuit fault diagnosis apparatus has been used for the purpose of identifying a fault location in order to determine the cause of a fault in a CMOS integrated circuit in which a fault has occurred.

For example, Japanese Patent Laying-Open No. 5-45423 proposes a configuration for obtaining a potential contrast image of an integrated circuit at high speed without deterioration in failure analysis of the integrated circuit using an electron beam tester. .

In this prior art, while driving an integrated circuit using an LSI tester, a potential contrast image is obtained in synchronism with the drive timing. At this time, a test pattern application state for obtaining the potential contrast image is obtained. Is obtained while temporarily holding the potential contrast image. In addition, in the above-mentioned JP-A-5-45423,
Temporarily hold the state of entering a certain test pattern,
A failure of the integrated circuit in which a potential contrast image is obtained at a high speed by acquiring the potential contrast in a state in which the potential contrast is longer than other test pattern input times, and the deterioration of the potential contrast due to charge accumulation (charge-up) is avoided. Analysis methods have been proposed.

Further, there are a failure diagnosis method using an emission microscope and a failure diagnosis method using a liquid crystal.
In each of these cases, it is necessary to open the device, and it is becoming difficult to specify the location of the failure due to the high integration of the integrated circuit.

[0006]

In the conventional fault diagnosis apparatus for an integrated circuit, the wiring potential of the integrated circuit is measured using an electron beam. As a result, there is a problem that it becomes difficult to measure a target wiring potential, and it becomes impossible to specify a failure portion.

In the function test of the device, no abnormality is detected in the input / output signal value, and in the case of an Iddq fault in which an abnormal power supply current flows only under a specific input condition, the conventional method is used. This is a method of tracing the wiring in which the expected signal value of the wiring on the chip in a normal device and the signal value of the wiring in the actual device are different, and identifying a failure point. There is a problem that it cannot work.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a device capable of estimating a failure location and a failure cause of a CMOS integrated circuit in which an Iddq defect is recognized. Is to provide.

[0009]

In order to achieve the above-mentioned object, the present invention provides a method for detecting an Iddq signal in which no abnormality is detected in a function test.
In the CMOS integrated circuit fault diagnosis apparatus for performing a function test result and an Iddq test result on a CMOS integrated circuit in which an Iddq abnormality occurs only in a specific pattern in a test pattern in a test, the CMO
Test pattern storage means for storing a test pattern describing input / output signals to a circuit for performing a function test of an S integrated circuit; a function test and an Iddq test of the CMOS integrated circuit as a circuit under test receiving the test pattern LSI tester for performing the above-mentioned operations, test result storage means for storing the functional test and Iddq test results, and circuit data recording element arrangement information, element function information, and wiring connection information between elements and terminals of the circuit under test. A logic simulator that inputs the test pattern and the circuit data, and logically simulates the internal operation of the circuit under test when the test pattern is applied to the device under test. Simulation result storage means for storing a simulation result inside the circuit; From the functional test result, the Iddq test result, and the simulation result, the number of “0” and “1” of the simulation result of the signal value inside the circuit at the time point when a pattern in which no abnormality is detected in the Iddq test is applied; A fault location for estimating the position of a short-circuit fault in the circuit under test based on the number of “0” and “1” of the simulation result of the signal value inside the circuit at the time point when the pattern in which the abnormality is detected in the test is applied. A failure diagnosis device for a CMOS integrated circuit, comprising:

The present invention also relates to a device under test C
A function test and an Iddq test are performed by supplying a test pattern from a test device to a MOS integrated circuit, and a test result obtained by the test device and a simulation result obtained by performing a logical simulation of an internal operation of the device under test corresponding to the test pattern With reference to the above I
a simulation result corresponding to the time point at which the ddq test applied a pattern showing no abnormality, and / or
From the simulation result corresponding to the time point at which the pattern indicating an abnormality in the ddq test was applied, the number of patterns of logic values “0” and “1” was calculated for the signal wiring inside the circuit of the device under test, respectively. A failure diagnosis method for a CMOS integrated circuit, wherein a failure of the signal wiring to a power supply line or a failure to a ground line is estimated.

According to the present invention, a function test of a CMOS integrated circuit, a result of an Iddq test, and a result of a simulation of a circuit operation are used for estimating a place where a short-circuit fault has occurred.
In the simulation result of the signal value inside the circuit corresponding to the pattern (test vector) in which the Iddq abnormality was detected by the LSI tester, and the simulation result of the signal value in the circuit corresponding to the pattern in the case where the Iddq abnormality was not detected, The position where the fault exists is estimated from the number of patterns of the logical values "0" and "1" of the line, and the location where the short-circuit fault has occurred can be quickly estimated. . In the present invention, in a test pattern for evaluating a device under test, a row composed of an input pattern and an expected value pattern at each time point (test cycle) is referred to as a pattern. The Iddq test is a CMOS test.
This is a test method used for testing short-circuit faults in integrated circuits, etc., and is referred to as Iddq test from VDD supply current Quiescent (quiescent power supply current). When a test vector is applied to a device under test and a signal is settled, The power supply current IDD of the device under test is measured.

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a diagnostic device according to an embodiment of the present invention.

Referring to FIG. 1, a test pattern storage unit 1 stores a device under test (Device Under Test;
T) is stored as a test pattern which is an input / output signal sequence for testing the function of (4). The circuit data storage unit 2 stores circuit information of the device under test DUT4. The circuit information includes information on circuit elements existing in the DUT 4, connection information between circuit elements and between input / output signal pins of the DUT 4, and information describing functional operations of the circuit elements.

The LSI tester 3 is connected to the test pattern storage unit 1 and performs a functional test on the DUT 4 connected to the LSI tester 3 based on the test pattern sent from the test pattern storage unit 1 (test from the driver of the LSI tester to the DUT 4). A functional test is performed by applying a pattern and a response output from the DUT 4 is compared with an expected value of a test pattern by a comparator), and at the same time, an abnormal power supply current does not flow for each individual pattern (also referred to as a “test vector”). Test (the power supply current I of the DUT)
DD is measured, and a comparison is made with a predetermined threshold value).

The results of the function test and the results of the Iddq test are sent to and stored in the test result storage unit 6.

The logic simulator 5 is connected to the circuit data storage unit 2 and the test pattern storage unit 1,
A simulation of a circuit operation when a test pattern is applied to the DUT 4 is executed. Then, the execution result of the logic simulation is sent to and stored in the simulation result storage unit 7.

The fault location determination unit 8 is connected to the test result storage unit 6 and the simulation result storage unit 7, and determines a failure location existing in the DUT 4 based on data sent from each of them. The determination result is output as the diagnosis result 9.

The specific operation of this embodiment shown in FIG. 1 will be described below using an example.

FIG. 2 is a circuit diagram showing an example of the DUT 4. The circuit is composed of a JK flip-flop and a NOR gate.

The circuit data storage unit 2 stores the circuit information shown in FIG.

FIG. 3 shows an example of a test pattern for the DUT.
It consists of a plurality of rows of input patterns and expected value patterns for each time point (test cycle) for evaluation (this one row is referred to as a pattern). In this case, the signals CL, R
The data in the ESET column is the signal value (applied signal) given to the DUT, and the data in the signals Q0, Q1, and Q2 are the DUT
Is the expected output value.

In FIG. 3, signal values "0" and "1" represent low-level and high-level signals, respectively.
“*” Represents “0” or “1”.

A function test of the DUT 4 is performed by the LSI tester 3 using the test pattern.

Here, the signal line S3 (N
It is assumed that the output of the OR circuit and the connection line between the second-stage JK flip-flop) have a power supply short-circuit fault. At this time,
Although the magnitude of the short-circuit resistance is sufficiently large and does not affect the logical function of the circuit itself, when the signal line S3 indicates a logical value "0", an abnormal power supply current flows through this short-circuit resistance. (Idddq failure).

As a result, the test result of the LSI tester 3 is as shown in FIG.

In this example, the function test is good (pass; pass) throughout all the patterns, and the Iddq test is the third, fourth,
A failure (Fail) is detected in the patterns 7, 8, 11, 12, 13, 14, 15, and 16, and the Iddq abnormality is not detected in other patterns.

This test result is sent to and held in the test result storage unit 6.

The logic simulator 5 performs a simulation based on the test pattern sent from the test pattern storage unit 1 and the circuit data sent from the circuit data storage unit 2, and executes the simulation of each net in the circuit when applying each pattern. Get the signal value.

As a circuit to be subjected to logic simulation,
FIG. 5 shows a simulation result when the circuit shown in FIG. 2 is used and the test pattern shown in FIG. 3 is used as the test pattern.

The simulation result is sent to and held in the simulation result storage unit 7.

The failure location determination unit 8 determines the failure location of the DUT 4 using the test results from the test result storage unit 6 and the simulation results from the simulation result storage unit 7.

A method for determining a fault location will be described below.

First, from the test results, a pattern in which no Iddq abnormality is detected (the number of the pattern that passes the Iddq test result) is extracted. Specifically, in the case of the example shown in FIG. 4, the first, second, fifth, sixth, ninth,
10, 17, and 18 patterns.

Next, each signal line (or node) in the circuit of the DUT 4 corresponding to the time point when this pattern is applied from the LSI tester 3 to the device under test (DUT) 4
Are obtained from the simulation result by the logic simulator 5.

The case of the logic circuit shown in FIG. 2 is as shown in FIG. In FIG. 6, the lowermost number m / n
Indicates the number (m) of logical values “1” and the number (n) of logical values “0”.

Here, the number of patterns (the number of pattern lines) indicating "0" and "1" is calculated for each signal line. In the example shown in FIG. 6, in the net CL, the number of patterns indicating “1” is three, and the number of patterns indicating “0” is three.

From this result, it is suspected that a signal line having zero number of patterns indicating “1” is short-circuited to the ground line, and a signal line having at least one pattern indicating “1” is suspected. There is no possibility of a short-circuit fault to the ground line.

A short circuit fault with respect to the power supply line is suspected for a net having zero patterns indicating "0", and there is no possibility of a short circuit fault with respect to the power supply line for at least one signal line.

As a result, the obtained fault candidate list is referred to as fault candidate A.

As shown in FIG. 6, in the circuit of FIG.
0 indicates a short-circuit fault to the power supply line, Q2 indicates a short-circuit fault to the ground line, S1 indicates a short-circuit fault to the power line, S2 indicates a short-circuit fault to the ground line, and S3 indicates a short-circuit fault to the power line. Suspected failure.

On the other hand, from the test results (see FIG. 4), Id
Based on the pattern in which the dq abnormality is detected, the value of the signal line inside the circuit of the DUT 4 corresponding to the time point when the pattern is applied to the DUT 4 is obtained from the simulation result.

The circuit shown in FIG. 2 is as shown in FIG.

At this time, the number of patterns indicating “0” and the number of patterns indicating “1” are calculated for each signal line.

As a result, for a net (signal line) in which the number of patterns indicating "1" is zero, a short-circuit failure to the power supply line is suspected, and a signal in which the number of patterns indicating "0" is zero is detected. For the wire, a short-to-ground fault is suspected.

This failure candidate list is referred to as failure candidate B.

As shown in FIG. 7, in the circuit shown in FIG.
It is suspected that ESET indicates a short-circuit fault to the power supply line, signal line S1 indicates a short-circuit fault to the ground line, signal line S3 indicates a short-circuit fault to the power supply line, and signal line S5 indicates a short-circuit fault to the power supply line.

The fault candidates commonly included in the fault candidate A and the fault candidate B are highly likely to be faults actually occurring in the DUT 4.

In this case, the only fault candidate commonly included in the fault candidate A and the fault candidate B is a short-circuit fault with respect to the power supply line of the signal line S3, which actually exists in the circuit shown in FIG. It is nothing but a malfunction.

The reason why a short circuit to the power line and a short circuit to the ground line are detected by the above operation will be described.

FIG. 8 is a diagram schematically showing an example of a short circuit to the power supply. In this case, when the output line of the NAND gate becomes “0”, an Iddq abnormal current flows and an Iddq abnormality is detected. However, when the output line becomes “1”, the Iddq abnormality is detected.
No ddq abnormality is detected.

That is, the simulation result of the output line of the NAND gate at the time when the pattern in which no Iddq abnormality is detected is always "1" (see "0"). If so, an Iddq abnormality should be detected).

That is, in the simulation results, the values of the gate output lines are all “1”,
Looking at the number of patterns indicating “0” and “1”,
The number of patterns indicating “0” is zero.

This also applies to the short-circuit fault to the ground line. In the case of the short-circuit fault to the ground line, the number of patterns indicating "1" becomes zero.

Also, looking at the simulation result at the time of applying a pattern in which the Iddq abnormality is detected, in the example shown in FIG. 8, when the output line of the NAND gate is "0", the Iddq abnormality is always detected. You can see that.

That is, when the simulation results are viewed at all times for all the patterns in which the Iddq abnormality is detected, it can be seen that the values of the simulation results of the output lines are all “0”.

Therefore, a signal line which is always "0" for all the patterns in which the Iddq abnormality is detected is suspected of a short-circuit failure to the power supply line, and a signal line which is always "1" is short-circuited to the ground line. Failure is suspected.

By selecting a common suspected fault from the simulation result when no Iddq error is detected and the simulation result when the Iddq error is detected, a fault actually occurring in the device is estimated. can do.

In this embodiment, the fault location is determined by the above-described operation. For all patterns in which no Iddq abnormality is detected, the sum of the expected values “0” and “1” of the internal signal lines at that time is calculated. Since only calculation is performed, this failure determination is instantaneously completed.

The result of this failure determination is output as a diagnosis result 9.

FIG. 9 is a block diagram showing the configuration of another embodiment of the present invention. A fault location judging unit 8a replaces the fault location judging unit 8 in FIG. 1 referred to in the description of the first embodiment. Is provided.

Similarly to the failure determination unit 8, the failure determination unit 8 a detects the simulation result of the value of the signal line in the circuit corresponding to the time point when the pattern where no Iddq abnormality is detected and the Iddq abnormality are detected. The total number of “0” and “1” patterns for each signal line is obtained from the simulation result of the logical value of the signal line inside the circuit corresponding to the time point when the applied pattern is applied.

Then, it is determined that the possibility of failure is high in the order from the one whose total number is close to zero (0).

For example, the Iddq
The simulation result of the logical value of the signal line inside the circuit of the DUT 4 corresponding to the time point at which the pattern in which no abnormality is detected is applied indicates that the total number of “0” of the internal signal line S1 is “1” and that of the internal signal line S2 Assuming that the total number of "1" is "2" and the total number of "0" of the internal signal line S3 is "3", the possibility of the internal signal line S1 being short-circuited to the power supply line is the highest. It is determined that the possibility of the short-circuit of the internal signal line S2 to the ground line and the short-circuit of the internal signal line S3 to the power supply line decrease in this order.

This determination is made for some reason.
For example, since the Iddq current is smaller than a predetermined threshold, an Iddq abnormality should normally be detected. However, since no Iddq abnormality was detected, it is determined that there is no Iddq abnormality, and the total number of “0” and “1” is calculated. In consideration of an error in the calculation, this is dealt with by indicating the possibility of failure.

FIG. 10 is a block diagram showing a configuration of still another embodiment of the present invention. In the present embodiment, a wiring layout information storage unit 10 and a short-circuit point estimation unit 11 are newly added.

The wiring layout information storage unit 10 stores the arrangement information of each wiring on the chip of the circuit of the DUT 4 and the correspondence information between each signal line.

The short-circuit point estimation unit 11 obtains the diagnosis result 9
The location information of the short-circuit fault is obtained from the CPU and the location where the short-circuit fault actually occurs is indicated on the chip. This indicates a portion where the respective wirings in which a short-circuit fault has occurred intersect or a portion which is close to each other. The result is
This is output as the short-circuit position estimation result 12.

[0069]

As described above, the CM according to the present invention is used.
The OS integrated circuit failure diagnosis apparatus uses the functional test of the CMOS integrated circuit, the Iddq test result, and the simulation result of the circuit operation to estimate the location where the short-circuit fault has occurred, and uses the inside of the circuit when the Iddq abnormality is detected. The position where the fault exists is estimated from the number of “0” and “1” of each signal line in the simulation result of the signal value of “1” and the simulation result of the signal value inside the circuit when the Iddq abnormality is not detected. Therefore, it is possible to quickly estimate the location where the short-circuit fault has occurred.

Further, by utilizing the correspondence relationship with the wiring on the signal line integrated circuit chip and the wiring layout information having the positional information of the wiring on the chip, the position on the chip where the failure actually occurs is indicated. It is possible to

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a failure diagnosis device according to an embodiment of the present invention.

FIG. 2 is a diagram for describing an embodiment of the present invention, and is a diagram illustrating an example of a circuit of a device under test.

FIG. 3 is a diagram for explaining an embodiment of the present invention, and is a diagram illustrating an example of a test pattern of the device under test of FIG. 2;

4 is a diagram for explaining an embodiment of the present invention, and is a diagram illustrating an example of a function test result and an Iddq test result of the circuit of FIG. 2;

FIG. 5 is a diagram for explaining an embodiment of the present invention, and is a diagram illustrating an example of a result of a logic simulation of the circuit of FIG. 2;

FIG. 6 is a diagram for explaining an embodiment of the present invention, and is a diagram illustrating a signal value inside a circuit when a pattern in which no Iddq abnormality is detected is applied.

FIG. 7 is a diagram for explaining an embodiment of the present invention, and is a diagram showing a signal value inside a circuit when a pattern in which an Iddq abnormality is detected is applied.

FIG. 8 is a diagram for explaining an embodiment of the present invention, and is a schematic diagram for explaining the principle of failure detection of the failure portion determination unit.

FIG. 9 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of still another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test pattern storage unit 2 Circuit data storage unit 2 LSI tester 4 DUT 5 Logic simulator 6 Test result storage unit 7 Simulation result storage unit 8 Failure location determination unit 8a Failure location determination unit 9 Diagnosis result 10 Wiring layout information storage unit 11 Short circuit location Estimation unit 12 Short-circuit position estimation result

Claims (8)

(57) [Claims] 1. A CMOS integrated circuit in which an abnormality is not detected in a function test and an Iddq error occurs in only a specific pattern in a test pattern in an Iddq test.
CM using function test results and Iddq test results
In the fault diagnosis device for an OS integrated circuit, a test pattern storing means for storing a test pattern describing input / output signals to a circuit for performing a function test of the CMOS integrated circuit; and a circuit under test receiving the test pattern. The CMO
LSI for performing functional test and Iddq test of S integrated circuit
A tester; test result storage means for storing the functional test and Iddq test results; and circuit data for storing circuit data recording element arrangement information, element function information, and wiring connection information between elements and terminals of the circuit under test. Storage means, a logic simulator that inputs the test pattern and the circuit data, and logically simulates an internal operation of the circuit under test when the test pattern is applied to the device under test; A simulation result storage unit for storing an internal simulation result; and a simulation of a signal value inside the circuit at a time point when a pattern in which no abnormality is detected in the Iddq test is applied from the function test result, the Iddq test result, and the simulation result. The number of “0” and “1” of the result, and I The position of the short-circuit fault in the circuit under test is estimated based on the number of “0” and “1” of the simulation result of the signal value inside the circuit at the time point when the pattern in which the abnormality is detected in the dq test is applied. A fault diagnosis device for a CMOS integrated circuit, comprising: a fault location determining means. 2. The system according to claim 1, wherein said failure location determination means is "0" or "1".
2. The CMOS according to claim 1, wherein the degree of a suspected failure is weighted based on the number of the failures to estimate the failure location.
Fault diagnosis device for integrated circuits. And a wiring layout information storing means for storing wiring layout information describing wiring position information and signal line information on a chip of the circuit under test. 2. A fault diagnosis apparatus for a CMOS integrated circuit according to claim 1, wherein a position on the chip where a fault has actually occurred is indicated based on the wiring layout information. 4. A function test and an Iddq test are performed by supplying a test pattern from a test apparatus to a CMOS integrated circuit which is a device under test, and a test result by the test apparatus and the test target corresponding to the test pattern are performed. A simulation result obtained by performing a logic simulation of the internal operation of the device; and a simulation result corresponding to a time point at which the Iddq test applied a pattern that does not indicate an abnormality, and / or
From the simulation result corresponding to the time point at which the pattern indicating an abnormality in the Iddq test was applied, the number of patterns of logical values “0” and “1” was calculated for the signal wiring inside the circuit of the device under test, respectively. Estimating a short-circuit fault of the signal wiring to a power supply line or a short-circuit fault to a ground line. 5. A simulation result corresponding to a time point at which a pattern showing no abnormality in the Iddq test is applied, the signal wiring having a logic number “1” having zero patterns has a short-circuit fault with respect to the ground line. 5. The method according to claim 4, further comprising: estimating that there is a high possibility, and estimating that there is a high possibility of a short-circuit fault with respect to a power supply line for a signal wiring having zero patterns indicating a logical value "0". A failure diagnosis method for a CMOS integrated circuit according to the above. 6. A simulation result corresponding to a time point at which a pattern indicating an abnormality in the Iddq test is applied, the signal wiring having a logic value of “1” having zero patterns is capable of short-circuit failure to a power supply line. 5. The method according to claim 4, wherein a signal wiring having a zero number of patterns indicating a logical value "0" is estimated to have a high possibility of a short-circuit fault to a ground line. 5. The method for diagnosing a failure of a CMOS integrated circuit according to claim 5. 7. A simulation result corresponding to a time point at which a pattern showing no abnormality in the Iddq test is applied. The number of patterns showing a logical value "1" is closer to zero than the number of signal wirings. 5. The method according to claim 4, further comprising: estimating that there is a high possibility, and estimating that the possibility of a short-circuit fault with respect to the power supply line is high in the order of signal wirings having a logical value of “0”, which is close to zero. A failure diagnosis method for a CMOS integrated circuit according to the above. 8. A simulation result corresponding to a time point at which a pattern indicating an abnormality in the Iddq test is applied, the number of patterns indicating a logical value of “1” can be short-circuited to a power supply line in order from a signal wiring having a number of patterns close to zero. 5. The method according to claim 4, further comprising: estimating that there is a high possibility of occurrence of a short-circuit fault to the ground line in order from a signal wiring having a pattern number indicating a logical value “0” close to zero. 8. The method for diagnosing a failure of a CMOS integrated circuit according to claim 7.