JP4945403B2 - Device for estimating failure location of semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a failure location estimation device for a semiconductor integrated circuit, and more particularly to a failure location estimation device for a semiconductor integrated circuit in which short failure candidate wirings are narrowed down using failure diagnosis software or a failure analysis device.

  Conventionally, the static power supply current (IDDQ) test has been utilized as a test method that can easily improve the leak test quality in a semiconductor integrated circuit (LSI) using a CMOS circuit. In a CMOS circuit in which the external input is fixed and the operation is stable, there is no current path flowing between VDD and GND. Therefore, only a very small off-leakage current flows in a normal CMOS circuit. Therefore, if a fault that causes an abnormality in current exists in the LSI using the CMOS circuit, the fault can be easily detected. In the leak test by the static IDDQ test, a semiconductor integrated circuit in which a static IDDQ exceeding a certain threshold flows is detected as a defective product using the above characteristics.

  Several methods have been proposed for narrowing down fault locations using the IDDQ measurement values obtained by the IDDQ test and using the LSI wiring expected value simulation by the test pattern used in the IDDQ test and the LSI layout information in combination (for example, Patent Documents). 1 and 2). However, in an LSI having several mega gates or more, the IDDQ measurement value acquired for narrowing down failure candidates increases, so that the diagnosis time for narrowing down failure candidates inevitably becomes enormous. If there are a plurality of narrowed failure candidates, it is necessary to perform an electrical failure analysis in order to narrow down the failure candidates.

  In addition, as a test method with high observability of the LSI internal state, the SCAN test that controls the state by using the FF circuit in the LSI as a shift register and the LSI internal as a combinational circuit is widely used. Several failure location narrowing methods have been proposed that use the results together with an LSI wiring expected value simulation based on the test pattern used in the SCAN test and LSI layout information (for example, Patent Document 3). However, since failure candidates are diagnosed based on the output result from the LSI tester, there are usually a plurality of short failure candidate locations, and it is necessary to perform electrical failure analysis in order to narrow down failure candidates.

  An analysis method using a failure diagnosis result by conventional IDDQ diagnosis or SCAN test diagnosis will be described with reference to FIG. Referring to FIG. 18, failure diagnosis step S1501 performed based on test pattern DB 11, LSI netlist (logic circuit connection information) DB 12, failure LSI fail log DB 13, layout information DB 14, emission, OBIRCH, EB tester, etc. The failure location narrowing-down step S1502 by the failure analysis apparatus and a failure cause investigation step (physical analysis) S1503 by physical observation of the failure location by flat polishing, FIB, SEM, TEM or the like.

  Three main failure analysis methods used in failure location narrowing step S1502 will be described.

  Electron beam (EB) tester analysis is the logic information (potential contrast image, logic operation waveform) of the wiring signal of the internal circuit while the LSI installed in the chamber of the EB tester (basically SEM) is driven by the LSI tester. ) In a non-contact manner. Main functions include potential contrast image (contrast image corresponding to wiring potential (white: low potential, black: high potential)), voltage waveform (signal waveform of any internal wiring), strobe operation analysis (time (picosecond order) Analysis of logic propagation state). Principle in which secondary electron detection amount increases / decreases by surface potential When an electron (primary electron) is irradiated from the electron gun to the LSI surface, secondary electrons are generated from the LSI surface. The energy distribution of the secondary electrons has a correlation with the wiring potential of the LSI, and the positive potential shifts to the smaller left side with respect to the energy distribution at the time of grounding. By providing a grid between the LSI and the secondary electron detector, detecting only secondary electrons having potential energy higher than the grid potential and comparing the number of secondary electrons, the wiring potential of the LSI can be relatively determined. .

  Emission analysis is a method for detecting weak light emission in the visible to near-infrared region of LSI and other semiconductor elements and specifying the position thereof. Photons emitted from a sample to which voltage is applied are collected by a microscope and detected by an image processing apparatus through an optical amplifier using a microchannel plate or a CCD or InGaAs element. If there is a junction leak or an insulating film breakage, when a voltage is applied, the electric field concentrates on the defective part and hot carriers are generated. And light is emitted when it recombines.

The OBIRCH analysis is to detect an abnormal current portion related to metal such as wiring. While biasing the sample to be observed, a change in IDDQ is displayed as a change in luminance at each point of the CRT corresponding to each point in the scanning region while scanning the laser beam with the region to be observed. For example, the resistance increases due to the temperature rise at the moment when a laser beam is irradiated at a location where a defect (void, Si alloyed portion) having poorer heat conductivity than Al, which is a constituent material of wiring, appears as a current decrease.
Japanese Patent Laid-Open No. 10-19986 JP 2007-24523 A JP 11-160400 A Tetsuto Uchikaku, 5 others, “Analysis TAT / Success Rate Improvement Method from Failure Diagnosis Using IDDQ Test to Investigation of Failure Cause”, LSI Testing Symposium / 2005, November 9, 2005, p. 243-248

  The following analysis was made by the present inventors.

  The first problem is that it takes time and money to perform a failure analysis of a multi-layered semiconductor integrated circuit using a conventional failure diagnosis result. This is because most of the current semiconductor integrated circuits have five or more wiring layers, and analysis from the device surface by three typical and major failure analysis methods has the following restrictions.

  As a restriction of the electron beam (EB) tester analysis, pad processing by FIB is necessary in order to carry out EB analysis of a net covered with upper layer wiring in a multi-layer LSI. If there are more than 10 failure candidates, the time required for analysis is determined by the FIB processing schedule rather than the schedule for EB analysis. In addition, there is a high risk that failure will not be reproduced by FIB processing multiple times (non-defective product return or disconnection due to charge inflow during ion beam irradiation, failure due to short circuit formation with other wiring during pad formation).

  As a limitation of emission analysis, light emission due to a short fault between signal lines is a cell that receives a signal of a net driven by a cell with a low driving capability in most cases if there is a difference in the driving capability of the cell driving the short net. Since only light is emitted, information on the short net on the side not accompanied by light emission cannot be obtained. In addition, in a multi-layer LSI, at least 50% of the entire layout and at most 90% of the entire layout are covered with upper wiring, and there is little leakage from the surface of light emission due to electron-hole recombination in the diffusion layer. In principle, light emission detection is difficult.

  As a limitation of OBIRCH analysis, the OBIRCH reaction of a short failure between signal lines usually reacts only in a cell having a low driving capability if there is a difference in the driving capability of the cell driving the short net. It is mentioned that the information about the short net is not available. Further, in a multi-layer wiring LSI, at least 50% of the layout and at most 90% of the layout are covered by the upper layer wiring, resistance change due to laser irradiation hardly occurs in the lower layer wiring, and it is difficult in principle to detect the OBIRCH reaction. Furthermore, the number of packages that are difficult to observe on the back side is increasing due to the stacking of multiple chips and the cost reduction of devices, and the number of LSIs that are difficult to analyze from the back side that can avoid observation through the wiring layer is increasing. .

  The second problem is that there are many cases where the cause of the failure cannot be clarified even if physical analysis such as peeling analysis or cross-sectional observation is performed using the conventional failure diagnosis result. The reason for this is that the failure points are not sufficiently narrowed down, so the area that must be observed in the physical analysis is too large, and the failure candidates that cannot be observed, or observation errors may occur due to mistakes during observation. Because.

  Therefore, it is an object to provide a failure location estimation apparatus that can reduce the time and cost required for failure analysis by efficiently narrowing short failure locations between wirings of a semiconductor integrated circuit.

A failure location estimation apparatus according to a first aspect of the present invention is a failure location estimation apparatus for a semiconductor integrated circuit in which failure candidate wiring pairs that may cause a short failure have been narrowed down in advance by failure diagnosis software or a failure analysis device. Then, for each of the plurality of test patterns , the expected value of the signal in the first wiring and the expected value of the signal in the second wiring included in the failure candidate wiring pair are input, and the exclusive OR ( a XOR operation unit that is configured to output seeking XOR), enter the IDDQ measured value of the semiconductor integrated circuit for each of the plurality of test patterns, when IDDQ measured value entered is greater than a predetermined threshold value to 1 in the IDDQ quantizing portion configured to output quantized to zero in other cases, it of the plurality of test patterns A comparison unit configured to compare the XOR and the quantized IDDQ, find the number of matches, and output a failure candidate wiring pair having a higher number of times as a higher possibility of failure. It is characterized by.

  A fault location estimation apparatus according to a second aspect of the present invention is a fault location estimation apparatus for a semiconductor integrated circuit in which fault candidate wiring that may cause a short fault is narrowed down in advance by fault diagnosis software or a fault analysis apparatus. An expected value calculation unit configured to calculate an expected value of the failure candidate wiring for each of a plurality of test patterns, and an IDDQ measurement value of the semiconductor integrated circuit for each of the test patterns, and the input IDDQ measurement IDDQ quantizer configured to quantize and output to 1 if the value is greater than a predetermined threshold, and to 0 otherwise, and output the expected value and the quantized value for each of the test patterns Compare with IDDQ, find the number of times of coincidence, and have a high possibility of short-circuit failure between the failure candidate wiring with a large number of times And outputting the results as of, it is characterized in that a comparison unit configured to output a fault candidate interconnection that the small number as likely to short-circuit failure of the power supply line.

  A failure location estimation apparatus according to a third aspect of the present invention is a failure location estimation apparatus for a semiconductor integrated circuit in which failure candidate wiring pairs that may cause a short failure have been narrowed down in advance by failure diagnosis software or a failure analysis device. A driving capability calculation unit configured to calculate a driving capability according to the parallel number of transistors constituting each gate for the gate driving each of the wirings included in the failure candidate wiring pair, and the failure candidate wiring When there is a difference in the drive capability between the failure propagation path estimation unit configured to estimate a path through which a fault propagates from each of the wirings included in the pair and the gates, the drive capacity of the failure candidate wirings It is highly probable that the failure propagates only downstream of the wiring driven by the low gate, as confirmed by the estimated route. And when there is no difference between the drive capabilities of the two gates, the failure propagates downstream of both wirings included in the pair of the failure candidate wiring pairs or is included in the pair There is a possibility that a failure output is generated only by the failure propagation from the other wiring, and that the failure propagation from the other wiring is masked by the downstream circuit and does not propagate to the failure detection unit, and the failure is confirmed by the estimated route. And a drive capability comparison unit configured to output a high output.

  A fault location estimation apparatus according to a fourth aspect of the present invention is a fault location estimation apparatus for a semiconductor integrated circuit in which fault candidate wiring pairs that may cause a short fault are narrowed down in advance by fault diagnosis software or a fault analysis apparatus. For each of the plurality of test patterns, an on-current calculating unit configured to calculate an on-current of a gate that drives the failure candidate wiring pair based on an expected value of an input wiring of the gate; and the test pattern An IDDQ quantizer configured to input an IDDQ measurement value of each of the semiconductor integrated circuits to each of them, quantize the input IDDQ measurement value into a value of three or more according to the magnitude, and the test The on-current and the quantized IDDQ measurement value are compared for each pattern, the number of coincidence is obtained, and the failure is frequent. Further comprising a comparison unit configured to output as a high possibility of failure as auxiliary wire pair and said.

  The first effect is that the time and cost required for failure analysis can be reduced by efficiently narrowing down short-circuit failure locations between wires of the semiconductor integrated circuit. The reason is that it is not necessary to implement various failure analysis methods that are performed by linking with the LSI tester, and the time and cost required for short failure analysis of the semiconductor integrated circuit can be reduced.

  The second effect is that the increase / decrease in the IDDQ value caused by the short circuit failure can be measured regardless of the large increase / decrease in the IDDQ measurement value for each non-defective semiconductor integrated circuit test pattern. The reason is that since the IDDQ value of the non-defective product is used as a reference, only the IDDQ measurement value in the reliable test pattern can be selected.

  The third effect is that the accuracy of the analysis can be improved as compared with the case where the analysis is performed using the failure diagnosis result without using the IDDQ measurement value in combination. The reason is that since the narrowed-down results are ranked, actual analysis can be performed from the most likely failure candidates.

  The fourth effect is that a short failure between the signal line of the semiconductor integrated circuit and the power supply line or the ground line is estimated in advance, and the failure analysis is efficiently performed. The reason is that the failure candidate wiring can be narrowed down by comparing the quantized IDDQ value in each test pattern with the expected value of the failure candidate wiring.

  The fifth effect is that the time required for failure diagnosis using the IDDQ value is reduced. The reason is that a typical failure diagnosis can be completed in a few minutes because the IDDQ value is collated after narrowing down the combinations of failure candidate wirings. Note that in the case of the conventional IDDQ diagnosis in which the IDDQ value is checked against the failure candidate wiring pairs existing in the entire chip, it may take one day or more to complete.

(First embodiment)
The failure location estimation apparatus according to the first embodiment of the present invention refers to a failure log acquired by an LSI tester, and is an estimation result obtained by an existing failure diagnosis software, or failure candidate wiring narrowed down by failure analysis. Refer to The value obtained by providing a threshold value for the IDDQ measured in each test pattern and the exclusive OR of the expected value of the combination of the short fault candidate wirings are compared, the number of coincidence is integrated, and the fault candidate wiring having a large number of times is added. Are narrowed down as short failure candidates, and adjacent locations are narrowed down as short failure candidate locations and output.

  FIG. 1 is a diagram illustrating an input / output example of the failure location estimation apparatus according to the first embodiment of the present invention. The failure location estimation apparatus according to the present embodiment refers to failure candidate wiring (FIG. 1A) narrowed down by existing failure diagnosis software or failure analysis, and obtains a failure candidate wiring pair (FIG. 1B) that may cause a short failure. Means for storing, means for storing a value (FIG. 1C) quantized into binary values by providing a threshold value for the IDDQ measurement value in each test pattern of the semiconductor integrated circuit, and expectation at the time of test pattern input of the failure candidate wiring pair The means for storing the exclusive OR of the values (FIG. 1D), the exclusive OR operation of the expected value of the failure candidate wiring pair in each test pattern, and the quantized IDDQ value are compared, and they match. And a means for ranking the combinations of failure candidate wirings having a high number of times as candidates having a high possibility of short-circuit failure, and outputting the ranked failure candidate wiring pairs (FIG. 1E).

  The failure candidate estimation device according to the present embodiment weights the failure candidates by the number of times that the exclusive OR of the expected value of the failure candidate wiring pair and the quantized IDDQ match in each test pattern. Can be narrowed down.

  Here, the effect of the failure location estimation apparatus of the present embodiment will be described with reference to FIG. In FIG. 16A, the failure location is narrowed down to either the input signals of the 2-input AND cell (wiring 1 and wiring 2) or between one of the inputs and the output (wiring 2 and wiring 3). And Further, in a test pattern in which a short fault is activated, it is assumed that a through current flows between VDD and GND via a shorted wiring and IDDQ increases, and one of the expected values of a shorted wiring pair is zero. In other words, the other is 1 and must be contradictory.

  The failure location estimation apparatus calculates and stores the expected values of the wirings 1 to 3 in each test pattern. Further, a threshold is provided for IDDQ, and a value larger than the threshold is quantized to 1 and a smaller value is quantized to 0 and stored. Further, the combinations of failure candidates are narrowed down by comparing the XOR of the expected values of the wirings 1 and 2 and the XOR of the expected values of the wirings 2 and 3 with the quantized IDDQ.

  Referring to FIG. 16B, when the XOR of the expected value of wiring 2 and wiring 3 and the quantized IDDQ are compared for each test pattern, they match each other for each test pattern. Therefore, a wiring pair composed of the wiring 2 and the wiring 3 is extracted as a wiring having a high possibility of short circuit failure (FIG. 16C). The 2-input AND operation is a logical operation that outputs 1 only when both of the two input signals are 1, and the 2-input XOR operation is a logical operation that outputs 1 only when there is a difference between the two input signals. .

(Second Embodiment)
The fault location estimation apparatus according to the second embodiment of the present invention is based on the result of narrowing down fault candidate wiring by the estimation result of the existing fault diagnosis software executed based on the fail log acquired by the LSI tester or the fault analysis. refer. The failure location estimation apparatus compares the result of calculating the driving ability determined by the parallel number of transistors constituting the gate that drives the short failure candidate wiring with the result of estimating the path through which the failure propagates from the short failure wiring. The failure location estimation device uses a combination of failure candidate wiring in which a failure signal propagates only from wiring driven by a gate with a small driving capability, and a failure signal propagates from both nets driven by gates having the same driving capability. The failure output can be explained only by the combination of the failure candidate wiring and the failure propagation from one wiring, and the failure signal from the other wiring is masked by the downstream circuit and does not propagate to the failure detection unit And a combination of failure candidate wirings that can be confirmed from the estimated route and a combination of short failure candidate wirings.

  FIG. 6 is a block diagram showing a configuration of the failure candidate specifying unit 26 in the failure location estimating apparatus according to the second embodiment of the present invention. Referring to FIG. 6, the failure candidate specifying unit 26 outputs a combination of failure candidate wirings based on a result (FIG. 1A) of narrowing down failure candidate wirings using an existing failure location estimation apparatus or failure analysis. 261, a driving capability comparison unit 262 that compares the driving capability according to the parallel number of transistors that constitute a gate that drives the failure candidate wiring, and a failure candidate wiring that is driven by a transistor having a small driving capability from the failure propagation estimation path The failure output can be explained only by the failure propagation from both of the combination of failure candidate wirings with the same driving ability or the propagation of the failure from only one of the wirings, or the failure wiring from one wiring. From the estimated path, it is confirmed that the failure signal from is masked by the downstream circuit and does not propagate to the failure detection unit. It is or not, and an output unit 263 for outputting the extraction result of each combination of to fault candidates wire determines, provided with operates to extract the fault candidates pairs.

  According to the failure location estimation apparatus according to the present embodiment, by extracting the combination of short failure candidate wirings by comparing the drive capability of the failure candidate wires and the estimated route of failure propagation, the failure candidate locations can be narrowed down. Can be achieved.

(Third embodiment)
The failure location estimation apparatus according to the third embodiment of the present invention determines the magnitude of the on current determined by the number of transistors that constitute the gate that drives the failure candidate wiring in each test pattern as the number of transistors that are turned on in parallel. Based on the expected value of the input wiring of the gate that drives the wiring, a threshold value is provided for the IDDQ of the semiconductor integrated circuit measured in each test pattern, the IDDQ is quantized by the threshold value, and the magnitude of the on-current in each test pattern The number of times that the size of the quantized IDDQ matches is accumulated, and the failure candidate wiring is weighted and output according to the number of times.

  FIG. 7 is a block diagram showing a configuration of the failure candidate specifying unit 27 in the failure location estimating apparatus according to the third embodiment of the present invention. Referring to FIG. 7, failure candidate specifying unit 27 outputs a combination of failure candidate wirings based on the result of narrowing down failure candidate wirings using an existing failure location estimation apparatus or failure analysis (FIG. 1A). 271 and a comparison unit that compares the magnitude of the on-current of the gate driving the failure candidate wiring in each test pattern with the magnitude of each IDDQ test pattern quantized by providing a threshold value for the IDDQ measurement value of the fault LSI 272 and based on the comparison result, the number of times that the magnitude of each of the test patterns of the ON current of the gate driving the failure candidate wiring matches the magnitude of each of the quantized IDDQ test patterns is integrated, and the number of times is large. Ranking the combinations of failure candidate wirings as candidates with a high possibility of short-circuit failure, and outputting the result of narrowing down failure candidate locations by ranking And a power unit 273 operates to output a combination of fault candidates narrowed down.

  According to the failure location estimation apparatus according to the present embodiment, short-circuiting is performed by performing weighting with a value obtained by integrating the number of times that the on-current magnitude of the failure candidate wiring and the magnitude of the quantized IDDQ value in each test pattern match. Failure points can be narrowed down efficiently.

(Fourth embodiment)
The failure location estimation apparatus according to the fourth embodiment of the present invention assumes a case where the IDDQ value of a non-defective LSI is remarkably different for each test pattern. That is, in each test pattern, the IDDQ measurement value is input, and the IDDQ measured in the non-defective product is pointed to the test pattern, and when the IDDQ measurement value after subtraction is larger than a predetermined threshold, 1, Otherwise, it is quantized to zero. Further, the quantized IDDQ and the value obtained by performing an exclusive OR operation on the expected value of the combination of the short fault candidate wirings are compared, the number of times of matching is added, and the combination of the fault candidate wirings with a large number of times is added to the short fault candidate Narrow down as a short fault candidate location and output it.

  FIG. 13 is a block diagram showing the configuration of the IDDQ difference calculation unit 30 in the failure location estimation apparatus according to the fourth embodiment of the present invention. Referring to FIG. 13, the failure location estimation apparatus according to the present embodiment measures the IDDQ value in each test pattern of the non-defective product and the failed LSI, calculates a difference, and calculates the difference IDDQ value. An IDDQ quantization unit 302 that quantizes the IDDQ value by providing a threshold value, a comparison unit 303 that compares the XOR of the expected value of the combination of the quantized IDDQ value and the failure candidate wiring, and the failure candidate wiring based on the comparison result And an output unit 304 that outputs a weighting result for each combination, and operates to calculate a combination of narrowed failure candidates.

  By calculating the difference between the non-defective LSI and the failed LSI by calculating the IDDQ value in each test pattern by the failure location estimating apparatus according to the present embodiment, the IDDQ quantized by subtracting the variation of the IDDQ value in each test pattern Using the values, failure candidate locations can be narrowed down.

(Fifth embodiment)
In the failure location estimation apparatus according to the fifth embodiment of the present invention, when the IDDQ value of a non-defective LSI is remarkably different for each test pattern, and the increase or decrease in IDDQ due to a short failure cannot be detected, the non-defective IDDQ value is determined for each test pattern. Measurement is performed to extract a pattern address having a small IDDQ value, obtain an IDDQ value of the faulty LSI only with the extracted pattern address, set a threshold value, quantize the IDDQ value with the threshold value, failure candidate wiring, Compare the expected value of the adjacent wiring combination with the value obtained by performing an exclusive OR operation, add up the number of times of matching, narrow down the combinations of fault candidate wiring that have a large number of times as short fault candidates, and short the adjacent parts Narrow down and output as failure candidate locations.

  FIG. 14 is a block diagram showing a configuration of a normal IDDQ test pattern extraction unit in the failure location estimation apparatus according to the fifth embodiment of the present invention. The failure location estimation apparatus according to the present embodiment measures a IDDQ value in each test pattern of a non-defective LSI and extracts a test pattern that takes a normal IDDQ value, and an extracted pattern address The IDDQ value of the faulty LSI is measured and the IDDQ quantizing unit 312 for quantizing the IDDQ value by setting a threshold value for the measured value is compared with the XOR of the expected value of the combination of the quantized IDDQ value and the fault candidate. A comparison unit 313 and an output unit 314 that outputs a weighting result for each combination of failure candidates based on the comparison result, and operates to calculate a narrowed combination of failure candidates.

  According to the failure location estimation apparatus according to the present embodiment, IDDQ in each test pattern is acquired from a non-defective LSI, and a test pattern that takes a normal IDDQ value is extracted, thereby increasing or decreasing the IDDQ value due to a short failure. The failure candidate locations can be narrowed down using only the quantized IDDQ of the test pattern that can detect.

(Sixth embodiment)
The fault location estimation apparatus according to the sixth embodiment of the present invention is based on the result of narrowing down fault candidate wiring by the estimation result of the existing fault diagnosis software executed based on the fail log acquired by the LSI tester or the fault analysis. Referring to the IDDQ measured in each test pattern with a threshold value quantized and the expected value of failure candidate wiring in each test pattern, the number of matches is integrated, and the number of matches is high Candidate wiring is narrowed down as a short fault candidate with the ground line, and fault candidate wiring with a small number of matches is narrowed down as a short fault candidate with the power supply line and output as a fault candidate.

  FIG. 15: is a block diagram which shows the structure of the comparison part of IDDQ in the failure location estimation apparatus which concerns on the 6th Embodiment of this invention. The failure location estimation apparatus according to the present embodiment calculates an expected value for each test pattern of the failure candidate wiring based on the result of narrowing down the failure candidate wiring by the existing failure location estimation device or failure analysis (FIG. 1A). An expected value calculation unit 321, an IDDQ quantization unit 322 that measures an IDDQ value of a faulty LSI with the pattern address, sets a threshold value for the measurement value, and quantizes the IDDQ value; an expected value of the failure candidate wiring; A comparison unit 323 that compares the quantized IDDQ value, and an output unit 324 that accumulates the number of times of matching in each test pattern based on the comparison result and outputs a weighting result for each failure candidate wiring based on the number of times. Prepared and operates to calculate the narrowed failure candidate wiring.

  The failure location diagnosis apparatus according to the present embodiment compares the quantized IDDQ in each test pattern with the expected value of the failure candidate wiring, and uses the weight of the short failure with the power supply line or the ground line to Candidate wiring can be narrowed down.

(Seventh embodiment)
A failure location estimation apparatus according to a seventh embodiment of the present invention will be described with reference to the drawings. The data processing apparatus 2 in the failure location estimation apparatus according to the present embodiment includes an XOR operation unit 22, an IDDQ quantization unit 23, and a comparison unit 24 as illustrated in FIG. The XOR operation unit 22 inputs the expected value of the wiring included in the failure candidate wiring pair for each of the plurality of test patterns, and obtains and outputs an exclusive OR (XOR). The IDDQ quantizing unit 23 inputs IDDQ measurement values of the semiconductor integrated circuit corresponding to these test patterns. When the input IDDQ measurement value is larger than a predetermined threshold value, the IDDQ quantization unit 23 quantizes it to 0. Output. The comparison unit 24 compares the XOR and quantized IDDQ in each test pattern for each failure candidate wiring pair, finds the number of matches, and outputs the failure candidate wiring pair having a higher possibility as a failure. To do.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram schematically showing the configuration of input information and output information in the failure location estimation apparatus according to the first embodiment of the present invention. 1 is a list of failure candidate wirings narrowed down by the failure analysis apparatus or failure candidate wirings narrowed down by the failure diagnosis software (FIG. 1A), and list information of combinations of wirings adjacent to the failure candidate wirings. (FIG. 1B), IDDQ value information quantized by a threshold based on IDDQ values measured for each test pattern (FIG. 1C), XOR operation information of expected values of combinations of failure candidate wirings (FIG. 1D), This is information (FIG. 1E) of failure candidate wiring that is output by weighting the combination of failure candidates based on the above four data.

  The list information (FIG. 1A) of the failure candidate wirings narrowed down by the failure analysis apparatus or the failure candidate wirings narrowed down by the failure diagnosis is the instance name of the narrowed failure candidate wiring and the failure type of the failure candidate wiring (when narrowed down by failure diagnosis). , Ranking of failure candidate wiring.

  The list information (FIG. 1B) of combinations of fault candidate wirings and neighboring wirings includes the instance name of the neighboring wiring for each narrowed failure candidate wiring and the neighboring coordinates for each neighboring wiring.

  The IDDQ value information (FIG. 1C) quantized by the threshold value based on the IDDQ value measured for each test pattern is provided with threshold values for the IDDQ value and IDDQ value of the non-defective product LSI and the failed LSI measured for each test pattern. IDDQ values quantized with a value larger than the threshold value as 1 and a smaller value as 0 are included.

  The information on the XOR operation of the expected value of the combination of failure candidate wirings (FIG. 1D) includes the expected value of the combination of failure candidate wires calculated for each test pattern and the result of performing the XOR operation based on the expected value. .

  The failure candidate wiring information (FIG. 1E) that is output by weighting the combinations of failure candidates is the data obtained by comparing the XOR operation and the quantized IDDQ value for each failure candidate wiring combination, It includes proximity coordinates and wiring layer data for each combination, and threshold data used for IDDQ quantization.

  FIG. 2 is a diagram illustrating the configuration of the failure location estimation apparatus according to the first embodiment of the present invention. Referring to FIG. 2, the failure location estimation apparatus according to the present embodiment includes an input device 1 including a keyboard or an external interface unit, a data processing device 2 that operates under program control, a hard disk and a memory that record information, and the like. Storage device 3 and an output device 4 such as a display device or a printing device which is an interface unit with the outside.

  The storage device 3 includes a circuit information storage unit 31, a failure candidate storage unit 32, an IDDQ measurement value storage unit 33, and a quantization IDDQ storage unit 34.

  The circuit information storage unit 31 stores the expected value (that is, the logic state) of each signal line when the circuit in each test pattern is normal, the net name of the signal line adjacent to each signal line, and the proximity coordinates. ing.

  The circuit information storage unit 31 also includes a logic circuit configuration on the path that is found to be related to the failure by failure analysis or failure diagnosis, that is, the type of gate, the connection relationship between the gates, the connection relationship between the gate and the signal line, the signal The connection relationship between lines is stored.

  The failure candidate storage unit 32 stores the failure candidate wiring, the failure type of the failure candidate wiring, the logical state of the failure candidate wiring, and the proximity coordinates of the wiring adjacent to the failure candidate wiring, which are the results narrowed down by failure analysis or logic failure diagnosis. is doing.

  The IDDQ measurement value storage unit 33 stores IDDQ measurement values of the failed LSI and the non-defective LSI in each test pattern.

  The quantized IDDQ storage unit 34 stores a value obtained by quantizing the IDDQ measurement value of the failed LSI in each test pattern by providing a threshold value, and the threshold value.

  The data processing device 2 includes a failure candidate narrowing unit 21 that is implemented by failure analysis or failure diagnosis by a failure analysis device linked to an LSI tester, an XOR operation unit 22 for an expected value of a combination of short failure candidate wires, and IDDQ quantization. Unit 23, XOR operation comparison unit 24 of the expected value of the combination of quantized IDDQ and short failure candidate wiring, and the number of coincidence in each test pattern is integrated based on the comparison result, and short failure is based on the number A failure candidate specifying unit 25 for weighting and outputting combinations of candidate wirings.

  The failure candidate narrowing-down unit 21 refers to the circuit information storage unit 31, and results of narrowing down the faults in the circuit, that is, failure candidates, failure types, and error observation nodes from which errors arrive and are detected from the failure candidates Are stored in the failure candidate storage unit 32.

  The XOR operation unit 22 of the expected value of the combination of short failure candidate wirings refers to the circuit information storage unit 31 and the failure candidate storage unit 32, and the XOR operation result based on the expected value of the combination of each failure candidate wire in each test pattern In other words, exclusive OR calculation information for calculating 0 when the expected values of the combinations of failure candidate wirings are the same and 1 when they are different is recorded in the failure candidate storage unit 32.

  The IDDQ quantizing unit 23 refers to the IDDQ measurement value storage unit 33 to obtain a quantized IDDQ value in each test pattern, that is, a threshold value based on the IDDQ measurement value and an IDDQ measurement value larger than the threshold value. 1. A value obtained by quantizing a small IDDQ measurement value as 0 is recorded in the quantized IDDQ storage unit 34.

  The comparison unit 24 of the XOR operation between the quantized IDDQ value and the expected failure candidate value includes the quantized IDDQ value in each test pattern stored in the quantized IDDQ storage unit 34 and each test stored in the failure candidate storage unit 32. The XOR operation result based on the expected value of each failure candidate wiring combination in the pattern is referred to, and the quantized IDDQ value in each test pattern is compared with the XOR operation result in each failure candidate wiring combination. The integrated value of the number of times of coincidence is calculated for each combination of failure candidate wirings and recorded in the failure candidate storage unit 32.

  The failure candidate specifying unit 25 refers to the failure candidate storage unit 32 and collates the quantization IDDQ value in each test pattern for each combination of failure candidate wirings and the XOR operation result in each failure candidate wiring combination. Then, the integrated value of the number of times of coincidence is calculated for each combination of failure candidate wirings, and a candidate having a larger number of times of coincidence is ranked as a candidate having a higher possibility of failure and is output to the output device 4.

  FIG. 4 shows an example of a detailed configuration of the XOR operation unit 22 of the combination of failure candidate wirings in FIG. Referring to FIG. 4, the XOR operation unit 22 for the combination of failure candidate wirings calculates the expected value of the failure candidate combination net, the short partner estimation unit 221 for the failure candidate wiring, the expected value calculation unit 222 for the combination of failure candidate wirings, And an XOR operation unit 223 based on the above.

  The short partner estimation unit 221 that estimates the short partner of the failure candidate wiring refers to the circuit information storage unit 31 and the failure candidate storage unit 32, selects the selected fault candidate wiring, the net adjacent thereto, and the proximity candidate The proximity coordinates for each combination are stored in the failure candidate storage unit 32, and information on the combination of failure candidate wirings is transmitted to the expected value calculation unit 222 of the failure candidate wirings.

  The expected value calculation unit 222 refers to the information about the combination of failure candidate wirings and the expected value of each signal line stored in the circuit information storage unit 31, and calculates the expected value for each combination of failure candidate wirings. The result is transmitted to the XOR operation unit 223.

  The XOR operation unit 223 performs an XOR operation with an expected value for each combination of failure candidate wirings as input, and records the operation result for each test pattern in the failure candidate storage unit 32.

  FIG. 5 is a diagram illustrating an example of a detailed configuration of the IDDQ quantization unit 23 of FIG. Referring to FIG. 5, the IDDQ quantization unit 23 includes an IDDQ measurement value sorting unit 231 that performs sorting based on the magnitude of IDDQ measurement values, and an IDDQ measurement value grouping unit that performs grouping based on the magnitude of IDDQ measurement values and determination of a threshold value. 232 and an IDDQ quantization processing unit 233 that performs IDDQ quantization using the determined threshold.

  The IDDQ measurement value sorting unit 231 sorts the IDDQ measurement values based on the IDDQ measurement data based on the IDDQ measurement data sorted in the test pattern order stored in the IDDQ measurement value storage unit 33, and the result is the IDDQ measurement value. The data is transmitted to the grouping unit 232.

  The IDDQ measurement value grouping unit 232 classifies the data into two groups having a certain range of IDDQ values (threshold values) based on the data sorted according to the size of the IDDQ values, and transmits the result to the IDDQ quantization processing unit 233. .

  Based on the IDDQ measurement threshold, the IDDQ quantization processing unit 233 performs a quantization process that sets a value larger than the threshold to 1 and a value smaller than the threshold to 0, and quantizes the IDDQ value in each test pattern. Record in the quantized IDDQ storage unit 34.

  FIG. 3 is a flowchart showing the operation of the failure location estimation apparatus according to the first example of the present invention. With reference to FIGS. 1-5, operation | movement of the failure location estimation apparatus which concerns on the 1st Example of this invention is demonstrated in detail.

  First, the failure candidate narrowing unit 21 narrows down failure candidate wirings by narrowing down failure candidates using a failure analysis device linked to a tester or by narrowing down by failure diagnosis (step A1). The example of the narrowed failure candidate list (FIG. 1A) is an example of a candidate list by failure diagnosis performed without using IDDQ measurement values. Examples of narrowing down failure candidates using a failure analysis device linked to a tester include (1) electron beam (EB) tester analysis, (2) emission analysis, and (3) OBIRCH analysis.

  The short partner estimation unit 221 that estimates the short partner of the failure candidate wiring with reference to the circuit information storage unit 31 records the short failure candidate net close to the failure candidate wiring and the coordinates thereof in the failure candidate storage unit 32 (step). A2). FIG. 1B is an example of a result of extracting layout information as a wiring adjacent to the failure candidate wiring N10 illustrated in FIG. 1A.

  Next, the circuit information storage unit 31 and the failure candidate storage unit 32 are referred to, and the expected value calculation unit 222 that calculates the expected value of the short failure candidate wiring pair stores them in the logic circuit information storage unit in each test pattern. The expected value of the failure candidate wiring and the wiring adjacent thereto are recorded in the failure candidate storage unit 32 (step A3), and the result of the XOR operation unit 223, which receives the expected value of the combination of the failure candidate wirings as an input, is stored in the failure candidate storage. It records in the part 32 (step A4). FIG. 1D shows the result of performing an XOR operation for each combination of failure candidate wirings in each test pattern.

  On the other hand, the IDDQ measurement value of the failed LSI in each test pattern acquired by the LSI tester is acquired and recorded in the IDDQ measurement value storage unit 33 (step A5).

  With reference to the IDDQ measurement value storage unit 33, the IDDQ measurement value sorting unit 231 sorts the data into IDDQ measurement value data in order of magnitude (step A6) and transmits the data to the IDDQ measurement value grouping unit 232.

  Based on the IDDQ measurement value data in order of magnitude, the IDDQ measurement value grouping unit 232 sets a threshold value for the IDDQ value, separates it into two groups (step A7), and performs an IDDQ quantization processing unit 233 that performs quantization using the threshold value. Send to.

  The IDDQ quantization processing unit 233 quantizes a value larger than the threshold value to 1 and a value smaller than the threshold value to 0, and stores them in the quantized IDDQ storage unit 34 (step A8). FIG. 1C shows the result of quantizing the IDDQ measurement value of the failed LSI in each test pattern based on the threshold value.

  Next, referring to the failure candidate storage unit 32 and the quantization IDDQ storage unit 34, the comparison unit 24 of the XOR operation means of the expected value of the quantization IDDQ and the short failure candidate combination in each test pattern is used. The expected number of XOR and the quantized IDDQ value are compared and the number of times of matching is added (step A9), and the result is transmitted to the failure candidate specifying unit 25.

  The failure candidate specifying unit 25 accumulates the number of times that the quantized IDDQ value in each test pattern matches the expected value XOR in each failure candidate wiring pair, and a failure candidate wiring pair having a large number of times can be short-circuited. The result of ranking as a candidate with high probability is output. The number of coincidence between the quantized IDDQ and the expected value XOR of each failure candidate wiring pair in each test pattern was integrated, and the failure candidate wiring pairs having a higher number of times were ranked as candidates having a high possibility of short failure. The result is shown in FIG. 1E.

  Next, with reference to FIG. 6, the failure location estimation apparatus which concerns on the 2nd Example of this invention is demonstrated in detail with reference to drawings.

  FIG. 6 is a block diagram illustrating the configuration of the failure location estimation apparatus according to the present embodiment. Referring to FIG. 6, the fault location estimation apparatus according to the second embodiment includes a fault candidate narrowing unit 261 that narrows down fault candidate wirings using a fault analysis apparatus or fault diagnosis software, and a driving capability of a gate that drives the fault candidate wirings. And a drive capability comparison unit 262 for confirming the failure propagation estimation route and an output unit 263 for outputting the extraction result of the combination of failure candidate wirings.

  The failure candidate narrowing-down unit 261 that narrows down the failure candidate wirings by the failure analysis device or the failure diagnosis software, when the combination of failure candidate wirings cannot be narrowed down to one set, selects failure candidate wirings from the combination of a plurality of failure candidate wirings. The driving ability is calculated from the parallel number of transistors constituting the driving gate and the fault propagation estimation path, or the fault propagates only from the fault candidate wiring driven by the transistor having the small driving ability, or the driving ability is equal. The failure output can be explained only by the failure propagation from one of the combinations of the failure candidate wirings or the failure propagation from one wiring, and the failure signal from the other wiring is masked by the downstream circuit Conditions of the drive capability comparison unit 262 and the drive capability comparison unit 262 for confirming from the estimated path whether or not the detection unit will propagate to the detection unit Possibility of short-circuit failure combinations fault candidates wiring outputs the narrowing result of the output unit 263 thus fault candidate is extracted as high candidates satisfying.

  FIG. 9A is a flowchart showing the operation of the failure location estimation apparatus according to the second example of the present invention. With reference to FIG.6 and FIG.9A, operation | movement of the failure location estimation apparatus which concerns on the 2nd Example of this invention is demonstrated. The failure location estimation apparatus according to the present embodiment determines whether the combination of failure candidates has been narrowed down to a single set by ranking (step C1) by narrowing down the failure candidate wirings using the existing failure location estimation device or failure analysis. (Step C2), if it has not been narrowed down (NO in Step C2), the driving ability of the gate that drives the failure candidate wiring and the driving ability comparison unit 262 that refers to the failure propagation path, from one of the short failure candidate wirings If a failure propagates only, a pair of wires whose driving capability of the gate that drives the failure candidate wiring through which the failure propagates is lower than the driving capability of the gate that drives the failure candidate wiring that does not propagate the failure is extracted or driven. Fault output can be explained only by fault propagation from one of the two lines driven by gates with equal capacity, When the failure signal from one of the wires is masked by the downstream circuit and is not propagated to the failure detection unit, the wire pair that can be confirmed by the estimated route is extracted, and the failure propagates from both short failure candidate wires Then, combinations having the same driving ability of the gates that drive the failure candidate wirings are extracted (step C3).

  In step C3, it is determined whether the combination of failure candidates is narrowed down to one set (step C4). If narrowed down (YES in step C4), the process ends. If not (NO in step C4), narrowing down by other short failure candidate specifying means is performed (step C5).

  Next, with reference to FIG. 7, a failure location estimation apparatus according to a third embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 7 is a block diagram showing the configuration of the failure location estimation apparatus according to the third example of the present invention. Referring to FIG. 7, the fault location estimation apparatus according to the third embodiment of the present invention includes a fault candidate narrowing unit 271 that narrows down fault candidate wirings using a fault analysis apparatus or fault diagnosis software, and fault candidates in each test pattern. Comparing unit for accumulating the number of times that the relative magnitude of the on-current proportional to the number of transistors that are turned on in parallel among the transistors constituting the gate for driving the wiring matches the IDDQ value quantized with a plurality of threshold values 272 and an output unit 273 that outputs a weighting result of a combination of failure candidate wirings by a value obtained by integrating the number of times of matching.

  In the failure candidate narrowing unit 271 that narrows down the failure candidate wirings by the failure analysis device or the failure diagnosis software, when a combination of failure candidate wirings cannot be narrowed down to one set, a combination of a plurality of failure candidate wirings is set in each test pattern. A comparison unit 272 that compares the magnitude of the on-current proportional to the number of transistors that are turned on in parallel among the transistors that constitute the gate that drives the failure candidate wiring and the magnitude of the IDDQ value quantized with a plurality of threshold values, The number of coincidence of the two is integrated, and a failure candidate narrowing result is output by an output unit 273 that ranks and outputs combinations of failure candidate wirings having a large number of coincidence as candidates with high possibility of failure.

  FIG. 9B is a flowchart showing the operation of the failure location estimation apparatus according to the third example of the present invention. With reference to FIGS. 7 and 9B, the operation of the failure location estimation apparatus according to the third embodiment of the present invention will be described. It is determined whether the combination of failure candidates has been narrowed down to one set by ranking by narrowing down the failure candidate wirings by using the existing failure location estimation device or failure analysis (step C6), and when the narrowing is not narrowed down (step C7) ( In step C7, the IDDQ measurement value is quantized by a change in on-current that is proportional to the number of transistors constituting the gate that drives the failure candidate wiring in each test pattern being turned on in parallel and a plurality of threshold values. Based on the IDDQ value and the comparison number 272 of both, ranking is performed on the basis of the number of matches for each combination of failure candidate wirings, and the failure candidate narrowing result is obtained by the output unit 273 that outputs the failure candidate narrowing result ( Step C8).

  When the combination of failure candidates is narrowed down to one set by the above narrowing down (YES in step C9), the narrowing down of failure candidates ends. If not (NO in step C9), narrowing down by other short failure candidate specifying means is performed (step C10).

  Next, with reference to FIG. 13, a failure location estimation apparatus according to a fourth example of the present invention will be described in detail with reference to the drawings.

  FIG. 13 is a block diagram showing a configuration of a failure location estimating apparatus according to the fourth embodiment of the present invention. Referring to FIG. 13, a failure location estimation apparatus according to a fourth embodiment of the present invention includes a difference calculation processing unit 301 that calculates an IDDQ difference between a non-defective product LSI and a failed product LSI, and an IDDQ quantum that quantizes an IDDQ difference value. The comparison unit 303 for comparing the quantization unit 302, the quantized IDDQ, and the XOR operation of the expected value of the combination of failure candidate wires, and the output unit for ranking the combinations of failure candidate wires by the comparison unit 303 and outputting the results 304 is provided.

  The failure location estimation apparatus according to the present embodiment has a significant increase / decrease in the IDDQ measurement value in each test pattern of a non-defective LSI, and when it is difficult to quantize only with the IDDQ value of the failure LSI, the good LSI in each test pattern The difference calculation processing unit 301 that calculates the difference between the IDDQ value of the non-defective product and the IDDQ value of the defective product LSI subtracts the increase / decrease depending on the non-defective product IDDQ value in each test pattern. The IDDQ difference value that is increased or decreased by the IDDQ quantization unit 302 is quantized by the comparison unit 303 that compares the quantized IDDQ value with the XOR operation of the expected value of the combination of the failure candidate wirings, An output that narrows down the failure candidates by ranking based on the number of matches for each failure candidate wiring pair and outputs the failure candidate narrowing results By 304 to obtain a refined result of the failure candidates wire pair.

  Next, with reference to FIG. 14, a failure location estimation apparatus according to a fifth example of the present invention will be described in detail with reference to the drawings. FIG. 14 is a block diagram showing a configuration of a failure location estimating apparatus according to the fifth embodiment of the present invention. Referring to FIG. 14, the failure location estimation apparatus according to the fifth embodiment includes a test pattern extraction unit 311 for extracting a test pattern having an IDDQ value in a normal range from an IDDQ measurement value of a non-defective LSI, and a non-defective IDDQ measurement. An IDDQ quantization unit 312 that quantizes the IDDQ value of the defective LSI with a pattern address in a normal range, and a quantized IDDQ of the defective LSI with a pattern address in which a non-defective IDDQ measurement value is in a normal range A comparison unit 313 that compares the XOR operation of the expected value of the combination of the value and the failure candidate wiring, and an output unit 314 that ranks the combination of the failure candidate wiring by the comparison unit 313 and outputs the result.

  There is a significant increase or decrease in the IDDQ measurement value for each test pattern of the non-defective LSI, and the large IDDQ measurement value reaches the upper limit of the IDDQ measurement range. Even if the difference between the IDDQ value of the defective LSI and the non-defective LSI is taken, it is caused by a short failure. When the increase / decrease in the IDDQ value cannot be measured, the test pattern extraction unit 311 that extracts a test pattern having a normal range of IDDQ values from the IDDQ measurement value of the non-defective LSI takes a difference between the IDDQ values of the defective LSI and the non-defective LSI. The IDDQ value in the test pattern that can measure the increase / decrease in the IDDQ value due to the short fault is extracted, and based on the result, the IDDQ quantizing unit 312 that quantizes the IDDQ value of the faulty LSI is measured. Of defective products with pattern addresses in the normal range The comparison unit 313 that quantizes the DDQ value and compares the quantized IDDQ with the XOR operation of the expected value of the combination of the failure candidate wirings accumulates the number of times of matching, and obtains the number of times of matching for each combination of failure candidate wirings. In accordance with the ranking, the failure candidates are narrowed down, and the output unit 314 that outputs the failure candidate narrowing down obtains the result of narrowing down combinations of failure candidate wirings.

  Next, with reference to FIG. 15, a failure location estimation apparatus according to the sixth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 15 is a block diagram of a failure location estimating apparatus according to the sixth embodiment of the present invention. Referring to FIG. 15, the failure location estimation apparatus according to the sixth embodiment includes an expected value calculation unit 321 that calculates an expected value of a failure candidate wiring, an IDDQ quantization unit 322 that quantizes an IDDQ measurement value using a threshold value, and The comparison unit 323 that compares the quantized IDDQ value with the expected value of the failure candidate wiring, and the output unit 324 that outputs the ranking result of combinations of short faults between the failure candidate wiring and the power supply line or the ground line by the comparison unit 323 It has.

  If the failure candidate wiring pair cannot be specified by the means for narrowing down the combination of failure candidate wirings described in the above embodiment, the comparison unit 323 compares the quantized IDDQ and the expected value of the failure candidate wiring. The expected value of the candidate wiring and the quantized IDDQ are compared, the number of coincidence of the two is integrated, and ranking based on the number of coincidence for each failure candidate wiring is performed to narrow down the failure candidates. The output unit 324 that outputs a ranking result of combinations of short faults between the fault candidate wiring and the power supply line or the ground line sets fault candidates that have a large number of times the expected value of the fault candidate wiring matches the quantized IDDQ as the ground line. As the short fault candidates, fault candidates with a large number of times that the expected value of the fault candidate wiring does not match the quantized IDDQ are ranked and output as short fault candidates with the power supply line.

  A failure location estimation apparatus according to a seventh embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5 and FIG.

  Fault candidate wiring is narrowed down by the fault candidate narrowing unit 21 in FIG. 2 (step A1).

  The short partner estimation unit 221 (FIG. 4) that estimates the short partner of the failure candidate wiring refers to the circuit information storage unit 31 and uses the existing layout information search system and approaches the fault candidate wiring in the circuit. The wiring is recorded in the failure candidate storage unit 32 as a combination of short failure candidates (step A2). For example, as shown in FIG. 1A, if the wiring name of the narrowed failure candidate wiring is determined to be N10 by narrowing down failure candidates using a failure analysis device linked to a tester or narrowing down by failure diagnosis, existing layout information search is performed. Using the system, as shown in FIG. 1B, information on the wiring names N30, N31, N21 of the wirings adjacent to the failure candidate wiring N10 in the semiconductor integrated path and the proximity coordinates thereof can be obtained.

  Next, the expected value calculation unit 222 (FIG. 4) for the combination of short failure candidates refers to the circuit information storage unit 31 and the failure candidate storage unit 32, and calculates the expected value for each test pattern for each combination of failure candidates. Obtained (step A3) and recorded in the failure candidate storage unit 32.

  Next, with reference to the failure candidate storage unit 32, an XOR operation is performed on each test pattern of the combination of failure candidate wirings (step A4) and recorded in the failure candidate storage unit 32. For example, as shown in FIG. 1D, the result of performing the XOR operation based on the expected value of the failure candidate wiring in each test pattern and the wiring adjacent thereto is recorded in the failure candidate storage unit 32.

  On the other hand, IDDQ is measured in each test pattern shown in FIG. 10, and recorded in the IDDQ value measured value storage unit 33 (step A5).

  Next, the IDDQ measurement value data sorted in the order of each test pattern is sorted in order of the IDDQ measurement value (step A6).

  Next, the data sorted in the descending order of IDDQ measurement values are grouped for each range of IDDQ values (step A7). For example, referring to the graph of IDDQ measurement values in each test pattern of the failed LSI in FIG. 10, it can be classified into four groups according to the IDDQ value. Among the four groups, an IDDQ value that can distinguish a group having the smallest IDDQ from other groups is used as a threshold value.

  Next, data quantized by providing a threshold value for the IDDQ measurement value is acquired (step A8). For example, as a means for determining the threshold value, IDDQ measurement values sorted by the test pattern are sorted by the magnitude of the IDDQ measurement values, and the difference between adjacent IDDQ measurement values is taken, and the IDDQ measurement in which the difference takes a large value. Use the value as a threshold. When there are a plurality of IDDQ measurement locations where the difference takes a large value, the IDDQ value at the location where the IDDQ value is the smallest is used as the threshold value. An IDDQ value larger than the threshold is set to 1, and an IDDQ value smaller than the threshold is set to 0 for quantization.

  By comparing the expected value XOR of the failure candidate wiring pair shown in FIG. 1D and the quantized IDDQ shown in FIG. 1C, the number of times the two match is obtained (step A9).

  The count result of the number of times of coincidence is output (step A10), and when the combination of failure candidates is narrowed down to one set by narrowing down, the narrowing down ends.

  The failure location estimation apparatus according to the eighth embodiment will be described in detail with reference to FIGS. 1, 6, 8, and 11. FIG.

  FIG. 8 is a flowchart showing the operation of the failure location estimating apparatus according to the eighth embodiment of the present invention. As shown in FIG. 1E, when the combination of failure candidates cannot be narrowed down to one set in the process of step B1 (NO in step B2), the drive capability of the gate that drives the failure candidate wiring is driven. A comparison is made by calculating from the parallel number of transistors constituting the gate (step B3). For example, when the gate that drives the failure candidate wiring N10 shown in FIG. 1E is the 3-input NOR shown in FIG. 11 and the gate that drives the neighboring wiring N20 is the 2-input NAND shown in FIG. is there. Therefore, when N10 and N20 are short-circuited, the failure propagates only downstream of N10. If it can be estimated by failure diagnosis that the failure has propagated only from N10, this failure candidate wiring pair can explain the failure diagnosis result without contradiction, and therefore becomes a higher-order failure candidate.

  On the other hand, if it can be estimated by the fault diagnosis that the fault has propagated downstream of both N10 and N20, this fault candidate wiring pair has a contradiction in the fault diagnosis result, and thus becomes a lower fault candidate. .

  Of the failure candidate wiring pairs shown in FIG. 1E, if the failure candidate wiring pairs are narrowed down to one set by referring to the match between the XOR operation result and the quantized IDDQ and the gate drive capability, the narrowing down ends.

  The failure location estimation apparatus according to the ninth embodiment will be described in detail with reference to FIGS. 1, 7 to 9, 11, and 12.

  As shown in FIG. 1E, when the combination of failure candidates cannot be narrowed down to one set by the failure location estimation apparatus according to the eighth embodiment (NO in step B4 in FIG. 8), failure candidate wirings in the respective test patterns are set. A change in on-current proportional to the number of transistors constituting the gate to be driven turned on in parallel is compared with a change in IDDQ value quantized to a value of three or more by a plurality of threshold values (step B5).

  For example, when the gate that drives the failure candidate wiring N10 shown in FIG. 1E is the three-input NOR shown in FIG. 11 and the gate that drives the neighboring wiring N20 is the two-input NAND shown in FIG. The ratio is 2 to 8. For this reason, the through current flowing between the power source and the GND due to the short circuit depends on the ON current of the three-input NOR.

  Since the magnitude of the on-current of the three-input NOR is inversely proportional to the on-resistance of the input gate, the on-current ratio is 3 to 1 when the expected value of the three inputs coincides with that when only one input is one.

  FIG. 12 shows the magnitude of the on-current that flows as a through current when the output wiring of the 3-input NOR is the wiring 1 and the output net of the 2-input NAND is the wiring 2 and the expected values of the wiring 1 and the wiring 2 are in conflict. It is a thing.

  When the expected values of the wiring 1 and the wiring 2 are contradictory, the magnitude of the current passing through between VDD and GND depends on the expected value of the input net of the three-input NOR. For example, when the IDDQ measurement value in each test pattern of the failed LSI is as shown in FIG. 10, it can be quantized with four values {0, 1, 2, 3} by three threshold values.

  When the magnitude of the on-current of one of the combinations of failure candidate wirings is a triangle (Δ) in the graph of FIG. 12 and the magnitude of the quantized IDDQ value is a circle (◯) in the graph of FIG. Therefore, it can be estimated that a short-circuit occurs at a location near the failure candidate wiring pair.

  Although the above description has been made based on examples, the present invention is not limited to the above examples.

It is the figure which showed the input-output example of the failure location estimation apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the failure location estimation apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the failure location estimation apparatus which concerns on 1st Example of this invention. It is a block diagram which shows the structure of the XOR calculating part in 1st Example of this invention. It is a block diagram which shows the structure of the IDDQ quantization part in 1st Example of this invention. It is a block diagram which shows the structure of the failure candidate specific | specification part in the failure location estimation apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the failure candidate specific | specification part in the failure location estimation apparatus which concerns on the 3rd Embodiment of this invention. It is a flowchart which shows operation | movement of the failure location estimation apparatus which concerns on the 8th and 9th Example of this invention. It is a flowchart which shows operation | movement of the failure location estimation apparatus which concerns on the 2nd and 3rd Example of this invention. It is a figure which shows the threshold value for quantizing an IDDQ measured value and its value. This is an equivalent circuit of 3-input NOR (output gate 3W). It is a figure which shows the magnitude | size of the on-current which flows as a through current. It is a block diagram which shows the structure of the IDDQ difference calculation part in the failure location estimation apparatus which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the normal IDDQ test pattern extraction part in the failure location estimation apparatus which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the structure of the comparison part of IDDQ in the failure location estimation apparatus which concerns on the 6th Embodiment of this invention. It is a figure for demonstrating operation | movement of the IDDQ diagnosis by the failure location estimation apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart of the failure analysis by the failure location estimation apparatus which concerns on embodiment of this invention. It is a flowchart of the conventional failure analysis. It is an equivalent circuit of 2-input NAND (output gate 8W). It is a block diagram which shows the structure of the failure location estimation apparatus which concerns on the 7th Embodiment of this invention.

Explanation of symbols

1 Input device 2 Data processing device 3 Storage device 4 Output device 11 Test pattern DB
12 Netlist DB
13 Fail log DB
14 Layout information DB
15 IDDQ measurement value DB
21, 261, 271 Failure candidate narrowing down part 22, 223 XOR operation part 23, 302, 312, 322 IDDQ quantization part 24, 42, 272, 303, 313, 323 Comparison part 25, 26, 27 Failure candidate specifying part 30 IDDQ difference calculation unit 31 Circuit information storage unit 32 Failure candidate storage unit 33 IDDQ measurement value storage unit 34 Quantized IDDQ storage unit 41 Normal IDDQ test pattern extraction unit 221 Short partner estimation unit 222, 321 Expected value calculation unit 231 IDDQ measurement value sort Unit 232 IDDQ measurement value grouping unit 233 IDDQ quantization processing unit 262 drive capability comparison unit 263, 273, 304, 314, 324 output unit 301 difference calculation processing unit 311 test pattern extraction unit N10 failure candidate wirings N21, N30, N31 proximity wiring

Claims (3)

A failure location estimation device for a semiconductor integrated circuit in which failure candidate wiring pairs that may cause a short failure in advance are narrowed down by failure diagnosis software or a failure analysis device,
For each of the plurality of test patterns , the expected value of the signal in the first wiring and the expected value of the signal in the second wiring included in the failure candidate wiring pair are input, and the exclusive OR (XOR) of both expected values An XOR operation unit configured to obtain and output
Enter the IDDQ measured value of the semiconductor integrated circuit for each of the plurality of test patterns, to 1 when IDDQ measurement value entered is greater than a predetermined threshold value, in other cases it is quantized to zero output An IDDQ quantizer configured to:
A comparison configured to compare the XOR and the quantized IDDQ for each of the plurality of test patterns , find the number of matches, and output a failure candidate wiring pair having a higher number of times as having a higher possibility of failure. And a failure location estimation apparatus.   The IDDQ quantization unit subtracts the IDDQ measured in the non-defective product from the input IDDQ measurement value for the test pattern. 2. The failure location estimation apparatus according to claim 1, wherein the failure location estimation apparatus is configured to quantize to 0 and output. The IDDQ quantizing unit is configured to output quantized IDDQ except for those having a non-defective IDDQ for the test pattern larger than a predetermined value among the input IDDQ measurement values,
The comparison unit is configured to compare the XOR and the quantized IDDQ and obtain the number of times of coincidence, except that the non-defective IDDQ among the test patterns is larger than the predetermined value. The failure location estimation apparatus according to claim 1.

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