JP2655105B2 - Fault location estimation method for sequential circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for estimating a fault location in a sequential circuit, and more particularly to a method for estimating a fault location in a sequential circuit formed by a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As a conventional method for estimating a fault location of a sequential circuit of this type, for example, an electronic beam tester is used.
A method of narrowing down a failure part by observing a signal state in each part of the semiconductor integrated circuit and comparing and comparing the observation result with a simulation result in the semiconductor integrated circuit, or creating a failure dictionary of the semiconductor integrated circuit in advance A method of narrowing down a failure location by comparing an actual failure result with a failure dictionary is used.

A method of narrowing down a faulty part of a sequential circuit using the above-described electron beam test is described in, for example, "M. Kato, T. Su
jide: Novel VLSI Failure Analysis Iechnique Using
Ele-ctron Beam Tester, 1992 First Asian Test Symp
osium '', compare the signal of the good product with the signal of the bad product, or compare the potential image of the good product with the potential image of the bad product, or compare the expected value obtained from the logic simulation. By performing the comparison, narrowing down is performed while sequentially following the failure signal line from the output pin that has actually failed to the inside of the semiconductor integrated circuit. In the case of using the expected value of the logic simulation, a signal line at the boundary described hierarchically is extracted from the circuit connection information, and an observation value of the signal line by an electron beam tester and obtained by a logic simulation. By examining whether or not the expected value matches, it is determined whether the failure location is inside or outside the block, and narrowing down is performed.

[0004] As another method, the above-mentioned method for estimating a fault using a fault dictionary performs an operation simulation on the assumption that a fault exists inside a semiconductor integrated circuit by using an actual test vector. A data file containing information on the assumed failure position and the output pin that failed at that time is created in advance as a failure dictionary, and the failure dictionary is indexed based on the failure state of the actually failed output pin, and the failure location is determined. Is a method of estimating a failure point by obtaining the candidate points of (1) and (2) and assigning a priority to the plurality of obtained candidate points.

[0005]

In the above-described conventional method for estimating a fault location of a sequential circuit, in the case of a fault diagnosis method using an electron beam tester, a fault signal line is observed and tracked as a procedure to determine a fault location. Although it is an effective means for estimating the failure location for narrowing down, the number of observation points by the electron beam tester becomes very large as the scale of semiconductor integrated circuits, multilayer wiring, and flattening advance. However, there is a disadvantage that it takes a lot of time to observe the state of the signal line.

In addition to the above disadvantages, it is becoming very difficult to observe the potential of the lower wiring due to the multilayer wiring.
In addition, there is a limit in the observation by the upper wiring part of the same wiring, and there is a disadvantage that the observation itself may not be possible depending on the layout of the semiconductor integrated circuit.

[0007] On the other hand, in the case of the above-mentioned fault location estimating method using the fault dictionary, it is necessary to create a fault dictionary in advance by a fault simulation assuming a fault inside the semiconductor integrated circuit. There is a disadvantage that the time used for the simulation is explosively increased with the increase in the scale of.

[0008] In addition, the fault model handled in the fault simulation is generally a fault model corresponding to a single stuck-at fault, but in the case of multiple faults such as a bridge fault, the fault model is not actually used. However, there is a drawback that the failure cannot be applied as a failure diagnosis method. Moreover, the fault location estimation method using the fault dictionary has a drawback that it is impossible to extend a model to multiple faults other than the single stuck-at fault model as a corresponding fault model.

[0009]

According to the present invention, there is provided a method for estimating a fault location in a sequential circuit, comprising: information of all expected values for all vectors of all latches, pass / fail information of a tester, and information of all circuits in a semiconductor integrated circuit. In the method for estimating a fault in a sequential circuit in which a fault is estimated by dividing the semiconductor integrated circuit into a latch and a combinational circuit using the connection information, the semiconductor integrated circuit is connected to a semiconductor chip from an actual fail output pin or a latch input line estimated to be failed. A combination circuit is extracted in the input direction until reaching the input pin or the latch output of the integrated circuit, and further from the extracted input of the combination circuit,
A first processing procedure for extracting a combinational circuit in an output direction until reaching an output pin or a latch input of the semiconductor integrated circuit; and an output of a latch connected to an output unit of the combinational circuit, A second processing procedure for creating a data flow by checking whether any other latch is affected or not, and a single-fault propagation confirmation at the input boundary of the combinational circuit, Confirmation of branching of the same signal line and activation of branch signal in combination circuit,
And a third processing procedure for estimating and confirming by simulation for selecting a signal line combination capable of simultaneous fault propagation by confirming the clock enable of the input boundary latch, and a subsequent stage from the combination circuit to the actual output of the semiconductor integrated circuit. If the extraction of the circuit is not confirmed, the fourth processing procedure of extracting the subsequent circuit, the failure propagation simulation using the failure estimation result at the input boundary of the combinational circuit, and the actual fail output A fifth processing procedure for determining whether or not they match, and, if it is determined in the fifth processing procedure that they match, create a latch state estimated value table and obtain the obtained latch state. The presence or absence of a stuck-at fault is determined based on the simulation result of each signal line in the combinational circuit using the estimated value table of And a sixth procedure for estimating a fault location in the combination as a procedure for obtaining a fault propagation estimated value at an input boundary of the combinational circuit at least for each fail vector. It is characterized by doing.

In the sixth processing procedure, a difference between a simulation result performed using the estimated value table of the latch state and the pass / fail information of the tester and an expected value in a normal operation is provided. A seventh processing procedure for detecting a fault propagation path in the combinational circuit, and detecting an overlapping portion of the fault propagation path obtained by the detection in the seventh processing procedure, And at least an eighth processing procedure for prioritizing, and a failure estimation list may be finally created.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a processing procedure for obtaining an estimated value of a fault propagation at an input boundary of a combination circuit for each fail vector according to an embodiment of the present invention, and FIG. 2 is included in the flowchart. 2 is a flowchart showing a processing procedure (a processing procedure 110 in FIG. 1) when estimating a fault location in a combination circuit to be performed. Also,
FIG. 3 shows an example of confirming the same signal line branch in the preceding combination circuit when multiple failure propagation is assumed in the input part failure propagation estimation procedure of the combination circuit in the course of the processing procedure in this embodiment. FIG.
FIG. 7 is a diagram illustrating an example of extraction of an overlapping area by comparing fault propagation paths of all fail vectors in fault location estimation in the combination circuit.

In FIG. 1, when an estimated value of a fault propagation at an input boundary of a combinational circuit is obtained for each fail vector, actual tester path / failure information S1, expected values S2 of all latches, and connection information of all circuits are obtained. The processing procedure is executed using S3. First, in the processing procedure 101,
From a predetermined file, tester pass / fail information S1,
The expected values S2 of all the latches and the connection information S3 of all the circuits are read, and the test path / fail pin information including these information is extracted. Next, in the processing procedure 102, using the tester / fail information S1 and the connection information S3 of all circuits, a search for fail pins is performed in order from the youngest vector, and the circuit is tracked in the input direction from the obtained fail pin, Circuit extraction is performed until the input pin or latch output of the semiconductor integrated circuit is reached, and then the circuit is traced in the output direction from the input pin or latch output of the obtained combinational circuit, and the output pin of the semiconductor integrated circuit is traced. Alternatively, circuit extraction until reaching the latch input is performed. This results in one combinational circuit,
When the output pins of the extracted combinational circuit include other fail pins than the first fail pin, the circuit in the reverse direction and the forward direction is also applied to the new fail pin. By performing the above operation repeatedly until extraction is performed and there is no new fail pin,
The combination circuit connection information S4 is obtained.

Next, following the processing procedure 102, the processing procedure 103 and the processing procedure 104 are executed. In the processing procedure 103, connection information S3 of all circuits
, It is checked whether the latch output of the output unit of the combination circuit affects any other latch, and a data flow corresponding to the latch is created. Next, in the processing procedure 105, based on the data flow created in the processing procedure 103, it is checked whether or not the subsequent circuit has already been extracted. Then, circuit extraction is performed, and the process proceeds to the processing procedure 106. On the other hand, following the processing procedure 102, the processing procedure 10
4, a simulation of an operation assuming a fault propagation to the input unit of the combinational circuit is performed with reference to all expected values S2 of all the latches, and the result is an actual fail result or a forward set. It is determined whether or not the result matches the fault propagation estimation result of the matching circuit, and only the fault propagation estimation value in the case of matching is selected and output. In this case, when a fault is inserted at the input section of the combinational circuit, single fault propagation and multiple fault propagation at each input pin of the combinational circuit are assumed.

In the case of the above-mentioned multiple fault propagation, as shown in FIG.
From the input signal lines of the latch group 32 in the reverse direction along a fault propagation path indicated by a broken line as an example, and extraction of the end points 301 and 302 of the circuits connected to these wirings is performed. Then, the circuit connection status is checked, and a set of fault propagation signal lines whose branch from the same signal line is a latch input is extracted. Next, a normal logic simulation is performed using all the expected values S2 of all the latches and the extracted combination circuit 31 of the preceding stage, and the signals which are not activated from the extracted set of fault propagation signal lines are output. The line is deleted. Then, the clock signal lines of the latch group 32 are checked, and signal lines for which the clock is not enabled are also deleted.

Next, in the processing procedure 106, using the fault propagation value obtained in the processing procedure 104 and referring to the connection information of the subsequent circuit obtained in the processing procedure 105, the operation is performed in the forward direction. Simulation is performed. In the processing procedure 107, the processing procedure 10
6 and the actual tester path /
The fail information is compared with the fail information to determine whether they match, and if they match, in the processing procedure 108, the latch estimated value information S5 is output based on all the expected values S2 of all the latches. The process is stored in a predetermined file, and the process proceeds to the next processing procedure 109. Further, in the processing procedure 107, when the simulation result of the processing procedure 106 does not match the actual tester pass / fail information, the estimated value based on the simulation result of the processing procedure 106 is deleted as an error, and the processing procedure is deleted. At 109, the next fail vector estimation process is performed. In the processing procedure 109, if the estimation processing has not been completed for all the vectors, the processing returns to the processing procedure 104, and the processing procedures subsequent to the processing procedure 104 are repeatedly executed. If it is determined that the input fault propagation estimated value of the circuit has been obtained, the process of estimating the fault in the combinational circuit is performed in the processing procedure 110. Regarding the processing procedure for estimating a fault in the combinational circuit in the processing procedure 110,
FIG. 2 shows a detailed flowchart thereof. After the process of estimating the failure in the combinational circuit in the processing procedure 110 is completed, the process of estimating the failure in the combinational circuit is performed in the processing procedure 111. It is determined whether or not the processing has been completed for all the combinational circuits. If the processing has not been completed for all of the combinational circuits, the procedure returns to the processing procedure 102 again, and the processing procedure after the processing procedure 102 is repeated. If the failure estimation processing has been completed for all the combinational circuits, the processing for obtaining the estimated failure propagation value at the input boundary of the combinational circuit for each fail vector is completed.

Next, the processing contents of the processing procedure 110 included in the above-mentioned flowchart will be described in detail. First, in the processing procedure 201, the estimated value information S5 of the latch of the combination circuit input unit obtained in the processing procedure 108, the tester pass / failure information S1, and the combination circuit connection information S obtained in the processing procedure 102
4 and the total expected value S2 of all the latches, the latch expected value S6 of the combinational circuit input section is extracted. In the processing procedure 202, the latch expected value S6 of the combinational circuit input section is replaced with the latch fault propagation estimated value S7 and output. In the processing procedure 203, a logic simulation is performed using the fault propagation estimated value S7 of the latch of the combinational circuit input unit, and in the processing procedure 204, the combinational circuit connection information S4 and the combinational circuit input unit A normal logic simulation is performed using the expected latch value S6. Next, processing procedure 20
5, the processing procedure 203 and the processing procedure 20
By using the result of the logic simulation in 4, the state of each signal line is compared, and a fault propagation path expressed as the difference is extracted. Next, in the processing procedure 206,
The fault propagation paths of all the fail vectors obtained in the processing procedure 205 are compared, and as an example, an overlapping circuit portion as shown in FIG. 4 is extracted. In FIG. 4, fault signal lines 401, 4
For 02 and 403, the fault propagation paths from the input signal line indicated by the broken line to the output of the combinational circuit are shown, and the overlapping portions existing corresponding to these fault propagation paths are shown. ing. An area 404 is an overlapping portion in the fault propagation assumption of the fault signal lines 402 and 403, and an area 406 is the fault signal lines 401 and 402
The overlapping portion in the fault propagation assumption, the region 404 is the overlapping portion in all the fault propagation assumptions of the fault signal lines 401, 402, and 403.

In the processing procedure 207, the priorities of the detected faulty parts detected are prioritized based on the duplication frequency result obtained in the processing procedure 206. Then, in the processing procedure 208, the state of the area that has been prioritized in the processing procedure 208 is obtained from the simulation result, and it is checked whether or not all test vectors have been reduced to “0” or “1”. Is performed, and the process proceeds to the processing procedure 111 (see FIG. 1).

[0019]

As described above, according to the present invention, as a failure estimating procedure in a semiconductor integrated circuit, a combination circuit is extracted from the output side of the semiconductor integrated circuit, and the combination circuit is extracted for all failures. In order to estimate the fault propagation value at the input boundary of, the method is compared with the conventional method, in which a fault is assumed for all signal lines of all circuits and a fault simulation is performed for all vectors. Then, the effect that the set number of fault points becomes the combination of the input part signal lines of the combination circuit that assumes a fault and the number is suppressed to a small value is obtained, and individual fault simulations are extracted. By limiting the combination circuit to that described above, the circuit scale is significantly reduced as compared with the failure simulation corresponding to the entire circuit, and the required calculation amount is reduced. There is a result.

Further, regarding the extraction of the fault propagation path in the combinational circuit, the fault propagation path is determined only by comparing and comparing the failure simulation result of the combinational circuit input section for estimating the failure and the simulation result in the case of normal operation. Since extraction can be performed, the amount of calculation required for the extraction processing is suppressed to a small amount, and a fault propagation circuit can be extracted even for a reconvergence circuit in a combinational circuit.

Further, a fault propagation value at the input boundary of the combinational circuit is estimated for all the fail vectors,
In order to trace the fault propagation value estimation path and further narrow down to the combination circuit in the preceding stage, even in the case of occurrence of multiple faults such as a bridge fault, independent fault propagation and fault propagation that mutually influence each other are performed. Since both can be assumed, there is an effect that an error hardly occurs in the fault propagation value estimation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flowchart of a processing procedure in an embodiment of the present invention.

FIG. 2 is a diagram showing a flowchart of a processing procedure for estimating a fault location in a combination circuit in the embodiment.

FIG. 3 is a diagram showing confirmation of branching of the same signal line in a combination circuit in a preceding stage when multiple fault propagation is assumed in the embodiment.

FIG. 4 is a diagram showing extraction of an overlap region by comparing fault propagation paths of all fail vectors when estimating a fault location in a combinational circuit in the embodiment.

[Explanation of symbols]

31, 33, 36, 38 Combination circuit 32, 34, 35, 37 Latch group 101 Test pass / fail pin information extraction processing procedure 102 Combination circuit connection information extraction processing procedure 103 Inter-latch data flow creation processing procedure 104 Combination circuit input Part fault propagation value estimation processing procedure 105 Post-stage circuit connection information extraction processing procedure 106 Fault propagation simulation processing procedure 107 Output match determination processing procedure 108 Latch estimation value table creation processing procedure 109 All vector estimation completion determination processing procedure 110 Fault estimation in combination circuit Processing Procedure 111 Estimation Completion Judgment Processing Procedure 201 Latch Expected Value Extraction Processing Procedure for Combinational Circuit Input Unit 202 Latch Fault Propagation Estimated Value Replacement Processing Procedure 203, 204 Logic Simulation Processing Procedure 205 Propagation Path Extraction Processing Procedure Based on Difference of Each Signal Line 20 6 Propagation path comparison processing procedure for all fail vectors 207 Estimated fault location prioritization processing procedure 208 Extracted fault location status check processing procedure 301, 302 Endpoints 401 to 403 Fault propagation estimated signal lines 404 to 406

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit, comprising: a circuit for combining a latch with a latch by using all expected value information for all vectors of all latches, pass / fail information of a tester, and connection information of all circuits in the semiconductor integrated circuit; In the fault location estimating method of the sequential circuit for estimating the fault by dividing into two, the input direction from the actual fail output pin or the latch input line which is estimated to fail to the input pin or the latch output of the semiconductor integrated circuit is reached. Extracting a combinational circuit toward the output direction from the input of the extracted combinational circuit to an output pin or a latch input of the semiconductor integrated circuit; And whether the output of the latch connected to the output of the combinational circuit affects any of the other latches. A second processing procedure for creating a data flow by checking the fault propagation value at the input boundary of the combinational circuit, confirming a single failure propagation, confirming the same signal line branch in the preceding combinational circuit, and activating the branch signal. A third processing procedure for estimating and confirming by a simulation for selecting a signal line combination capable of simultaneous fault propagation by confirming the conversion and confirming the clock enable of the input boundary latch; and outputting the actual output of the semiconductor integrated circuit from the combination circuit. A fourth processing procedure for extracting the subsequent circuit when the extraction of the latter circuit is not confirmed until the failure propagation simulation using the failure estimation result at the input boundary of the combinational circuit; A fifth processing procedure for determining whether or not the output matches, and a determination is made in the fifth processing procedure that they match. In this case, a latch state estimation value table is created, and the presence / absence of a stuck-at fault is determined based on a simulation result of each signal line in the combination circuit using the obtained latch state estimation value table. A sixth processing procedure for estimating the fault location of the fault vector, and a processing procedure for obtaining a fault propagation estimation value at the input boundary of the combinational circuit at least for each fail vector, and finally generate a fault estimation list. A fault estimating method for a sequential circuit, comprising: 2. The method according to claim 1, further comprising the step of: estimating the value of the latch state and the pass / fail of the tester.
A seventh processing procedure for detecting a fault propagation path in the combinational circuit based on a difference between a simulation result performed using the fail information and an expected value in a normal operation; An eighth processing procedure of detecting an overlapped portion of the obtained fault propagation path and assigning a priority to the estimated fault location, and finally creating a fault estimation list 2. The method for estimating a fault in a sequential circuit according to claim 1, wherein: