JP2701753B2 - LSI failure location estimation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for estimating a fault location of an LSI, and more particularly to a technique for estimating a fault location of a logic circuit.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional fault location estimating method includes a procedure 19 for preparing a fault dictionary in advance using a fault simulator, a procedure 20 for actually performing an LSI test and obtaining fail information, and The procedure includes a procedure 21 for searching the failure dictionary from the fail information of the test result and a procedure 22 for estimating a failure location.

The fault simulator performs a logic simulation assuming a fault inside the LSI, compares the result of the logic simulation with an expected value, and associates the assumed fault location with a test vector that has detected the fault. Create a dictionary. From the fail information obtained by actually testing the LSI, the fault dictionary is searched to find a hypothetical fault location, and a plurality of fail information and path information are used to prioritize a plurality of hypothetical faults obtained. This is to estimate the location.

As another method, there is a method in which the above procedure is performed hierarchically and an internal observation procedure is performed using an electron beam tester. The fault location is estimated in order from the upper hierarchy, the internal observation is performed using the electron beam tester at the boundary of the hierarchy, and the failure location is narrowed down to the lower hierarchy.

[0005]

In these conventional fault location estimation methods, it is necessary to create a fault dictionary in advance. However, since the creation of a fault dictionary requires a great deal of fault simulation time, the scale of an LSI becomes larger. The more time is required, the longer the calculation time becomes, and the size of the failure dictionary file becomes very large.

Further, since a single stuck-at fault is generally used as a fault model used in the fault simulation, the fault model may not coincide with an actual fault in a multiple fault such as a bridge fault. The problem is that it is not practical in terms of time.

Further, in the case of using both the hierarchical failure simulation and the electron beam tester, this is an effective means for narrowing down while sequentially observing the estimated location. There is a problem that observation of is impossible.

[0008]

According to the present invention, there is provided a fault location estimating method comprising the steps of: extracting a flip-flop from a netlist; calculating all expected values of all flip-flops extracted by logic simulation of an entire LSI; A procedure of actually performing an LSI test to obtain pass / fail pin and fail vector information for all test vectors, and using a netlist of the entire LSI, a backtrack from the failpin and a forward track from a branch point of the net by a forward track. Extracting a combinational circuit having a plurality of output pins or flip-flop outputs as inputs and outputting a plurality of output pins or flip-flop inputs; and Find all expected values of nodes by logic simulation Compares the sequence, the expected value of each node of the combinational circuit backtrack from the fail pin,
A fault location is estimated by a procedure of estimating a net on which a failure has propagated and determining a node value based on an output result of forward tracking from a branch point of the net.

[0009]

Therefore, it is not necessary to create a failure dictionary by failure simulation, and it is possible to greatly reduce the processing time.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 to 3 are flowcharts showing an estimation procedure according to the present invention.

First, an embodiment will be described with reference to FIG. In the procedure 1, an actual LSI test is performed by a tester, and all pass / fail information is obtained.
The pass / fail information is information including determination / non-determination of each pin, and simultaneously stores a fail pin number and a fail vector number. Step 2 is to backtrack from the netlist with the fail pin obtained in step 1 as the starting point,
If the net branches, the forward track,
By performing backtracking, a combinational circuit having a plurality of inputs and outputs whose input is an input pin or an output of a flip-flop and whose output is an output pin or an input of a flip-flop is extracted.

On the other hand, in step 3, all flip-flops included in the LSI netlist are extracted, and in step 4, logic simulation is executed to obtain all expected values of all the flip-flops for each vector.

In step 5, the combinational circuit obtained in step 2 which is considered to be partially and fail-propagating is used, by using the expected values of all the flip-flops obtained in step 4, A simulation is performed to obtain all expected values for each vector for all nodes of the combinational circuit.

In step 6, the failure estimation in each of the nodes is narrowed down by sequentially repeating the fail estimation of each node based on the expected value of each node of the combinational circuit obtained in step 5 and the pass / failure information in step 1.

FIG. 3 shows a detailed procedure of the procedure 6, which will be described with reference to FIG.

FIG. 4 shows a part of the combinational circuit, where X, Y and Z are logic blocks, and a to g are nets. Assuming that the net b has failed, the backtrack continuation determination in the procedure 16 is performed in the procedure 14 because there is no branch of the net b in the procedure 14. In step 16, backtracking is continued unless the net reaches the input pin or the output of the flip-flop or the estimated value of the net is not normal in step 15. Therefore, backtracking is performed on the net b, and the block b is reached. Step 17
Compares the expected value of nets d, e, and b with the output path / fail of net b using the truth table of block Y,
It is determined whether or not the block Y has failed. Step 18
Then, the fail propagation input of the block Y is estimated using the truth table of the block Y, the expected values of the nets d, e, and b, and the fail estimated value of the net b. Then, it is assumed that the net of d has been failed-estimated. Then, the procedure returns to the procedure 14. However, since the net d has a branch point, the procedure proceeds to the procedure 15. Step 15
Forward-tracks the net d sequentially as a block X and a net a, and repeats the forward track until reaching the output pin or flip-flop. Then, by comparing the pass / fail information of the output pin or the pass / fail estimated value of the flip-flop with the result of the start point of the back track of the net b, the failure before the branch point of the net d or the block behind the branch point is determined. It is determined whether the Y input side is faulty. In step 16, if the failure after the branch point occurs, that is, if the output of the block Z becomes normal, the backtracking ends. If the failure occurs before the branch point, the backtracking is performed.
In step 17, pass / fail judgment of the block Z is performed.

After estimating the failure of the combinational circuit in this way, it is determined in step 7 in FIG. 1 whether or not the narrowing is completed. If the backtrack reaches the flip-flop, the narrowing is completed. Therefore, in step 8, input failure estimation of the combinational circuit, that is, failure estimation of the flip-flop is performed. Then, returning to the procedure 2, the combinational circuit is extracted again by the backtrack and the forward track at the branch point, starting from the flip-flop where the fail has propagated, and estimation is performed. If the backtrack is completed in step 6, it is determined in step 7 that the narrowing has been completed, and weighting is performed in step 9 on all the estimated failure locations obtained so far. In step 10, a list is output in the order of the priority of failure estimation based on the weight.

In FIG. 2 showing another embodiment, in procedure 1, as in FIG. 1, an actual LSI test is performed by a tester to acquire all the pass / fail information. Step 11 is Step 1
Backtracking is performed from the net list with the fail pin obtained in the above as the starting point, and when the net is branched, the forward track and the backtrack are performed.
Input pin or output of flip-flop as input,
In addition, a combinational circuit having a plurality of inputs and outputs such that an output of an output pin or an input of a flip-flop is used as an output and a flip-flop serving as an input / output of the combinational circuit are extracted. Step 1
2 executes a logic simulation to obtain all expected values of the flip-flops extracted in step 11 for each vector. Step 13 is to apply the partial circuit obtained in step 11 to the combinational circuit which is considered to have propagated the failure.
Using the expected values of the flip-flops obtained in step 2, the logic simulation of the combinational circuit is executed, and all the expected values of each vector for all the nodes of the combinational circuit are obtained.

In step 6 similar to FIG. 1, the fail estimation of each node is sequentially repeated based on the expected value of each node of the combinational circuit obtained in step 13 and the pass / failure information of step 1 in the combinational circuit. Narrow down failures.

In step 7, when the backtrack reaches the flip-flop as a result of the narrowing down in step 6, it is determined that the narrowing has not been completed, and the input failure estimation of the combinational circuit in step 8, ie, the flip-flop Is performed. Then, returning to the procedure 11, the backtracking and the forwardtracking of the branch point are performed again starting from the flip-flop to which the fail has propagated, and the combinational circuits and the flip-flops corresponding to their inputs and outputs are extracted and determined. If the backtrack is completed in the procedure 13, the narrowing-down is determined to be completed in the procedure 7, and weighting is performed in the procedure 9 on all the estimated fault locations obtained so far. In step 10, a list is output in the order of priority of failure estimation based on the weight.

[0021]

As described above, according to the present invention, a logic simulation of all expected values of a flip-flop, a partial combination circuit extraction by a back track and a forward track, and a combination circuit using an expected value of a flip-flop are performed. Since this is a method of backtracking and fault estimation using the logic simulation and its result, there is no need to create a fault dictionary by fault simulation, and the processing time can be greatly reduced. At the same time as this effect, there is an advantage that the trouble of preparing and storing a large-capacity failure dictionary in advance can be omitted. These effects become larger as the scale of the LSI increases and the number of nodes increases. In addition, there is an advantage that a fault location can be estimated even if the fault is not a single stuck-at fault.

Compared to the case where the observation using the EB tester is also used, in the case of the multilayer wiring, it is impossible to observe immediately with the EB tester. Can be

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a processing procedure according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure according to another embodiment of the present invention.

FIG. 3 is a flowchart illustrating a processing procedure for performing estimation by backtracking from each expected value of the combinational circuit;

FIG. 4 is a block diagram illustrating a part of a combinational circuit;

FIG. 5 is a flowchart illustrating a processing procedure according to the related art.

[Explanation of symbols]

 1-22 Processing procedure X, Y, Z Blocks such as logic gates ag Node names of nets

Claims (3)

(57) [Claims] 1. A procedure for performing an LSI test with a tester to obtain all pass / fail information and determination / non-determination information of each pin at the time of testing, and from a netlist starting from a fail pin or a fail estimation flip-flop. performs backtrack, also forward track if the net is branched by performing a backtracking, receives the output of the input pins or flip-flop, and a plurality of inputs and outputs the input of the output pins or flip-flop Extracting a combinational circuit having an output from the netlist, extracting all the flip-flops included in the netlist, performing a logic simulation to obtain all expected values for each vector of the flip-flops, Combined with the combination circuit and all expected values of the flip-flop A logic simulation procedure for obtaining all expected values of all nodes of the combinational circuit, a procedure of performing backtracking by using all expected values of all nodes of the combinational circuit and the obtained path / failure information, and completion of narrowing down. From the result obtained by the procedure for determining the end of the backtrack by and the failure estimation procedure of the combinational circuit,
A step of estimating the type comprising a fail of the flip-flop output of the combinational circuit, backtracking the end, the all
A fault location estimation method for an LSI, comprising: estimating a failure location by a procedure for weighting a failure estimation location obtained by the above procedure and a procedure for outputting a list in priority order based on the weighting. 2. Instead of using all flip-flop extraction procedures and logic simulation procedures of all expected values of all flip-flops, extraction of combinational circuits by backtrack and forward track and extraction of flip-flops as inputs and outputs of the combinational circuits are performed. 2. A logic simulation procedure for obtaining all expected values of each vector of the extracted flip-flops, wherein a logic simulation of the extracted combinational circuit and a fault location estimation can be performed. A method for estimating a failure location of the described LSI. 3. A procedure for performing a backtrack using all expected values of all nodes of a combinational circuit and acquired path / failure information and estimating a fault, a procedure for determining whether or not there is a branch of a net, and a procedure for when there is a branch. Sequentially performing forward track, detecting an output pin or flip-flop, comparing the pass / fail estimated value of the output pin with the pass / fail information or estimated value of the starting point of the back track,
A procedure for determining whether the fault is before or after the branch point, a procedure for performing a backtrack continuation determination by determining whether or not the failure estimation result before and after the branch point is an input of a combinational circuit; Truth tables and function descriptions,
Estimation of block failure using the net failure estimation value and expected block input / output value, block truth table and function description, and net failure estimation block input expected value 2. A fault location estimation method for an LSI according to claim 1, wherein the fault estimation of the combinational circuit is performed by using the following procedure.