JPH0894714A - Method for estimating failed part of lsi - Google Patents

Abstract

PURPOSE: To provide a method for estimating the failed part of a large-scale and multilayer-wired LSI with a short processing time without limiting to a single degeneracy failure by logic simulation and failure estimation processing. CONSTITUTION: Back track and forward track are performed from pass/fail information obtained by testing an LSI and a fail pin to extract a combination circuit with a plurality of I/O pins. A flip-flop obtains the total expectation value for each test vector by logic simulation. The expectation value is used and the total expectation value of each node of the combination circuit is obtained by logic simulation. The conformity/nonconformity of each net and block and fail value estimation are performed by the actual pass/fail result and a failure estimation part is outputted. Finally, the failure estimation part is weighted and the failure estimation part is outputted in the order of priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI failure location estimating method, and more particularly to a method for estimating a failure location of a logic circuit.

[0002]

2. Description of the Related Art A conventional failure location estimating method is, as shown in FIG. 5, a procedure 19 for creating a failure dictionary in advance using a failure simulator, and a procedure 20 for actually testing an LSI to obtain fail information. It is composed of a procedure 21 of searching the failure dictionary from the fail information of the test result and a procedure 22 of estimating the failure location.

The fault simulator performs a logic simulation assuming a fault inside the LSI, collates the result of the logic simulation with an expected value, and associates the assumed fault location with the test vector detecting the fault. Create a dictionary. Based on the fail information as a result of actually testing the LSI, the failure dictionary is searched to find a supposed failure location, and a plurality of failure information and path information are used to prioritize a plurality of obtained failure failures, The location is estimated.

Another method is to carry out the above procedure hierarchically and have an internal observation procedure with an electron beam tester. The failure point is estimated in order from the upper layer by the above procedure, the internal observation is performed at the boundary of the layer using the electron beam tester, and the failure point is narrowed down to the lower layer.

[0005]

In these conventional fault location estimating methods, it is necessary to create a fault dictionary in advance. However, since the fault dictionary requires a large amount of fault simulation time, the scale of the LSI may be increased. There is a problem in that the calculation time becomes enormous as it is extended, and the file of the failure dictionary becomes very large.

Further, since the fault model used in the fault simulation is generally a single stuck-at fault, there are cases where multiple faults such as a bridge fault do not match the actual situation. Therefore, when the fault simulation model is extended to multiple faults, the fault simulation process is performed. The problem is that it is not practical in terms of time.

Further, in the case of using both the hierarchical failure simulation and the electron beam tester, it is an effective means for narrowing down while sequentially observing the estimated points, but if the LSI becomes large in scale and becomes a multi-layer wiring, the potential of the lower layer will be increased. There is a problem that it becomes impossible to observe.

[0008]

A fault location estimating method according to the present invention comprises a procedure for extracting flip-flops from a netlist, means for calculating all expected values of all flip-flops extracted by logic simulation of the entire LSI, Using the procedure to actually test the LSI and obtain pass / fail pins and fail vector information for all test vectors, and the back track from the fail pin and the forward track from the branch point of the net using the net list of the entire LSI. A procedure for extracting a combinational circuit having a plurality of output pins or flip-flop outputs as inputs and a plurality of output pins or flip-flop inputs as an output, and a total of the extracted combinational circuits using all expected values of the flip-flops. Find all expected values of nodes by logic simulation Compares the sequence, the expected value of each node of the combinational circuit backtrack from the fail pin,
Estimate the net in which the fail is propagated, and estimate the fault location by the procedure of determining the value of the node from the result of the output forward-tracked from the branch point of the net.

[0009]

Therefore, it is not necessary to create a fault dictionary by fault simulation, and the processing time can be greatly reduced.

[0010]

The present invention will be described below with reference to the drawings. 1 to 3 are flowcharts showing the estimation procedure of the present invention.

First, an embodiment will be described with reference to FIG. In the procedure 1, an actual LSI test is performed by a tester and all pass / fail information is acquired.
The pass / fail information is information including judgment / non-judgment of each pin, and stores the fail pin number and the fail vector number at the same time. Procedure 2 is to backtrack from the netlist starting from the fail pin obtained in Procedure 1,
If the net is branched, it is a forward track,
By performing backtracking, a combinational circuit having a plurality of inputs and outputs, the input of which is the output of the input pin or the flip-flop and the output of which is the input of the output pin or the flip-flop, is extracted.

On the other hand, in procedure 3, all flip-flops included in the LSI netlist are extracted, and in procedure 4, logic simulation is performed in order to obtain all expected values for each vector of all flip-flops.

The procedure 5 uses the expected values of all the flip-flops obtained in the procedure 4 for the combinational circuit obtained in the procedure 2 and which seems to propagate the fail, and the logic of the combination circuit is obtained. A simulation is executed to obtain all expected values for each vector for all nodes of the combinational circuit.

In step 6, the failure estimation in each combination circuit is performed by sequentially repeating the fail estimation of each node based on the expected value of each node of the combination circuit obtained in step 5 and the pass / failure information of step 1.

FIG. 3 shows a detailed procedure of procedure 6, which will be described with reference to FIG.

FIG. 4 shows a part of the combinational circuit, where X, Y and Z are logic blocks and a to g are nets. Assuming now that the net of b has failed, the backtrack continuation judgment of step 16 is performed in step 14 because there is no branch of net b. Backtracking is continued in step 16 unless the net reaches the input pin or the output of the flip-flop or the estimated value of the net becomes normal in step 15. Therefore, the net b is backtracked and the block Y is reached. Step 17
Compares the expected values of nets d, e, and b with the pass / fail of the output destination of net b using the truth table of block Y,
It is determined whether or not the block Y has a failure. Step 18
Then, the fail propagation input of the block Y is estimated using the truth table of the block Y, the expected values of the nets d, e, and b and the fail estimated value of the net b. Therefore, it is assumed that the net of d has been fail-estimated. Then, the procedure returns to step 14, but since the net d has a branch point, the procedure moves to step 15. Step 15
Sequentially forward-tracks the net d such as the block X and the net a, and repeats the forward-tracking until it reaches the output pin or the flip-flop. Then, by comparing the pass / failure information of the output pin or the pass / failure estimation value of the flip-flop with the result of the start point of the backtrack of the net b, a failure occurs before the branch point of the net d or a block after the branch point of the net d. It is determined whether the Y input side is out of order. In step 16, backtracking ends if there is a failure after the branch point, that is, if the output of block Z is normal, and backtracking occurs if there is a failure before the branch point,
In step 17, the pass / fail judgment of the block Z is performed.

After the failure of the combinational circuit is estimated in this way, it is judged in step 7 of FIG. 1 whether or not the narrowing is completed. If the backtrack reaches the flip-flop, the narrowing is completed. Since it does not exist, in step 8, input fail estimation of the combinational circuit, that is, flip-flop fail estimation is performed. Then, returning to the procedure 2, the combinational circuit is extracted again by the back track and the forward track of the branch point, starting from the flip-flop where the fail is propagated, and the estimation is performed. If backtracking is completed in step 6, it is determined that the narrowing down has been completed in step 7, and weighting is performed in step 9 for all the failure estimation points obtained up to that point. In step 10, the list is output in order of priority of failure estimation based on the weighting.

In FIG. 2 showing another embodiment, procedure 1 is the same as in FIG. 1, in which an actual LSI test is performed by a tester to acquire all pass / fail information. Procedure 11 is Procedure 1
By performing backtracking from the netlist starting from the fail pin obtained in step 1, and performing forwardtracking and backtracking when the net is branched,
Input pin or output of flip-flop,
Further, a combinational circuit having a plurality of inputs and outputs such that the output pin or the input of the flip-flop is used as an output, and the flip-flops serving as the inputs and outputs thereof are extracted. Step 1
In step 2, a logical simulation is executed in order to find all expected values for each vector of the flip-flops extracted in step 11. Procedure 13 is the same as the procedure 1 for the partial and fail-propagating combinational circuit obtained in Procedure 11.
The expected value of the flip-flop obtained in 2 is used to execute a logic simulation of the combinational circuit to obtain all expected values for each vector for all nodes of the combinational circuit.

In procedure 6 similar to that in FIG. 1, fail estimation of each node is sequentially repeated based on the expected value of each node of the combinational circuit obtained in procedure 13 and the pass / failure information of procedure 1 in the combinational circuit. Narrow down the failure.

In step 7, when the backtrack reaches the flip-flop as a result of the narrowing down in step 6, it is judged that the narrowing down is not completed, and the input fail estimation of the combinational circuit in step 8, that is, the flip-flop is performed. Fail estimation is performed. Then, returning to step 11, backtracking and forward branching of the branch point are performed again starting from the flip-flop through which the fail has propagated, and the combinational circuit and the flip-flops corresponding to their inputs and outputs are extracted and the determination is performed. If backtracking is completed in step 13, it is determined in step 7 that the narrowing is completed, and in step 9, weighting is applied to all the failure estimation points obtained up to that point. In procedure 10, the list is output in order of priority of failure estimation based on the weighting.

[0021]

As described above, according to the present invention, logical simulation of all expected values of flip-flops, partial combinational circuit extraction by backtrack and forward track, and combinational circuits using expected values of flip-flops are performed. Since it is a method of backtracking and fault estimation using the logic simulation and its result, there is no need to create a fault dictionary by fault simulation, and the processing time can be greatly shortened. At the same time as this effect, there is an advantage that the trouble of preparing and storing a large-capacity fault dictionary in advance can be saved. These effects increase as the scale of the LSI increases and the number of nodes increases. There is also an advantage that the failure location can be estimated even when the failure is not a single stuck-at failure.

Compared with the case of using the observation with the EB tester together, in the case of the multi-layer wiring, it is impossible to immediately observe with the EB tester, but there is an advantage that the failure location can be estimated only by the processing. To be

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing procedure of an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure of another embodiment of the present invention.

FIG. 3 is a flowchart showing a processing procedure for performing backtracking estimation from each expected value of a combinational circuit.

FIG. 4 is a block diagram showing a part of a combinational circuit.

FIG. 5 is a flowchart showing a processing procedure of a conventional technique.

[Explanation of symbols]

 1 to 22 Processing procedure X, Y, Z Blocks such as logic gates a to g Net node names

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G06F 11/25

Claims (3)

[Claims] 1. A procedure for performing an LSI test with a tester and acquiring all pass / fail information and judgment / non-judgment information of each pin at the time of testing, and from a net list starting from a fail pin or a fail estimation flip-flop. Backtracking is performed, and if the net is branched, forward tracking and backtracking are performed, so that the output of an input pin or flip-flop is used as an input, and the output of an output pin or flip-flop is used as an output. A procedure for extracting a combinational circuit having inputs and outputs, a procedure for extracting all flip-flops included in the netlist, a logic simulation procedure for obtaining all expected values for each vector of all the flip-flops, According to the extracted combinational circuit and all expected values of the flip-flops Logic simulation procedure for obtaining all expected values of all nodes of the combinational circuit, procedure of backtracking using all expected values of all nodes of the combinational circuit and the obtained pass / failure information, and completion of narrowing down Based on the results of the procedure for determining the end of backtrack by the above and the result of the failure estimation procedure for the combinational circuit, the failure estimation procedure for the flip-flop output that is the input to the combinational circuit, and the above estimation at the end of the backtracking are obtained. A method of estimating a failure location of an LSI, characterized in that a failure location is estimated by a weighting procedure of failure estimation locations and a procedure of outputting a list in order of priority according to the weighting. 2. Instead of using all flip-flop extraction procedure and logic expected procedure of all expected values of all flip-flops, combination circuit extraction by backtrack and forward track and flip-flop extraction procedure which becomes input / output of the combination circuit. And a logic simulation procedure for obtaining all expected values for each vector of the extracted flip-flops, which makes it possible to perform logic simulation of the extracted combinational circuit and fault location estimation. A method for estimating a failure location of the described LSI. 3. In a procedure of backtracking by using all expected values of all nodes of a combinational circuit and acquired pass / failure information to perform failure estimation, a procedure of determining the presence or absence of a branch of a net, and a case of branching , Sequentially performing forward tracking, detecting an output pin or a flip-flop, and comparing the pass / fail estimated value of the output pin with the pass / fail information or estimated value of the starting point of the back track,
A procedure for determining whether the fault is before or after the branch point, a procedure for performing backtrack continuation determination by determining whether the fault estimation result before and after the branch point and the input of the combination circuit, and further backtracking the block. Truth table and function description,
Estimate a block's fail-propagation input using the net fail estimate value, the block input / output expected value, the block's truth table and functional description, and the net's fail estimate value's expected input value. 2. The method for estimating a failure location of an LSI according to claim 1, wherein the failure estimation of the combinational circuit is performed using the procedure described above.