JP2904129B2 - Fault diagnosis device and fault diagnosis method for CMOS integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault diagnosis apparatus and a fault diagnosis method for a CMOS integrated circuit, and more particularly to Iddq.
(DC power supply current) The CMOS (Complementary Metal-
The present invention relates to a fault diagnosis method for estimating a fault location in an integrated circuit (Oxide Semiconductor) integrated circuit.

[0002]

2. Description of the Related Art Conventionally, this type of fault diagnosis method has been used for the purpose of identifying a fault location in order to determine the cause of a fault in a CMOS integrated circuit in which a fault has occurred. There is a method of identifying a failure location by observing the voltage of each part on an integrated circuit chip.

Japanese Patent Application Laid-Open No. 5-45423 describes a technique for obtaining a potential contrast image of an integrated circuit at high speed and without deterioration in failure analysis of the integrated circuit using an electron beam tester.

In this technique, while driving an integrated circuit using an LSI (Large Scale Integrated Circuit) tester, a potential contrast image is obtained in synchronization with the drive timing. At this time, a test pattern for obtaining a potential contrast image is used. It is characterized in that a potential contrast image is obtained while holding the applied state temporarily.

As other failure diagnosis methods, there are a failure diagnosis method using an emission microscope, a failure diagnosis method using a liquid crystal, and the like. High integration has made it difficult to identify the location of the failure.

[0006]

In the above-mentioned conventional failure diagnosis method, in the case of a method of analyzing a failure of an integrated circuit using an electron beam tester, a wiring potential of the integrated circuit is measured by using an electron beam. Therefore, it becomes difficult to measure a target wiring potential due to miniaturization, multi-layering, and high-density of the integrated circuit, and it becomes impossible to specify a failed portion.

Further, in the function test of a device, in the case of an Iddq fault in which no abnormality is detected in the input / output signal value and an abnormal power supply current flows specifically only under a specific input condition, this conventional method is used for a normal device. In this method, the wiring is traced such that the expected signal value of the wiring on the chip and the signal value of the wiring in an actual device are different from each other, and a failure point is specified.

When an Iddq failure occurs, an extremely large current flows depending on the state of the circuit, and the performance expected when used in a device requiring low power consumption, such as a portable telephone, cannot be obtained.

In view of the above, an object of the present invention is to solve the above-mentioned problems, and in a CMOS integrated circuit, a functional test does not detect an abnormality in an input / output signal value, but an abnormality occurs in a power supply current value depending on a test pattern. It is an object of the present invention to provide a fault diagnosis apparatus and a fault diagnosis method for a CMOS integrated circuit, which can specify a fault location which caused a fault in an Iddq fault fault including a plurality of faults.

Another object of the present invention is to provide a CM which can indicate a position on a chip where a failure actually occurs.
An object of the present invention is to provide a failure diagnosis device and a failure diagnosis method for an OS integrated circuit.

[0011]

SUMMARY OF THE INVENTION A failure diagnosis apparatus for a CMOS integrated circuit according to the present invention is a CMOS integrated circuit in which no abnormality is detected in a function test and a DC power supply current abnormality occurs only in a specific test pattern in a DC power supply current test. CMOS for performing failure diagnosis on a circuit by using the test result of the functional test and the test result of the DC power supply current test
A failure diagnosis device for an integrated circuit, comprising: test pattern storage means for storing a test pattern describing input / output signals to and from a circuit for performing the function test; Test means for performing a current test and measurement of the value of the DC power supply current; and a test for storing a test result of the function test, a test result of the DC power supply current test, and a measurement result of the DC power supply current by the test means. A result storage unit, a circuit data storage unit for storing circuit data recording element arrangement information, element function information, and wiring connection information between the element and the terminal of the circuit under test; and a circuit data storage unit based on the test pattern and the circuit data. A logic simulator that logically simulates the operation of the circuit every moment when the test pattern is applied to the circuit under test. A simulation result storage unit for storing a simulation result of the logic simulator; a failure candidate set predicted from the test result of the functional test, the test result of the DC power supply current test, and the simulation result; Fault location determining means for generating a simultaneous linear equation having an unknown DC power supply current flowing at the time of execution and estimating a short-circuit fault between signal lines including a plurality of faults by solving the simultaneous linear equation. .

Another CMOS integrated circuit failure diagnosis apparatus according to the present invention, in addition to the above-described configuration, further comprises position information of each wiring on a chip of the CMOS integrated circuit and the CMOS.
A layout information storage unit for storing correspondence information of each wiring of a gate-level circuit of the integrated circuit; and a failure that may cause a failure due to a layout limitation based on the information stored in the layout information storage unit. Selecting means for selecting an occurrence location, wherein the failure location determination means,
A fault candidate set predicted from the test result of the functional test, the test result of the DC power supply current test, and the simulation result at the fault occurrence location selected by the selection unit is created and flows when each fault exists. The system is configured so as to estimate a short-circuit fault between signal lines including a plurality of faults by creating a simultaneous linear equation having a DC power supply current as an unknown number and solving the simultaneous linear equation.

Another CMOS integrated circuit failure diagnosis apparatus according to the present invention, in addition to the above-described configuration, further comprises: position information of each wiring on a chip of the CMOS integrated circuit;
A layout information storage unit for storing correspondence information of each wiring of a gate level circuit of the integrated circuit; and a CMOS based on the short-circuit fault estimated by the fault location determination unit and the layout information stored in the layout information storage unit. Means for specifying a location where a failure has actually occurred on the chip of the integrated circuit.

The method for diagnosing a fault in a CMOS integrated circuit according to the present invention is applicable to a CMOS integrated circuit in which no abnormality is detected in a function test and a DC power supply current abnormality occurs only in a specific test pattern in a DC power supply current test. A failure diagnosis method for a CMOS integrated circuit that performs failure diagnosis by using a test result of a test, a test result of the DC power supply current test, and a measurement result of the DC power supply current, wherein a circuit for performing the function test is provided. A first step of performing the functional test and the DC power supply current test based on a test pattern describing the input / output signals of the DC power supply current test;
When applying a test pattern in which no abnormality is detected
Test in which the abnormality is not detected when the normal condition is not detected
In the CMOS integrated circuit at the time when the pattern is applied,
Of the internal operation of the CMOS integrated circuit.
A second step of obtaining from the translation result, the direct current
Apply a test pattern that detects an abnormality in the source current test.
If an error is detected when the
The CMOS integrated circuit at the time of applying the strike pattern
Of the internal operation of the CMOS integrated circuit.
A third step of obtaining from a simulation result;
A fourth step of selecting a short-circuit fault as a fault candidate from the simulation result of the internal operation of the MOS integrated circuit, the test results of the function test and the DC power supply current test, and the simulation results obtained in each of the second and third steps; Steps, and assuming that each of the failure candidates existed
Create a system of linear equations with the flowing DC power supply current as an unknown
Multiple faults by solving the simultaneous linear equations
And a fifth step of selecting a short-circuit fault between the signal lines including the signal line .

In the method for diagnosing a failure of a CMOS integrated circuit according to the present invention, in addition to the above-described steps, the position information of each wiring on a chip of the CMOS integrated circuit and the CMOS
A step of selecting a failure location where a failure may occur from a restriction on a layout based on the correspondence information of each wiring of a gate level circuit of the integrated circuit, and selecting only a failure at the failure location as a failure candidate I try to diagnose.

The method for diagnosing a fault in a CMOS integrated circuit according to the present invention may include, in addition to the steps described above, the short-circuit fault estimated in the fifth step, the position information of each wiring on the chip of the CMOS integrated circuit, and the CMOS. From the corresponding information of each wiring of the gate level circuit of the integrated circuit, the CM
The method includes a step of identifying a place on the chip of the OS integrated circuit where a failure actually occurs.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the operation of the present invention will be described below.

A failure diagnosis apparatus for a CMOS integrated circuit according to the present invention includes a test pattern storage unit for storing a test pattern for performing a function test, a function test for the CMOS integrated circuit based on the test pattern, and a power supply current. An LSI tester for performing an Iddq test to be observed, a test result storage unit for recording the results of each of the functional test and the Iddq test, a circuit data storage unit for storing circuit data of the CMOS integrated circuit, and a circuit data and a test pattern. A logic simulator that simulates the behavior of the signal value of each signal line inside the circuit when a test pattern is given to the circuit, a simulation result storage unit that stores an expected value of the circuit operation as a simulation result, Failure occurs from test results And a failure location judgment unit for outputting the estimated position of the point that could have been estimated.

As a result, in the CMOS integrated circuit, no abnormality is detected in the input / output signal value in the function test, but the failure location that caused the failure in the Iddq failure where the power supply current value specifically occurs due to the test pattern. Can be specified including a plurality of failures.

Here, the mechanism by which the Iddq abnormal current flows will be considered. Now, it is assumed that the wiring of the signal value “1” and the wiring of the signal value “0” are short-circuited by the resistor R for some reason. In this case, if the resistance value of the resistor R is sufficiently large, the signal value of each signal line does not exceed the threshold value,
Still keeps "1" and "0". However, the short-circuit current due to the resistor R is reflected in the power supply current of the entire device and becomes an abnormally large current that is not normally detected.
ddq is detected as abnormal.

The Iddq abnormality caused by the resistor R occurs only when the signal values of both signal lines are different from each other. If the signal values of both signal lines are the same, no Iddq abnormality is detected. That is, when a test pattern p is applied, a set of signal lines indicating a signal value “1” is H (p), and a set of signal lines indicating a signal value “0” is L (p).
If no dq abnormal current flows, there is no short-circuit fault between any signal lines between H (p) and L (p).

If an Iddq abnormal current flows, H
A short circuit fault exists between the signal lines between (p) and L (p). At this time, the signal value of the power supply line is set to "1", the signal value of the ground line is set to "0", and each of them is regarded as a signal line, so that a short-circuit fault involving the power supply line and the ground line is also diagnosed. It is possible.

By inputting the test pattern to the CMOS integrated circuit and testing the presence / absence of an Iddq abnormal current for each pattern, candidates for the position where a short-circuit fault exists are listed as combinations of signal lines.

When an Iddq abnormality is observed when a certain test pattern is input to a CMOS integrated circuit, a failure candidate at that time is represented by fi, and an Iddq abnormal current value due to the failure fi is represented by Ii.

When the test pattern p is input to the CMOS integrated circuit, an Iddq abnormality is detected. If the Iddq abnormal current value at that time is Iddq (p), the failure candidate fi becomes apparent by the input of the test pattern p. Then (that is, if the values of the two signal lines indicated by the failure candidate fi contradict each other), it is assumed that Dip = 1, and if it is not actualized that Dip = 0, fi × Ii × Dip [... (1) ]
, I equals Iddq (p).

For all the test patterns in which the Iddq abnormal current is detected, the equation (1) is obtained to calculate Ii. If Iii0, the existence of the fault fi is estimated.
If Ii = 0, the existence of the fault fi is negated.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, a failure diagnosis apparatus for a CMOS integrated circuit according to an embodiment of the present invention includes a test pattern storage unit 1, a circuit data storage unit 2, an LSI tester 3, and a CMOS integrated circuit DUT (DeviceUn
der Test (hereinafter referred to as DUT) 4, a logic simulator 5, a test result storage unit 6, a simulation result storage unit 7, and a fault location determination unit 8.

The test pattern storage unit 1 has a DUT for testing the function of the DUT 4 as a device under test.
A test pattern which is a signal sequence of input / output to / from 4 is stored. The circuit data storage unit 2 stores the gate level circuit information of the DUT 4. Here, the circuit information is the information of the existing circuit elements,
It comprises connection information between input / output signal pins of the UT 4 and information describing the functional operation of the circuit element.

The LSI tester 3 is connected to the test pattern storage unit 1, performs a functional test of the DUT 4 connected to the LSI tester 3 based on the test pattern sent from the test pattern storage unit 1, and simultaneously performs individual test operations. The power supply current of the DUT 4 is observed for each pattern, and an Iddq test is performed to test whether the power supply current flows over a specified value. The results of the functional test and the Iddq test are sent to the test result storage unit 6 and stored.

The logic simulator 5 is connected to the test pattern storage unit 1 and the circuit data storage unit 2,
A simulation of a circuit operation when a test pattern is applied to the DUT 4 is executed. The result of the simulation is sent to and stored in the simulation result storage unit 7.

The fault location determination unit 8 is connected to the test result storage unit 6 and the simulation result storage unit 7, and based on the data sent from each of them, the DU unit.
The fault location existing at T4 is determined. This determination result is output as the diagnosis result 9.

FIGS. 2 and 3 are flowcharts showing the processing operation of one embodiment of the present invention, and FIG. 4 is a circuit diagram showing an example of an example circuit for explaining the processing operation of one embodiment of the present invention. FIG. 5 is a diagram showing an example of a test pattern for the example circuit shown in FIG. 4, FIG. 6 is a diagram showing an example of a simulation result of the example circuit shown in FIG. 4, and FIG. 7 is an example of the example circuit shown in FIG. FIG. 9 is a diagram illustrating an example of a test result of a circuit.

In FIG. 4, the example circuit is an inverter 11
To 13 and NAND circuits 14 to 18. The inverter 11 inverts the signal input via the signal line y and outputs the inverted signal to the NAND circuits 14 and 15 via the signal line a.

The inverter 12 inverts the signal input through the signal line w, and outputs the inverted signal to the NAND circuit 17 through the signal line b. Inverter 13 inverts the signal input through signal line z, and outputs the inverted signal to NAND circuit 17 through signal line c.

The NAND circuit 14 takes the NAND of the signal input through the signal line x and the signal input from the inverter 11 through the signal line a, and outputs the result to the NAND circuit 18 through the signal line d. Output. The NAND circuit 15 NANDs the signal input through the signal lines w and z and the signal input from the inverter 11 through the signal line a, and outputs the result to the NAND circuit 18 through the signal line e. I do.

The NAND circuit 16 takes the NAND of the signal input through the signal lines x, y, z and outputs the result to the signal line f.
And outputs the result to the NAND circuit 18. The NAND circuit 17 is connected to the signal input through the signal line x and the inverters 12 and 1.
3 and outputs the result to a NAND circuit 18 via a signal line g. The NAND circuit 18 takes the NAND of the signal input from each of the NAND circuits 14 to 17 via the signal lines d, e, f, and g, and outputs the result via the signal line u.

In FIG. 5, test pattern # 1
# 16 are the signal values on the signal lines x, y, w, z and u, respectively. In this example, “00000” is used as test pattern # 1 and “0001” is used as test pattern # 2.
0, "00100" as test pattern # 3, "00111" as test pattern # 4, "01000" as test pattern # 5, "01010" as test pattern # 6, and "0110" as test pattern # 7.
0, “01110” as test pattern # 8, “10001” as test pattern # 9, “10011” as test pattern # 10, “10101” as test pattern # 11, and “1” as test pattern # 12.
0111 ”and“ 1100 as test pattern # 13.
1 "," 11010 "as test pattern # 14," 11100 "as test pattern # 15, and" 11111 "as test pattern # 16, which are stored in the test pattern storage unit 1.

Further, in FIG. 6, simulation results # 1 to # 16 of the example circuit are signal lines x, y, w,
It consists of signal values on z, a, b, c, d, e, f, g, u.

In this example, the simulation result # 1 is "000011111110", the simulation result # 2 is "000111011110", the simulation result # 3 is "00101011110",
As the simulation result # 4, “001110010
111 ”and“ 0100 ”as the simulation result # 5.
01111110 ", simulation result # 6 is" 010101011110 ", simulation result # 7 is" 011000111110 ", simulation result # 8 is" 011100011110 ",
“100011101” as a simulation result # 9
101 ”, and“ 100 ”as the simulation result # 10.
“111001111”, “101010111111” as the simulation result # 11, “101110000011” as the simulation result # 12, and “1100011111” as the simulation result # 13.
01 ”and“ 1101 ”as the simulation result # 14.
01011110 "," 111000111110 "as the simulation result # 15, and" 111100011011 "as the simulation result # 16 are stored in the simulation result storage unit 7, respectively.

Further, in FIG. 7, the test results of the example circuit include the result of the functional test (bad), the result of the Iddq test (bad), and Idd for each of test patterns # 1 to # 16.
q current value (mA).

In this example, the result of the function test is “normal” corresponding to the test pattern # 1, and the result of the Iddq test is “normal”.
And Iddq current value = 0 (mA) are stored.
"Normal" as a result of the function test corresponding to test pattern # 2
And the result of the Iddq test “normal”, and the Iddq current value =
0 (mA) is stored.

In response to test pattern # 3, the result of the function test is "normal", the result of the Iddq test is "normal", and Id
The dq current value = 0 (mA) is stored, and the result of the function test corresponding to test pattern # 4 is “normal”, and Id
As a result of the dq test, “abnormal” and Iddq current value = 0.7
(MA).

In response to test pattern # 5, the result of the function test is "normal", the result of the Iddq test is "normal",
The dq current value = 0 (mA) is stored, and the result of the function test corresponding to test pattern # 6 is “normal”, and Id
As a result of the dq test, "normal" and Iddq current value = 0 (m
A) are stored.

In correspondence with test pattern # 7, the result of the function test is "normal", the result of the Iddq test is "normal", and Id
The dq current value = 0 (mA) is stored, and the result of the function test corresponding to test pattern # 8 is “normal”, and Id
As a result of the dq test, "normal" and Iddq current value = 0 (m
A) are stored.

According to test pattern # 9, the result of the function test is "normal", the result of the Iddq test is "abnormal", and Id
The current value of dq = 3.4 (mA) is stored, and the result of the function test corresponding to test pattern # 10 is “normal”.
And the result of the Iddq test “abnormal”, and the Iddq current value =
1.1 (mA) is stored.

According to test pattern # 11, the result of the function test is “normal”, the result of the Iddq test is “abnormal”, and
The ddq current value = 1.1 (mA) is stored, and the result of the function test corresponding to the test pattern # 12 is “normal”.
And the result of the Iddq test “abnormal”, and the Iddq current value =
1.1 (mA) is stored.

According to test pattern # 13, the result of the function test is "normal", the result of the Iddq test is "abnormal",
ddq current value = 2.3 (mA) is stored, and as a result of the function test corresponding to test pattern # 14, “normal”
And the result of the Iddq test “normal”, and the Iddq current value =
0 (mA) is stored.

According to the test pattern # 15, the result of the function test is “normal”, the result of the Iddq test is “normal”,
The ddq current value = 0 (mA) is stored, and the result of the function test corresponding to the test pattern # 16 is “normal”;
As a result of the Iddq test, “abnormal” and an Iddq current value = 0.
7 (mA) is stored. These test results are stored in the test result storage unit 6.

The operation of the embodiment of the present invention will be described with reference to FIGS. It is assumed that the test pattern storage unit 1, test result storage unit 6, and simulation result storage unit 7 store data as shown in FIGS.

The pattern information stored in the test pattern storage unit 1 is sent to the LSI tester 3 and is input from the LSI tester 3 to the DUT 4 (Step S1 in FIG. 2).
The pattern information includes a signal vector input to the DUT 4 at a certain time step and an expected output vector of the DUT 4. The pattern information in the example circuit shown in FIG. 4 is as shown in FIG.

The LSI tester 3 inputs a signal vector to the DUT 4 based on the test pattern,
4 is compared with the output vector described in the test pattern (step S in FIG. 2).
2) The result is sent to and stored in the test result storage unit 6 (step S3 in FIG. 2).

The LSI tester 3 monitors the power supply current of the DUT 4 flowing when the signal vector is input to the DUT 4 based on the test pattern. This power supply current value is Iddq (p).
It is determined that ddq is abnormal. In that case, the determination result of Iddq abnormality and the value of Iddq (p) are also sent to the test result storage unit 6 and stored.

The circuit information of the DUT 4 is stored in the circuit data storage unit 2, and this circuit information is composed of information on elements constituting the DUT 4, information on connections between elements and between external terminals, and information on function of the elements. ing. This circuit information is stored in the logic simulator 5 together with the test pattern information.
To simulate the operation of the DUT 4 when the test pattern is input to the DUT 4.

In this simulation, the change of the value of the signal line inside the DUT 4 is also recorded, and the operation result of the DUT 4 including the change of the value of the external terminal is stored in the simulation result storage unit 7. For the example circuit shown in FIG.
The result of simulating the operation of the circuit when the pattern information shown in FIG. 5 is input is as shown in FIG.

As a result of inputting a series of test patterns to the DUT 4, no functional failure was detected in the DUT 4,
It is assumed that Iddq abnormality is detected in some pattern inputs.

In the case of the example circuit shown in FIG. 4, the signal lines e and f
It is assumed that a short-circuit fault occurs between the signal line d and the power supply line vdd, and a short-circuit fault occurs between the signal line g and the power supply line vdd. These short-circuit faults do not affect the function of the example circuit, but assume that an Iddq abnormality has occurred. This example circuit is shown in FIG.
FIG. 7 shows the results of an Iddq test performed using the pattern information shown in FIG.

The fault location judging unit 8 executes the following processing from the simulation results stored in the simulation result storage unit 7 and the test results stored in the test result storage unit 6 to estimate a fault location.

The failure point determination unit 8 first sets a set S of combinations of all signal lines as a set F of candidate combinations of signal lines that may have a failure (step S4 in FIG. 2). The above p (pattern number) is set to 1 (step S5 in FIG. 2).

Assume that no Iddq abnormality is detected when the test pattern p is applied to the DUT 4. The value of each signal line inside the DUT 4 when the test pattern p is applied can be known from the simulation result.
(P) is a set of signal lines whose signal values are “1”, L (p)
Is a set of signal lines whose signal values are “0”.

In the case of the example circuit shown in FIG. 4, a set H of signal lines indicating "1" when test pattern # 1 is applied.
(1), a set L (1) of signal lines indicating “0” is H (1) = {a, b, c, d, e, f, g, vdd} L (1) = {x, y, w, z, u, gnd} (steps S6 to S8 in FIG. 2).

For the combination of signal lines indicated by C (H (p), L (p)), no short-circuit fault exists because no Iddq abnormality was detected. However, the above C (H
(P), L (p)) is C (H, L) = {(h, l): h ： H, l∈L, (h,
l) = (l, h)｝.

In the case of the example circuit shown in FIG. 4, C (H (1), L (1)) = ｛(a, x), (a,
y), (a, w), (a, z), (a, u), (a, g)
nd), (b, x), (b, y), (b, w), (b,
z), (b, u), (b, gnd), (c, x),
(C, y), (c, w), (c, z), (c, u),
(C, gnd), (d, x), (d, y), (d,
w), (d, z), (d, u), (d, gnd),
(E, x), (e, y), (e, w), (e, z),
(E, u), (e, gnd), (f, x), (f,
y), (f, w), (f, z), (f, u), (f, g
nd), (g, x), (g, y), (g, w), (g,
z), (g, u), (g, gnd), (vdd, x),
(Vdd, y), (vdd, w), (vdd, z),
(Vdd, u), (vdd, gnd)}. In this case, for example, no short-circuit fault exists between the signal lines a and x. If a short-circuit fault exists between the signal lines a and x, an Iddq abnormality should be detected when the test pattern # 1 is applied.

After setting the above p (pattern number) to 1 (step S5 in FIG. 2), the test results for the test pattern p are read out one by one from the test result storage unit 6 (step S6 in FIG. 2). The test result is Idd
It is determined whether q is abnormal (step S7 in FIG. 2), and Iddq
A set H (p) of signal lines having a signal value of “1” and a set of signal lines having a signal value of “0” based on the simulation result of the simulation result storage unit 7 for a test result determined to be not abnormal. L (p) (step S8 in FIG. 2).

From the set S of combinations of all signal lines,
C (H (p), L where no ddq abnormality was detected
(P)). However, since the set S is set to the set F in step S4, [FC (H
(P), L (p)) → F]. {Circle around (1)}, the combinations of signal lines that may have a short-circuit fault are narrowed down (step S9 in FIG. 2).

By performing this operation for all the test patterns p in which no Iddq abnormality is detected, a set F = {fi} of candidate combinations of signal lines which may have a failure is obtained (FIG. 2). Steps S6 to S1
1). In this case, assuming that the number of test patterns is n, p>
The above operation is repeated until n is reached.

In the example circuit shown in FIG. 4, as shown in FIG. 7, test patterns # 1, # 2, # 3, # 5, #
Since no Iddq abnormality is detected in 6, # 7, # 8, # 14, and # 15, a set F of candidate combinations of signal lines that may have a failure is given by F = S−C ( H (1), L (1))-C (H (2), L (2))-C (H (3), L (3))-C (H (5), L (5))- C (H (6), L (6))-C (H (7), L (7))-C (H (8), L (8))-C (H (14), L (14) ) −C (H (15), L (15)) = ｛(d, e), (d, f), (e, f), (d, g), (e, g), (f, g) ), (Gnd, u), (d, vdd), (e, vdd), (f, vdd), (g, vdd)}, and the combination of the signal lines in which the failure may have occurred. A set F of candidates is transmitted (step S1 in FIG. 2).
2). A short-circuit fault exists in any one of the signal line combinations shown here (there may be more than one).

On the other hand, it is assumed that an Iddq abnormality is detected when the test pattern q is applied to the DUT 4. This is C
This means that a set of combinations of signal lines represented by (H (q), L (q)) includes a fault causing an Iddq abnormality.

That is, of all the faults existing in the DUT 4, some of the faults become apparent due to a change in the internal state of the circuit of the DUT 4 due to the application of the test pattern q. The current flows, and the Iddq abnormality is detected.

Assuming that a set of elements of C (H (q), L (q)) included in the above set F is G (q), a fault that has become obvious by the application of the test pattern q is a set G (q )include.

In the example circuit shown in FIG. 4, when the test pattern # 4 is applied, the Iddq abnormality is detected.
At this time, a set H (4) of signal lines indicating “1”, “0”
L (4) = {w, z, a, d, f, g, u, vdd} L (4) = {x, y, b, c, e , Gnd}.

This is because after setting the above q (pattern number) to 1 (step S13 in FIG. 3), the test pattern q
Is read out from the test result storage unit 6 one by one (step S14 in FIG. 3), and the test result is
It is determined whether or not ddq is abnormal (step S15 in FIG. 3).
A set H (q) of signal lines having a signal value of “1” and a signal line having a signal value of “0” based on the simulation result of the simulation result storage unit 7 for the test result determined to be ddq abnormal. (Step S16 in FIG. 3).

A set G (q) of these C (H (q), L (q)) elements included in the set F is obtained (step S17 in FIG. 3). In the above case, since the Iddq abnormality was detected when test pattern # 4 was applied, the set G (4) of the elements of C (H (4), L (4)) included in the set F was , G (4) = F∧C (H (4), L (4)) = ｛(d, e), (d, f), (e, f), (d, g), (e, g ), (F, g), (gnd, u), (d, vdd), (e, vdd), (f, vdd), (g, vdd)} {(w, x), (w, y) ), (W, b), (w, c), (w, e), (w, gnd), (z, x), (z, y), (z, b), (z, c), (Z, e), (z, gnd), (a, x), (a, y), (a, b), (a, c), (a, e), (a, gnd), (d , X), (d, y), (d, b), (d, c), (d, e), (d, gnd), f, x), (f, y), (f, b), (f, c), (f, e), (f, gnd), (g, x), (g, y), (g, b), (g, c), (g, e), (g, gnd), (u, x), (u, y), (u, b), (u, c), (u, e) , (U, gnd), (vdd, x), (vdd, y), (vdd, b), (vdd, c), (vdd, e), (vdd, gnd)｝ = {(d, e) , (E, f), (e, g), (u, gnd), (e, vdd)}.

By performing this operation on all the test patterns q in which the Iddq abnormality is detected, a set G (q) included in the set F is obtained (FIG. 3).
Steps S14 to S19). In this case, assuming that the number of test patterns is n, the above operation is repeated until q> n.

The combination of signal lines represented by G (q) is represented by Δg
q1, gq2,..., gqn), and the Iddq current due to the fault gqi when the short-circuit fault gqi exists is unknown Iddq.
If (q, i), then Iddq (q) = ΣIdddq (q, i). Here, Σ is the sum of i = 1 to n.

When the above equation is obtained for all the test patterns q in which Iddq abnormality is detected, Iddq (q, i)
Is obtained as a simultaneous linear equation A. This coalition 1
By solving the following equation, Iddq (q, i) is determined. At this time, if Iddq (q, i) = 0,
There is no short circuit fault between the signal lines indicated by gqi. If Iddq (q, i) ≠ 0, it is estimated that a short-circuit fault exists between signal lines indicated by gqi.

When the simultaneous linear equation A is obtained for the example circuit shown in FIG. 4, 0.7 = i (d, e) + i (e, f) + i (gnd,
u) + i (e, vdd) 3.4 = i (d, e) + i (d, f) + i (e, g) +
i (f, g) + i (gnd, u) + i (d, vdd) +
i (g, vdd) 1.1 = i (d, e) + i (d, f) + i (d, g) +
i (gnd, u) + i (d, vdd) 1.1 = i (d, e) + i (d, f) + i (d, g) +
i (gnd, u) + i (d, vdd) 1.1 = i (d, g) + i (e, g) + i (f, g) +
i (gnd, u) + i (d, vdd) + i (e, vd
d) + i (f, vdd) 2.3 = i (d, g) + i (e, g) + i (f, g) +
i (gnd, u) + i (g, vdd) 0.7 = i (d, f) + i (e, f) + i (f, g) +
i (gnd, u) + i (f, vdd). Here, i (s, t) represents an Iddq current due to a short circuit fault of the signal lines s, t.

Under the constraint that i (s, t) ≧ 0, one of the solutions of this simultaneous linear equation A is as follows: i (d, e) = 0 i (e, f) = 0.7 i (e, g) = 0 i (d, f) = 0 i (gnd, u) = 0 i (e, vdd) = 0 i (d, vdd) = 1.1 i (g, vdd) = 2 0.3 i (d, g) = 0 i (f, g) = 0 i (f, vdd) = 0

From the above description, a short-circuit fault between the signal lines e and f, a short-circuit fault between the signal lines d and vdd, a signal line g and vdd
A short-circuit fault is estimated (step S20 in FIG. 3). This estimation result is output as the diagnosis result 9.

FIG. 8 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a failure diagnosis device for a CMOS integrated circuit according to another embodiment of the present invention includes a failure location determination unit 8a instead of the failure location determination unit 8,
Except that the layout information storage unit 10 is provided, it has the same configuration as the CMOS integrated circuit failure diagnosis apparatus according to the embodiment of the present invention shown in FIG. 1, and the same components are denoted by the same reference numerals. The operation of the same component is the same as that of the embodiment of the present invention.

The layout information storage unit 10 has a DU
Information indicating the position of each wiring on the T4 chip and which signal line each wiring corresponds to when the DUT 4 is represented by a gate level circuit is stored.

The fault location judging unit 8a is connected to the test result storage unit 6, the simulation result storage unit 7, and the layout information storage unit 10, and determines a fault location existing in the DUT 4 based on data sent from each of them. judge. This determination result is output as the diagnosis result 9.

FIGS. 9 and 10 are flow charts showing the processing operation of another embodiment of the present invention. These FIGS. 8 to 1
The operation of the example circuits shown in FIGS. 4 to 7 will be described with reference to FIG. It is assumed that the test pattern storage unit 1, test result storage unit 6, and simulation result storage unit 7 store data as shown in FIGS.

The pattern information stored in the test pattern storage unit 1 is sent to the LSI tester 3 and is input from the LSI tester 3 to the DUT 4 (step S2 in FIG. 9).
1). The pattern information includes a signal vector input to the DUT 4 at a certain time step and an expected output vector of the DUT 4. The pattern information in the example circuit shown in FIG. 4 is as shown in FIG.

The LSI tester 3 inputs a signal vector to the DUT 4 based on the test pattern,
4 is compared with the output vector described in the test pattern (step S in FIG. 9).
22), and sends the result to the test result storage unit 6 for storage (step S23 in FIG. 9).

The LSI tester 3 monitors the power supply current of the DUT 4 flowing when the signal vector is input to the DUT 4 based on the test pattern. This power supply current value is Iddq (p).
It is determined that ddq is abnormal. In that case, the determination result of Iddq abnormality and the value of Iddq (p) are also sent to the test result storage unit 6 and stored.

The circuit information of the DUT 4 is stored in the circuit data storage unit 2, and this circuit information is composed of information on elements constituting the DUT 4, information on connections between elements and between external terminals, and information on function of the elements. ing. This circuit information is stored in the logic simulator 5 together with the test pattern information.
To simulate the operation of the DUT 4 when the test pattern is input to the DUT 4.

In this simulation, the change in the value of the signal line inside the DUT 4 is also recorded, and the operation result of the DUT 4 including the change in the value of the external terminal is stored in the simulation result storage unit 7. The result of simulating the operation of the example circuit shown in FIG. 4 when the pattern information shown in FIG. 5 is inputted is as shown in FIG.

As a result of inputting a series of test patterns to the DUT 4, no functional failure was detected in the DUT 4,
It is assumed that Iddq abnormality is detected in some pattern inputs.

In the case of the example circuit shown in FIG. 4, the signal lines e and f
It is assumed that a short-circuit fault occurs between the signal line d and the power supply line vdd, and a short-circuit fault occurs between the signal line g and the power supply line vdd. These short-circuit faults do not affect the function of the example circuit, but assume that an Iddq abnormality has occurred. This example circuit is shown in FIG.
FIG. 7 shows the results of an Iddq test performed using the pattern information shown in FIG.

The fault location judging unit 8a executes the following processing from the simulation results stored in the simulation result storage unit 7 and the test results stored in the test result storage unit 6 to estimate a fault location.

Here, it is obvious that a short circuit fault between signal lines occurs between adjacent or crossing wirings on a chip of a CMOS integrated circuit, and it does not occur between all signal lines. Therefore, if a set S ′ of adjacent or intersecting wirings is used instead of the set S of all combinations of signal lines in one embodiment of the present invention, a fault that can actually occur in the fault candidate set F is A set F 'of new picked-up failure candidates is obtained. Hereinafter, the set F ′ is used in place of the set F in the above-described embodiment of the present invention, a portion where a short-circuit fault has occurred is estimated, and a diagnosis result 9 is output.

Therefore, the failure point judging unit 8a first sets the set S 'of adjacent or intersecting wirings to the set F' (step S24 in FIG. 9), and sets 1 to the above-mentioned p (pattern number) (FIG. 9). 9 steps S25).

In the example circuit shown in FIG. 4, a fault set S ′ that can be generated based on the layout information is as follows: S ′ = ｛(x, a), (x, w), (x, z), (x, z)
b), (x, d), (x, f), (x, g), (y,
a), (w, z), (w, e), (w, f), (w,
b), (z, e), (z, f), (z, c), (a,
d), (a, e), (b, g), (b, c), (d,
u), (d, e), (e, f), (e, u), (f,
u), (g, u), (x, vdd), (x, gnd),
(Y, vdd), (y, gnd), (w, vdd),
(W, gnd), (z, vdd), (z, gnd),
(A, vdd), (a, gnd), (b, vdd),
(B, gnd), (c, vdd), (c, gnd),
(D, vdd), (d, gnd), (e, vdd),
(E, gnd), (f, vdd), (f, gnd),
(G, vdd), (g, gnd), (u, vdd),
(U, gnd)}. This set S ′ is set to the set F ′.

Assume that no Iddq abnormality is detected when the test pattern p is applied to the DUT 4. The value of each signal line inside the DUT 4 when the test pattern p is applied can be known from the simulation result.
(P) is a set of signal lines whose signal values are “1”, L (p)
Is a set of signal lines whose signal values are “0”.

After setting the above p (pattern number) to 1 (step S2 in FIG. 9)
5) Read out the test results for the test pattern p from the test result storage unit 6 one by one (step S2 in FIG. 9).
6) It is determined whether or not the test result is Iddq abnormality (step S27 in FIG. 9).

As a result, the fault location determination unit 8a
A set H (p) of signal lines having a signal value of “1” and a signal line having a signal value of “0” are set based on the simulation result of the simulation result storage unit 7 for the test result determined to be not abnormal. A set L (p) is obtained (step S28 in FIG. 9).

In this case, C (H) in which no Iddq abnormality was detected from the set S ′ of adjacent or intersecting wirings was detected.
(P), L (p)). However, since the set S ′ is set to the set F ′ in step S24,
[F′−C (H (p), L (p)) → F ′]｝,
Combinations of signal lines that may have a short-circuit fault are narrowed down (step S29 in FIG. 9).

By performing this operation for all test patterns p in which no Iddq abnormality is detected, a set F ′ = {fi} is obtained (FIG. 9, steps S26 to S3).
1), a set F ′ of candidates for the combination of signal lines that may have a failure is transmitted (step S3 in FIG. 9).
2). A short-circuit fault exists in any one of the signal line combinations shown here (there may be more than one). in this case,
If the number of test patterns is n, the above operation is repeated until p> n.

On the other hand, it is assumed that an Iddq abnormality is detected when the test pattern q is applied to the DUT 4. This is C
This means that a set of combinations of signal lines represented by (H (q), L (q)) includes a fault causing an Iddq abnormality.

That is, among all the faults existing in the DUT 4, some faults become apparent due to a change in the state of the circuit inside the DUT 4 due to the application of the test pattern q, and the Iddq abnormality occurs in the DUT 4 due to the realized fault. The current flows, and the Iddq abnormality is detected.

Assuming that a set of elements of C (H (q), L (q)) included in the above set F ′ is G (q), a fault that has become obvious by application of the test pattern q is set G (q). q)
include.

After setting the above q (pattern number) to 1 (step S3 in FIG. 10).
3) The test results for the test pattern q are read out one by one from the test result storage unit 6 (step S in FIG. 10).
34), it is determined whether or not the test result is Iddq abnormality (step S35 in FIG. 10).

As a result, the fault location determination unit 8a
A set H (q) of signal lines having a signal value of “1” and a signal line having a signal value of “0” based on the simulation result of the simulation result storage unit 7 for the test result determined to be ddq abnormal. Is obtained (step S36 in FIG. 10).

A set G (q) of these C (H (q), L (q)) elements included in the set F ′ is obtained (step S37 in FIG. 10). By performing this operation on all the test patterns q in which the Iddq abnormality is detected, the set G included in the set F ′ is set.
(Q) is obtained (steps S34 to S39 in FIG. 10).
In this case, assuming that the number of test patterns is n, the above operation is repeated until q> n.

The combination of signal lines represented by G (q) is represented by Δg
q1, gq2,..., gqn), and the Iddq current due to the fault gqi when the short-circuit fault gqi exists is unknown Iddq.
If (q, i), then Iddq (q) = ΣIdddq (q, i). Here, Σ is the sum of i = 1 to n.

Using information S 'of a fault that can actually occur based on this layout information, F' = {(d, e), (e, f), (u, gnd),
(D, vdd), (e, vdd), (f, vdd),
(G, vdd)}.

In another embodiment of the present invention, the simultaneous linear equation A in one embodiment of the present invention is a simultaneous linear equation B as follows: 0.7 = i (d, e) + i (e , F) + i (gnd,
u) + i (e, vdd) 3.4 = i (d, e) + i (gnd, u) + i (d, v
dd) + i (g, vdd) 1.1 = i (d, e) + i (gnd, u) + i (d, v
dd) 1.1 = i (d, e) + i (gnd, u) + i (d, v
dd) 1.1 = i (gnd, u) + i (d, vdd) + i
(E, vdd) + i (f, vdd) 2.3 = i (gnd, u) + i (g, vdd) 0.7 = i (e, f) + i (gnd, u) + i (f, v
dd).

When this simultaneous linear equation B is solved, short-circuit faults between the signal lines e and f, short-circuit faults between the signal lines d and vdd, and short-circuit faults between the signal lines g and vdd are estimated as fault candidates ( FIG. 9 step S40). This estimation result is the diagnosis result 9
Is output as

FIG. 11 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, a fault diagnosis apparatus for a CMOS integrated circuit according to another embodiment of the present invention is similar to that of the other embodiment of the present invention shown in FIG. 8 except that a fault location determination unit 8b is provided instead of the failure location determination unit 8a. CMO
It has the same configuration as the failure diagnosis device for the S integrated circuit,
The same components are denoted by the same reference numerals. The operation of the same components is the same as in the other embodiments of the present invention.

The failure location determination unit 8b is connected to the test result storage unit 6, the simulation result storage unit 7, and the layout information storage unit 10, and determines the failure location existing in the DUT 4 based on the data sent from each of them. judge. This determination result is output as the diagnosis result 9.

FIGS. 12 and 13 are flowcharts showing the processing operation of another embodiment of the present invention. These FIGS.
The operation of the example circuits shown in FIGS. 4 to 7 will be described with reference to FIG. The test pattern storage unit 1
It is assumed that the test result storage unit 6 and the simulation result storage unit 7 store data as shown in FIGS.

Also, from step S41 in FIG. 12 to FIG.
Since the processing operation up to step S60 is the same as the operation of the other embodiment of the present invention shown in FIGS. 9 and 10, the description of the processing operation is omitted.

The fault location judging unit 8b according to another embodiment of the present invention receives the diagnostic output of the fault location judging unit 8a according to another embodiment of the present invention, and outputs the wiring information on the chip from the layout information storage unit 10 and the DUT 4. The fault location actually occurring on the chip is estimated from the gate level circuit information.

That is, if the diagnosis result is a short-circuit fault between the signal lines i and j, the fault location determination unit 8b determines the position occupied on the chip by the signal line i on the chip from the information stored in the layout information storage unit 10. The position occupied by the line j on the chip is obtained (step S61 in FIG. 13), and it is estimated that a short-circuit fault has occurred at a portion where the two wires cross or approach each other for some reason (step S62 in FIG. 13). This estimation result is output to the fault location determination unit 8b.
Is output as the diagnosis result 9 from

In the case of the example circuit shown in FIG. 4, the position on the chip where the signal lines e and f intersect is the coordinates (x1, y1) from the layout information, and the signal lines d and vdd intersect. The position of the part on the chip is represented by coordinates (x2, y
2), and assuming that the position on the chip where the signal lines g and vdd intersect is the coordinates (x3, y3),
Coordinates (x1, y1), (x2, y2), (x3, y
It is estimated that a short-circuit fault has occurred at the position 3).

FIG. 14 is a block diagram showing the configuration of still another embodiment of the present invention. In the drawing, a failure diagnosis apparatus for a CMOS integrated circuit according to still another embodiment of the present invention is based on the embodiment of the present invention shown in FIG. 1 except that a failure location determination unit 8c is provided instead of the failure location determination unit 8. The configuration is the same as that of the failure diagnosis device for a CMOS integrated circuit, and the same components are denoted by the same reference numerals. The operation of the same component is the same as that of the embodiment of the present invention.

The fault location judging unit 8c is connected to the test result storage unit 6 and the simulation result storage unit 7, and based on the data sent from each of these units,
The fault location existing in the UT 4 is determined. This determination result is output as the diagnosis result 9.

FIGS. 15 and 16 are flowcharts showing the processing operation of still another embodiment of the present invention. The operation of the example circuits shown in FIGS. 4 to 7 will be described with reference to FIGS. It is assumed that the test pattern storage unit 1, test result storage unit 6, and simulation result storage unit 7 store data as shown in FIGS.

Further, steps S71 in FIG. 15 to FIG.
Since the processing operation up to step S90 is the same as the operation of the embodiment of the present invention shown in FIGS. 2 and 3, the description of the processing operation is omitted.

The fault location determination unit 8c according to still another embodiment of the present invention provides a fault output of the failure location determination unit 8 according to one embodiment of the present invention with a fault having a low possibility of being present among the estimated short-circuit faults. Is removed, and only the fault having a high possibility of being present is transmitted as the diagnosis result 9.

That is, the fault location determination unit 8c
Similar to the failure point determination unit 8 in FIG. 1, the above-mentioned simultaneous linear equation A is obtained based on the test results from the test result storage unit 6 and the simulation results from the simulation result storage unit 7, and by solving this, the fault is obtained. Is output as the diagnosis result 9.

However, the number of unknowns and the number of equations of the simultaneous linear equation A fluctuate depending on the length of the test pattern and the like.
In some cases, the number of failure candidates may increase. Usually, since the number of simultaneously occurring faults is small, the fault location judging unit 8c has a possibility that the faults that have been pointed out as the fault candidates may have occurred in order from the one with the smallest number of simultaneously occurring faults. If the number is high, the one with the small number of failures is transmitted as a failure candidate (step S in FIG. 16).
91). The failure candidate is output as the diagnosis result 9 from the failure point determination unit 8c.

In the example circuit shown in FIG. 4, in addition to the fault actually occurring, for example, i (d, e) = 0.7 i (e, f) = 3.4 i (e, g) = 1.1 i (d, f) = 1.1 i (gnd, u) = 0 i (e, vdd) = 0 i (d, vdd) = 0 i (g, vdd) = 0 i (d, g ) = 2.3 i (f, g) = 0 i (f, vdd) = 0.7 may be obtained by solving the simultaneous linear equation A.

This is a short-circuit fault between the signal lines d and e, a short-circuit fault between the signal lines e and f, a short-circuit fault between the signal lines e and g, a short-circuit fault between the signal lines d and f, and the signal lines f and vdd. This indicates that a short-circuit fault between the two exists at the same time.

However, the possibility of failure occurring at three locations is much higher than that occurring at six locations at the same time. Output as a failure candidate with high possibility.

Although not described above, one embodiment of the present invention, another embodiment, another embodiment, and still another embodiment can be used in combination with each other.

As described above, the simulation result of the signal value inside the circuit when the Iddq abnormality is detected and the Iddq
A fault candidate is selected from the simulation result of the signal value in the circuit when the q abnormality is detected, and a simultaneous linear equation is derived for each fault using the Iddq current value flowing when the fault exists as an unknown value. By solving the linear equation, the fault that caused the Iddq abnormality is specified. That is, since the simultaneous linear equations are solved and the short-circuit fault is determined based on the magnitude of the solution, not only a single short-circuit fault but also a plurality of short-circuit faults can be diagnosed.

Therefore, in the CMOS integrated circuit, no abnormality is detected in the input / output signal value in the functional test, but an abnormality occurs in the power supply current value depending on the test pattern.
In the ddq failure failure, the failure location that caused the failure can be specified including a case where there are a plurality of failures.

Further, by utilizing the correspondence between the signal lines and the wiring on the integrated circuit chip and the wiring layout information having the positional information of the wiring on the chip, the position on the chip where the failure actually occurs is pointed out. It is possible to do.

[0130]

As described above, according to the CMOS integrated circuit failure diagnosis apparatus of the present invention, a CMOS integrated circuit in which an abnormality is not detected in a function test and an Iddq abnormality occurs only in a specific test pattern in an Iddq test. In a CMOS integrated circuit fault diagnosis apparatus that uses the test result of the functional test and the test result of the Iddq test, a failure candidate set predicted from the test result of the functional test, the test result of the Iddq test, and the simulation result To estimate a short-circuit fault between signal lines including a plurality of faults by creating and solving a system of linear equations having an Iddq current flowing when each fault exists as an unknown. No abnormalities are detected in the input / output signal values during the test, but the power supply current Abnormality there is an effect that a failure of the fault location from which it failure cause in Iddq failure fault occurring can be identified include plural.

According to another CMOS integrated circuit failure diagnosis apparatus of the present invention, the position information of each wiring on the chip of the CMOS integrated circuit and the correspondence information of each wiring of the gate level circuit of the CMOS integrated circuit are obtained. The location where the fault actually occurs on the chip of the CMOS integrated circuit is specified based on the estimated short-circuit fault and the layout information based on the stored short-circuit fault, and the position on the chip where the fault actually occurs is indicated. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing operation according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating a processing operation according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of an example circuit for explaining the processing operation of one embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of a test pattern for the example circuit illustrated in FIG. 4;

6 is a diagram illustrating an example of a simulation result of the example circuit illustrated in FIG. 4;

FIG. 7 is a diagram illustrating an example of a test result of the example circuit illustrated in FIG. 4;

FIG. 8 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 9 is a flowchart showing a processing operation of another embodiment of the present invention.

FIG. 10 is a flowchart showing a processing operation of another embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 12 is a flowchart showing a processing operation of another embodiment of the present invention.

FIG. 13 is a flowchart showing a processing operation of another embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of still another embodiment of the present invention.

FIG. 15 is a flowchart showing a processing operation of still another embodiment of the present invention.

FIG. 16 is a flowchart showing a processing operation of still another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test pattern storage unit 2 Circuit data storage unit 3 LSI tester 4 CMOS integrated circuit DUT 5 Logic simulator 6 Test result storage unit 7 Simulation result storage unit 8 Fault location judgment unit 9 Diagnosis result 10 Layout information storage unit

Claims (13)

(57) [Claims] 1. A test result of the function test and the DC power supply current test for a CMOS integrated circuit in which no abnormality is detected in the function test and a DC power supply current abnormality occurs only in a specific test pattern in the DC power supply current test. A failure diagnosis device for a CMOS integrated circuit that performs failure diagnosis by using the test result of (1), wherein a test pattern storage unit that stores a test pattern describing an input / output signal to a circuit for performing the function test; Test means for receiving the test pattern, performing the function test, the DC power supply current test, and measuring the value of the DC power supply current; the test result of the function test and the test result of the DC power supply current test by the test means; Test result storage means for storing the measurement results of the DC power supply current, element arrangement information and element function information of the circuit under test, elements and Circuit data storage means for storing circuit data in which wiring connection information between daughters is recorded; and a circuit which is constantly tuned when the test pattern is applied to the circuit under test based on the test pattern and the circuit data. A logic simulator for logically simulating an internal operation; a simulation result storage unit for storing a simulation result of the logic simulator; a test result of the functional test, a test result of the DC power supply current test, and a prediction based on the simulation result Short-circuiting between signal lines including a plurality of faults by creating a set of fault candidates, creating a simultaneous linear equation with the DC power supply current flowing when each fault exists as an unknown, and solving the simultaneous linear equation A failure diagnosis device comprising: a failure location determination unit that estimates a failure. 2. A layout information storage means for storing position information of each wiring on a chip of the CMOS integrated circuit and correspondence information of each wiring of a gate level circuit of the CMOS integrated circuit; Selecting means for selecting a fault occurrence location in which a fault may possibly occur from restrictions on the layout based on the stored information, wherein the fault location determining means includes the fault occurrence location selected by the selecting means. A simultaneous linear equation in which a set of fault candidates predicted from the test result of the functional test, the test result of the DC power current test, and the simulation result is created, and the DC power current flowing when each fault exists is an unknown number. And estimating a short-circuit fault between signal lines including a plurality of faults by solving the simultaneous linear equations. Fault diagnosis apparatus according to claim 1, symptoms. 3. The method according to claim 2, wherein the selecting unit is configured to select at least one of a location where the wirings are close to each other and a location where the wirings intersect on the chip of the CMOS integrated circuit as the failure occurrence location. The fault diagnosis device according to claim 2, wherein 4. A layout information storage means for storing position information of each wiring on a chip of the CMOS integrated circuit and correspondence information of each wiring of a gate level circuit of the CMOS integrated circuit; And a means for specifying a location where a fault has actually occurred on the chip of the CMOS integrated circuit from the estimated short-circuit fault and the layout information stored in the layout information storage means. 1. The failure diagnosis device according to 1. 5. A location on the CMOS integrated circuit chip where a fault has actually occurred based on the short-circuit fault estimated by the fault location determining means and the layout information stored in the layout information storage means. The fault diagnosis device according to claim 2 or 3, further comprising means. 6. The fault according to claim 1, further comprising a removing unit that removes a fault having a low possibility of being present among the short-circuit faults estimated by the fault location determining unit. Diagnostic device. 7. The fault diagnosis apparatus according to claim 6, wherein said removing means removes a short-circuit fault having a large number of faults occurring simultaneously as said fault having a low possibility of being present. 8. A test result of the function test and the DC power supply current test for a CMOS integrated circuit in which no abnormality is detected in the function test and the DC power supply current is abnormal only in a specific test pattern in the DC power supply current test. A method of diagnosing a failure in a CMOS integrated circuit that performs a failure diagnosis by using the test result of the above and the measurement result of the DC power supply current, wherein a test pattern describing an input / output signal to a circuit for performing the functional test A first step of performing the function test and the DC power supply current test based on the test pattern;
If no abnormality is detected when applying
At the time of applying a test pattern where no
The internal signal value of the CMOS integrated circuit is
A second step of obtaining from the simulation result of the internal operation of the road, the test pattern of abnormality is detected in the DC power supply current test
If an abnormality is detected when applying
The CMO at the time of applying the output test pattern
The signal value inside the S integrated circuit is stored in the CMOS integrated circuit.
A third step obtained from a simulation result of the operation of the unit, a simulation result of an internal operation of the CMOS integrated circuit, a test result of the function test and the DC power supply current test, and a simulation obtained in each of the second and third steps The fourth step is to select a short-circuit fault as a fault candidate from the result.
And the steps that flow when assuming that each of the failure candidates exists.
Create a simultaneous linear equation with the power supply current as an unknown and
Signals containing multiple faults by solving the system of linear equations
And a fifth step of selecting a short-circuit fault between lines . 9. A possibility that a failure may occur due to a layout restriction based on positional information of each wiring on a chip of the CMOS integrated circuit and correspondence information of each wiring of a gate level circuit of the CMOS integrated circuit. 9. The failure diagnosis method according to claim 8, further comprising a step of selecting a certain failure occurrence location, wherein only the failure at the failure occurrence location is diagnosed as a failure candidate. 10. The step of selecting a fault occurrence location includes selecting at least one of a location where wirings are close to each other and a location where the wirings intersect on the chip of the CMOS integrated circuit as the failure occurrence location. 10. The failure diagnosis method according to claim 9, wherein: 11. The CMOS according to the short-circuit fault estimated in the fifth step, position information of each wiring on a chip of the CMOS integrated circuit, and correspondence information of each wiring of a gate level circuit of the CMOS integrated circuit. The failure diagnosis method according to any one of claims 8 to 10, further comprising a step of identifying a place where a failure has actually occurred on a chip of the integrated circuit. 12. The fault diagnosis according to claim 8, further comprising the step of removing a fault having a low possibility of being present among the short-circuit faults estimated in the fifth step. Method. 13. The method according to claim 1, wherein the step of removing a fault having a low possibility of occurrence includes removing a short-circuit fault having a large number of simultaneously occurring faults as the fault having a low possibility of occurrence. 12. The failure diagnosis method according to item 12.