JP3372488B2 - Test device for semiconductor CMOS integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for easily and rationally determining the quality of a semiconductor CMOS integrated circuit.

[0002]

2. Description of the Related Art An IDDQ test is known as a test method for improving the quality of a semiconductor CMOS integrated circuit.

The IDDQ test is a method in which a test pattern is sequentially input to a device under test (hereinafter referred to as "DUT"), an internal logic state is set to a steady state, and a quiescent power supply current is measured. This is a test method utilizing the fact that the static power supply current of a CMOS integrated circuit is theoretically zero.

If a leak current occurs even if the stationary power supply current is originally zero due to a stuck-at fault or a breakdown voltage failure in the DUT internal circuit, the DUT can be determined as a defective product. However, the leak current measured and detected by this method is
Small current (μA) mainly caused by internal circuit failure
Degree or less).

On the other hand, in the case of a circuit having a current path (hereinafter referred to as “DC path”) in which devices such as pull-up / down resistors and analog circuits exist in a static state, a through current generated from the DC path is DC. Some pass 1 mA per pass. Therefore, in the case of a circuit having a DC path, the leak current caused by the failure of the circuit to be originally detected is buried under the influence of the through current, and it is difficult to determine whether or not the static current consumption has increased.

As a conventional technique for solving the above problems, there are the following methods.

A typical DC path of a semiconductor CMOS integrated circuit has an input pull-up resistor, but when the input voltage is at a low level, D from the power supply terminal to the input terminal is used.
A through current flows due to the C path. When performing the IDDQ test, as a method of avoiding the influence of the through current flowing from the power supply by the pull-up resistor, for example, a method of adding a test circuit for separating the input pull-up resistor to cut off the bypass by the resistor from the power supply, , There is a method of creating a test pattern in which a potential difference does not occur between a power supply voltage and an input so that a pull-up current does not flow (Japanese Patent Laid-Open No. 9-113).
575).

Alternatively, there is a method in which the through current of the DC path is previously measured and stored, or a prediction is made by simulation or the like, and the result is subjected to arithmetic processing to make a determination (Japanese Patent Laid-Open No. 7-12886). (See Japanese Patent Laid-Open No. 9-80114), the IDDQ test cannot be easily performed as compared with the case where there is no DC path.

[0009]

Even in a semiconductor CMOS integrated circuit having a DC path, such as an input pull-up resistor, D
IDDQ test circuit that cuts off the C path
There is a method of incorporating the OS integrated circuit in the same chip and avoiding the through current of the DC path before the IDDQ test, but there is a problem that the chip size increases and the cost increases.

Further, the pass / fail judgment test is possible by subtracting the through current of the DC path predicted by the arithmetic processing from the static current consumption measured by the IDDQ test, but the through current is pseudo. And between the actual measured DUT through current and the predicted through current, DU
Differences occur depending on the characteristic state of T.

Further, even when there are a plurality of DC paths of the same type, there is a slight difference in the current value depending on the individual DC paths, and it is difficult to accurately predict the through current. Therefore, it is necessary to predict a through-current value with a margin in consideration of fluctuations in characteristics. Therefore, the IDDQ test that makes a determination with a minute current value lacks reliability. Of course, the same applies to the case where the through-current of the DUT is measured in advance and the reference through-current value is stored and subtracted, and the reference through-current is corrected or the current value after the through-current is subtracted It is necessary to give some margin to the judgment allowable value. Further, there is a problem that the test time for the arithmetic processing becomes long.

In addition, if the DC path cannot be separated by an IDDQ test circuit or the like, there is also a method of setting the judgment value in a state in which the through current of the DC path is added.
Normally, the through current of the DC path was about 100 times the current consumption in the static state measured by the IDDQ test, and the pass / fail judgment test of the minute current value was out of the question. In order to improve the quality in this way, a great deal of labor and a certain degree of compromise were required before the final quality judgment.

[0013]

A semiconductor according to claim 1, wherein:
The method of testing a CMOS integrated circuit is a semiconductor CMOS integrated circuit.
Measures the power supply current when the road is at rest and integrates the semiconductor CMOS
Test each circuit input with specified voltage and timing
Simultaneously measure the input current while giving a pattern, and
Input current input to each input part of the conductor CMOS integrated circuit
Add the measurement results and add
The addition value of each measured input current is subtracted, and the subtraction result
Is compared with a preset value to make a determination.
It is a thing.

A semiconductor CMOS device according to a second aspect of the present invention.
The product circuit tester is used when the semiconductor CMOS integrated circuit is stationary.
Power supply current is measured and each of the above semiconductor CMOS integrated circuits is turned on.
Apply a test pattern to the input section according to the specified voltage and timing.
Simultaneously measure the input current while giving the
The input current measurement result input to each input part of the S integrated circuit
Add and measure from the above measured power supply current value to the above
The added value of each input current is subtracted, and the subtraction result is set in advance.
It is characterized by comparing and determining with a set value.
It The semiconductor CMOS integrated circuit according to claim 3
The test equipment is the static power supply current of the semiconductor CMOS integrated circuit.
Power supply current measuring circuit for measuring
Test each input section of the product circuit with specified voltage and timing.
Input that simultaneously measures the input current while applying the
Current measuring circuit and each input of the semiconductor CMOS integrated circuit
Circuit that adds the input current measurement results input to the section
And the power supply current value measured by the above power supply current measurement circuit
From the measured input current calculated by the adder circuit,
A subtraction circuit for subtracting the addition value and the subtraction result are set in advance.
And a comparison / determination circuit for determining and comparing the determined value
It is characterized by. According to a fourth aspect of the present invention, there is provided a semiconductor CMOS integrated circuit testing apparatus, wherein the input current measuring circuit supplies a specified voltage to each input section of the semiconductor CMOS integrated circuit.
The test apparatus for a semiconductor CMOS integrated circuit according to claim 3 , wherein a test pattern for a function test is given at a timing .

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, based on one embodiment,
The present invention will be described in detail.

FIG. 1 shows a semiconductor C according to an embodiment of the present invention.
FIG. 4 is a block diagram of a MOS integrated circuit test device, and FIG. 4 is a block diagram of a second high-precision current measuring device. 1 and 4, in FIG.
Reference numeral 00 is a power supply circuit, 101 is a first high-precision current measuring device for measuring a power supply current at rest by setting an internal logic state to a steady state, 102 is a device under test of a semiconductor CMOS integrated circuit having a DC path, and 103 is a high Precision current measurement circuit, 10
3a _{1 to} 103a _N are second high-precision current measuring devices, 104 ₁
~ 104 _N is a driver circuit, 105 is an arithmetic circuit, 105
a adder, 105b subtracter, 106 comparator / judging circuit, 107 ₁ to 107 _N are comparator circuits.

The configuration of the embodiment of the present invention will be described below with reference to FIG.

First, the power source (V) is supplied to the power source terminal (VDD) of the device under test (DUT) 102 through the first high-precision current measuring device 101 for measuring the power supply current at rest and converting the voltage.
S) Apply a specified power supply voltage from 100, while DUT
Driver circuits to the input terminals of the 102 ((DR), this time the pattern generator, a timing generator, a waveform shaping circuit or the like is omitted from illustration) from 104 ₁ -104 _N, accurate current measurement for each input terminal A plurality of second high-accuracy current measuring devices 103a ₁ , 103a ₂ , ... 103 forming the circuit 103.
A test pattern is applied via a _N at a specified voltage and timing to bring the internal logic of the DUT 102 into a steady state, and a quiescent power supply current including a through current of the DC path flows.

The output from each of the second high-precision current measuring devices 103a _{1 to} 103a _{N of} the high-precision current measuring circuit 103 is connected to the input part of the adder 105a, and the first high-precision current measuring device 101 is connected. And the output of the adder 105a are connected to the input of the subtractor 105b. The arithmetic unit 105 includes an adder 105a and a subtractor 105b.

Further, the output part of the subtractor 105b is connected to the input part of the comparator of the comparison / judgment circuit 106, and the judgment reference voltage is compared with the output of the subtractor 105b. Further, by using the test pattern for the function test as the test pattern given from the input terminal of the DUT 102 by the driver 104, the output operation result is compared with the comparators (COMP) 107 _{1 to} 107 _N for each specified set address.
By observing at, the functional test can be performed at the same time.

Next, the detailed operation of the present invention will be described with reference to the timing charts of FIGS.

FIG. 2 shows the operation when a non-defective DUT is tested. A specified power supply voltage is applied to the DUT 102 from the power supply 100, and a functional test is performed from the driver 104 to each input terminal at a specified voltage and timing. Test patterns are given. Thereby, for example, the stationary power supply current including the input current of A (through current of the DC path) like the address 11 is measured by the first high-precision current measuring device 101.

Further, the flow (through current DC path) input current to the input terminals, the input current flowing to the input terminals is measured at the second precision current measuring device 103a ₁ ~103a _N. The current of A ′ (voltage converted), which is the sum of the respective input currents, is added by the adder 105a of the arithmetic circuit 105.
And subtracting the total input current A ′ from the stationary power supply current including the total input current (sum of through currents in the DC path) by the subtractor 105b, thereby obtaining the net stationary power supply current.

Power supply current value at rest (converted to voltage)
Can be compared with a predetermined judgment reference value set in advance in the comparison / judgment circuit 106 to make a pass / fail judgment.

FIG. 3 is a timing chart for testing a defective DUT under the same measurement conditions as in FIG. For example,
When the quiescent power supply current including the leakage current C due to a failure is measured separately from the total input current B like the address 13,
By subtracting the total input current B'in the subtractor 105,
The leak current C ′ due to the failure is obtained, and since it exceeds the specified determination reference value, it is determined as a defective product.

[0026]

As described above in detail, according to the present invention, the IDD can be applied to a semiconductor CMOS integrated circuit having a DC path.
It is controlled in advance by a Q test circuit, etc., and I
Since the DDQ test can be performed, it is not necessary to add an IDDQ test circuit, and an increase in chip area can be prevented.

Further, the through current of the DC path is measured for each measurement address, and the through current is added or subtracted as it is to I
Since it is possible to perform a DDQ test, it is not necessary to measure or predict the shoot-through current value of the DC path in advance, store it in the memory circuit of the test equipment, and perform arithmetic processing. There is no need to consider unevenness.

Further, since the logic of the internal circuit is set to the steady state by using the test pattern for function test, the function test can be performed at the same time as the IDDQ test, and the test time can be shortened. In addition, since the test pattern for functional test is used without using the test pattern for IDDQ test (test mode, that is, the operation different from the actual use state), the test can be performed under the operating condition close to the actual use mode.

Therefore, the present invention is effective not only in easiness of quality judgment of the semiconductor CMOS integrated circuit but also in improvement of shipping quality, improvement of development efficiency and cost reduction.

[Brief description of drawings]

FIG. 1 is a semiconductor CMOS showing an embodiment of the present invention.
It is a block diagram of the testing device of an integrated circuit.

FIG. 2 is a timing chart diagram showing the progress when a non-defective semiconductor CMOS integrated circuit is tested using the semiconductor CMOS integrated circuit test apparatus of the present invention.

FIG. 3 is a timing chart diagram showing the progress when a defective semiconductor CMOS integrated circuit is tested using the semiconductor CMOS integrated circuit testing apparatus of the present invention.

FIG. 4 is a configuration diagram of a second high-precision current measuring device.

[Explanation of symbols]

100 Power Circuit 101 First High-Precision Current Measuring Device 102 Device Under Test 103 High-Precision Current Measuring Circuit 103a _{1 to} 103a _N Second High-Precision Current Measuring Device 104 _{1 to} 104 _N Driver Circuit 105 Arithmetic Circuit 105a Adder 105b Subtractor Comparator / Determination circuit 107 _{1 to} 107 _N Comparator circuit

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Claims (4)

(57) [Claims] 1. A quiescent power supply for a semiconductor CMOS integrated circuit.
Current is measured, and a specified voltage is applied to each input section of the semiconductor CMOS integrated circuit.
Input at the same time while giving a test pattern according to the timing.
The force current is measured and the input current input to each input section of the semiconductor CMOS integrated circuit is input.
Force current measurement results are added, and from the measured power supply current value, each input measured above
The addition value of the current is subtracted, and the subtraction result is compared with a preset value.
A method for testing a semiconductor CMOS integrated circuit, which is characterized. 2. A quiescent power supply for a semiconductor CMOS integrated circuit.
Current is measured, and a specified voltage is applied to each input section of the semiconductor CMOS integrated circuit.
Input at the same time while giving a test pattern according to the timing.
The force current is measured and the input current input to each input section of the semiconductor CMOS integrated circuit is input.
Force current measurement results are added, and from the measured power supply current value, each input measured above
The addition value of the current is subtracted, and the subtraction result is compared with a preset value.
A testing device for a semiconductor CMOS integrated circuit, which is characterized. 3. A power supply current measuring circuit for measuring a static power supply current of a semiconductor CMOS integrated circuit, and a voltage specified for each input section of the semiconductor CMOS integrated circuit.
An input current measurement circuit that simultaneously measures an input current while giving a test pattern according to timing, an addition circuit that adds the input current measurement results input to each input section of the semiconductor CMOS integrated circuit, and a power supply current measurement circuit A subtraction circuit for subtracting the addition value of each measured input current calculated by the addition circuit from the calculated power supply current value, and a comparison / determination circuit for comparing and comparing the subtraction result with a preset value. Characteristic semiconductor CMOS
Integrated circuit test equipment. 4. The input current measuring circuit is a semiconductor CMOS.
Specified in the respective input of the integrated circuit voltage and the machine by the timing
The test apparatus for a semiconductor CMOS integrated circuit according to claim 3 , wherein a test pattern for performance test is provided.