JP2004257815A - Inspection method of semiconductor integrated circuit and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for failure analysis of a semiconductor integrated circuit enabling an IDDQ test even in a greatly miniaturized process. <P>SOLUTION: An LSI 1 is equipped with a signal input/output terminal 2, a power source potential supply terminal 3, a ground potential supply terminal 4, a substrate potential supply terminal 5 of an Nch transistor, and a substrate potential supply terminal 6 of a Pch transistor. The LSI 1 is inspected by an external current inspection circuit 200 at the IDDQ test time. A determination result on whether a value determined by subtracting the current flowing in substrate potential supply wiring 9 of the Pch transistor and in substrate potential supply wiring 10 of the Nch transistor from the current flowing in power source potential supply wiring 7 is higher or lower than a prescribed determination standard current value recorded in the power source current inspection circuit 200 is outputted by an inspection determination signal. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to fault detection of a CMOS integrated circuit, and more particularly to a CMOS integrated circuit suitable for an inspection method using a quiescent power supply current in a fine process and an inspection method thereof.
[0002]
[Prior art]
As a method of analyzing a failure of a CMOS integrated circuit, there is an IDDQ test (Quiescent Current Testing). This is to measure a power supply current (hereinafter, IDDQ) flowing when the CMOS integrated circuit is at rest and detect the presence or absence of a defect based on the magnitude of the measured current value (for example, Non-Patent Document 1). As shown in FIG. 1, in the IDDQ test, a power supply current inspection circuit is connected to the power supply VDD of the LSI, and the power supply current flowing through the power supply VDD is monitored. At this time, the LSI is in a quiescent state and only a small quiescent current flows. The measurement is performed for each sample, and is compared with the current value serving as a failure determination line. For a non-defective sample, the measured IDDQ is lower than the defective determination line current value, and for a defective sample, the measured IDDQ exceeds the defective determination line current value. By measuring the IDDQ in this way, a defect can be detected. The IDDQ test is an important method as a failure analysis of a CMOS integrated circuit that can detect a failure that cannot be detected by a function test for testing an operation state and has a high failure detection rate.
[0003]
With recent miniaturization of process technology, an off-leak current flowing when a transistor is turned off is increasing. This increase in off-leak current means an increase in IDDQ. As a result, the current that normally flows during the IDDQ test increases, and the current that flows when a failure occurs is buried in the current, making it impossible to detect a failure.
[0004]
As a technique for reducing the increased off-leak current and enabling the IDDQ test, there is a VT-CMOS technique for applying a reverse bias to a transistor substrate. In a normal CMOS circuit, the substrate of the Nch transistor is connected to the ground VSS, and the substrate of the Pch transistor is connected to the power supply VDD. As shown in FIG. 2, the VT-CMOS circuit has a configuration in which the substrate potentials of the Nch and Pch transistors can be controlled independently of the power supply VDD and the ground VSS. FIG. 3 shows a VT-CMOS transistor structure. The substrate potentials PWVSS and NWVDD of the Nch and Pch transistors are drawn separately from the power supply VDD and the ground VSS. At this time, a triple substrate structure is generally adopted as the device structure of the transistor. Off-leak current can be reduced by applying a reverse bias to the substrate. By utilizing this fact, a reverse bias is applied to the substrate of the Nch and Pch transistors in the stationary state to reduce the off-leakage current, thereby reducing the IDDQ flowing in the LSI and enabling the IDDQ test.
[0005]
[Non-patent document 1]
ROCHIT RAJSUMAN, "Iddq Testing for CMOS VLSI", PROCEEDINGS OF THE IEEE, VOL. 88, NO. 4, APRIL 2000, P544-566
[0006]
[Problems to be solved by the invention]
However, in the case of a fine process of 0.10 μm or less, failure detection cannot be performed even by an IDDQ test using VT-CMOS technology. Up to the 0.13 μm process generation, only an increase in the drain leakage current is a problem in the IDDQ test, and this problem can be solved by using VT-CMOS. However, after the 0.10 μm process generation, the gate leak current and the junction leak current increase in addition to the drain leak current.
[0007]
FIG. 4 is a diagram showing a leak current component flowing through the transistor. The drain leak current I_DL flows from the drain to the source when the transistor is off. The gate leak current I_GL flows between the gate and the substrate immediately below the gate or between the source and the drain when a potential difference is generated between them. Further, the junction leak current I_JL flows between the drain and the source and the substrate when a potential difference occurs between them.
[0008]
The gate leak current I_GL and the junction leak current I_JL increase due to miniaturization even in a normal CMOS, but when a reverse bias is applied to the transistor substrate using VT-CMOS to reduce the off leak current, the gate leak current I_GL and the junction are reduced. Leak current I_JL will further increase. FIG. 5 shows changes in leak components of Nch and Pch transistors when a substrate bias is applied and when no substrate bias is applied. By applying a reverse bias to the transistor substrate, the gate leak current I_GL and the junction leak current I_JL increase or newly occur. As described above, when the reverse bias is applied, the drain leak current I_DL can be reduced, but the gate leak current I_GL and the junction leak current I_JL increase.
[0009]
Until now, only the drain leak current has to be considered for the IDDQ test, and the VT-CMOS technology has solved the problem. However, after the 0.10 μm process generation, the use of VT-CMOS increases the other leak components such as the gate leak current and the junction leak current, and consequently makes the IDDQ test impossible.
[0010]
[Means for Solving the Problems]
A method for testing a semiconductor integrated circuit according to the present invention includes steps (a) to (c). In step (a), predetermined potentials are respectively applied to a power supply potential supply terminal, a ground potential supply terminal, a substrate potential supply terminal of an internal Nch transistor, and a substrate potential supply terminal of an internal Pch transistor of the semiconductor integrated circuit. In step (b), currents flowing through the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Nch transistor, and the substrate potential supply terminal of the internal Pch transistor are measured. In step (c), a current value (IDDQ value) obtained by subtracting a current flowing to the substrate potential supply terminal of the internal Nch transistor and a current flowing to the substrate potential supply terminal of the internal Pch transistor from the current flowing to the power supply potential supply terminal is calculated. calculate.
[0011]
Preferably, in the step (a), a reverse bias is applied to the substrate potential supply terminal of the internal Nch transistor and the substrate potential supply terminal of the internal Pch transistor. Specifically, a potential lower than the ground potential is applied to the substrate potential supply terminal of the internal Nch transistor, and a potential higher than the power supply potential is applied to the substrate potential supply terminal of the internal Pch transistor.
[0012]
Preferably, the inspection method further includes a step (d). In the step (d), the IDDQ value calculated in the step (c) is compared with a predetermined reference value, and based on the comparison result, a good / defective product of the semiconductor integrated circuit is determined.
[0013]
Preferably, the semiconductor integrated circuit has a plurality of power supply potential supply terminals, a plurality of ground potential supply terminals, a plurality of substrate potential supply terminals of internal Nch transistors, and a plurality of substrate potential supply terminals of internal Pch transistors. In the above step (a), predetermined power supply potential supply terminals of the semiconductor integrated circuit, a plurality of ground potential supply terminals, a plurality of substrate potential supply terminals of the internal Nch transistor, and a plurality of substrate potential supply terminals of the internal Pch transistor are respectively predetermined. Apply potential. In the step (b), currents flowing through the plurality of power supply potential supply terminals, the plurality of ground potential supply terminals, the plurality of substrate potential supply terminals of the internal Nch transistor, and the plurality of substrate potential supply terminals of the internal Pch transistor are measured. The step (c) is obtained by subtracting a current flowing through the plurality of substrate potential supply terminals of the internal Nch transistor and a current flowing through the plurality of substrate potential supply terminals of the internal Pch transistor from the current flowing through the plurality of power supply potential supply terminals. The current value (IDDQ value) is calculated.
[0014]
Preferably, the semiconductor integrated circuit includes a plurality of circuit blocks. In the step (a), predetermined potentials are respectively applied to the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Nch transistor, and the substrate potential supply terminal of the internal Pch transistor of each of the plurality of circuit blocks. In the step (b), the current flowing through each of the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Nch transistor, and the substrate potential supply terminal of the internal Pch transistor of each of the plurality of circuit blocks is measured. In the step (c), for each of the plurality of circuit blocks, a current flowing to the substrate potential supply terminal of the internal Nch transistor and a current flowing to the substrate potential supply terminal of the internal Pch transistor are subtracted from the current flowing to the power supply potential supply terminal. The obtained current value (IDDQ value) is calculated.
[0015]
Preferably, in the step (a), a potential at which the off-leak current of the transistor is minimized is applied to the substrate potential supply terminal of the internal Nch transistor and the substrate potential supply terminal of the internal Pch transistor.
[0016]
Preferably, the steps (a) to (c) are performed by setting the potential applied to the power supply potential supply terminal to a first potential, and then the step (a) is performed by setting the potential applied to the power supply potential supply terminal to a second potential. ) To (c) are performed.
[0017]
Preferably, the steps (a) to (c) are performed with the ambient temperature of the semiconductor integrated circuit as a first temperature, and then the steps (a) to (c) are performed with the ambient temperature of the semiconductor integrated circuit as a second temperature. Perform (c).
[0018]
Preferably, the inspection method further includes a step (d). In the step (d), the time change of the value of the current flowing to the power supply terminal is monitored.
[0019]
A semiconductor integrated circuit device according to the present invention includes a first circuit block and a first current test circuit. The first circuit block includes a first power supply potential supply terminal, a first ground potential supply terminal, a first substrate potential supply terminal of an internal Nch transistor, and a first substrate potential supply terminal of an internal Pch transistor. including. The first current test circuit includes means (a) to (c). The means (a) includes predetermined potentials at a first power supply potential supply terminal, a first ground potential supply terminal, a first substrate potential supply terminal of an internal Nch transistor, and a first substrate potential supply terminal of an internal Pch transistor, respectively. give. The means (b) is configured to supply currents flowing through a first power supply potential supply terminal, a first ground potential supply terminal, a first substrate potential supply terminal of an internal Nch transistor, and a first substrate potential supply terminal of an internal Pch transistor, respectively. Measure. The means (c) subtracts the current flowing to the first substrate potential supply terminal of the internal Nch transistor and the current flowing to the first substrate potential supply terminal of the internal Pch transistor from the current flowing to the first power supply potential supply terminal. The obtained current value (IDDQ value) is calculated.
[0020]
Preferably, the means (a) applies a reverse bias to the first substrate potential supply terminal of the internal Nch transistor and the first substrate potential supply terminal of the internal Pch transistor. Specifically, a potential lower than the ground potential is applied to the first substrate potential supply terminal of the internal Nch transistor, and a potential higher than the power supply potential is applied to the first substrate potential supply terminal of the internal Pch transistor.
[0021]
Preferably, the first current test circuit further includes means (d). The means (d) compares the IDDQ value calculated by the means (c) with a predetermined reference value, and determines good / bad of the first circuit block based on the comparison result.
[0022]
Preferably, the semiconductor integrated circuit device further includes a second current test circuit and a test determination circuit. The first circuit block includes a second power supply potential supply terminal, a second ground potential supply terminal, a second substrate potential supply terminal of an internal Nch transistor, and a second substrate potential supply terminal of an internal Pch transistor. And further. The second current test circuit includes means (d) to (f). Means (d) include predetermined potentials at a second power supply potential supply terminal, a second ground potential supply terminal, a second substrate potential supply terminal of an internal Nch transistor, and a second substrate potential supply terminal of an internal Pch transistor, respectively. give. The means (e) includes a current flowing through a second power supply potential supply terminal, a second ground potential supply terminal, a second substrate potential supply terminal of an internal Nch transistor, and a second substrate potential supply terminal of an internal Pch transistor. Measure. The means (f) subtracts a current flowing to the second substrate potential supply terminal of the internal Nch transistor and a current flowing to the second substrate potential supply terminal of the internal Pch transistor from the current flowing to the second power supply potential supply terminal. The obtained current value (IDDQ value) is calculated. The inspection determination circuit compares the IDDQ value obtained by the first current determination circuit and the second current determination circuit with a predetermined reference value, and determines whether the first circuit block is good or defective based on the comparison result. I do.
[0023]
Preferably, the semiconductor integrated circuit device further includes a second circuit block, a second current test circuit, and a test determination circuit. The second circuit block includes a power supply potential supply terminal, a ground potential supply terminal, a substrate potential supply terminal of an internal Nch transistor, and a substrate potential supply terminal of an internal Pch transistor. The second current test circuit includes means (d) to (f). The means (d) applies predetermined potentials to the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Nch transistor, and the substrate potential supply terminal of the internal Pch transistor of the second circuit block. The means (e) measures currents flowing through the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Nch transistor, and the substrate potential supply terminal of the internal Pch transistor of the second circuit block. The means (f) includes: a current flowing from a power supply potential supply terminal of the second circuit block to a current flowing to a substrate potential supply terminal of an internal Nch transistor of the second circuit block; and a substrate potential of an internal Pch transistor of the second circuit block. A current value (IDDQ value) obtained by subtracting the current flowing through the supply terminal is calculated. The inspection determination circuit determines pass / fail of the first circuit block based on a comparison result between the IDDQ value obtained by the first current determination circuit and a predetermined reference value, and obtains the result by the second current determination circuit. The pass / fail of the second circuit block is determined based on a comparison result between the obtained IDDQ value and a predetermined reference value.
[0024]
Preferably, the semiconductor integrated circuit device further includes a second circuit block and a switch circuit. The second circuit block includes a first power supply potential supply terminal, a first ground potential supply terminal, a first substrate potential supply terminal of an internal Nch transistor, and a first substrate potential supply terminal of an internal Pch transistor. including. The means (a) of the first current inspection circuit includes a first power supply potential supply terminal, a first ground potential supply terminal, and a first substrate potential of the internal Nch transistor of the first circuit block or the second circuit block. A predetermined potential is applied to each of the supply terminal and the first substrate potential supply terminal of the internal Pch transistor. The switch circuit controls on / off of potential supply from the first current test circuit to the first circuit block or the second circuit block.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.
[0026]
(1st Embodiment)
FIG. 6 shows a schematic configuration of the semiconductor inspection device according to the first embodiment. This inspection apparatus is an apparatus for performing an IDDQ test of LSI1.
[0027]
The LSI 1 to be inspected includes a signal input / output terminal 2, a power supply potential supply terminal 3, a ground potential supply terminal 4, a substrate potential supply terminal of a Pch transistor 5, and a substrate potential supply terminal 6 of an Nch transistor. The signal input / output terminal 2 is a terminal for inputting a signal to an internal circuit of the LSI 1 and outputting a signal from the internal circuit of the LSI 1. The power supply potential supply terminal 3 is a terminal for supplying the power supply potential VDD to the internal circuit of the LSI 1. The ground potential supply terminal 4 is a terminal for supplying the ground potential VSS to the internal circuit of the LSI 1. The substrate potential supply terminal 5 of the Pch transistor is a terminal for supplying the substrate potential NWVDD to the Pch transistor inside the LSI 1. The substrate potential supply terminal 6 of the Nch transistor is a terminal for supplying the substrate potential PWVSS to the Nch transistor inside the LSI 1.
[0028]
The power supply potential VDD and the ground potential VSS are supplied from the potential supply circuit 100 to the current inspection circuit 200. The power supply potential supply line 7, the ground potential supply line 8, the substrate potential supply line 9 for the Pch transistor, and the substrate potential supply line 10 for the Nch transistor come out of the current inspection circuit 200. The power supply potential supply line 7 supplies the power supply potential. The terminal 3, the ground potential supply line 8 is connected to the ground potential supply terminal 4, the Pch transistor substrate potential supply line 9 is connected to the Pch transistor substrate potential supply terminal 5, and the Nch transistor substrate potential supply line 10 is connected to the Nch transistor substrate potential. It is connected to the supply terminal 6 and supplies each potential to the LSI 1.
[0029]
The current flowing through the power supply potential supply wiring 7, the ground potential supply wiring 8, the substrate potential supply wiring 9 of the Pch transistor, and the substrate potential supply wiring 10 of the Nch transistor is measured by the current inspection circuit 200, and the current flowing through the power supply potential supply wiring 7 The value obtained by subtracting the current flowing through the substrate potential supply wiring 9 of the Pch transistor and the current flowing through the substrate potential supply wiring 10 of the Nch transistor exceeds a predetermined reference current value recorded in the power supply current inspection circuit 200? The result of the determination is output as an inspection determination signal. Although the judgment reference current value is recorded in the power supply inspection circuit 200, an arbitrary value can be input from the outside.
[0030]
FIG. 7 shows the internal configuration of the current inspection circuit 200. The current inspection circuit 200 includes regulators 201 to 202, current monitoring circuits 203 to 206, and a current value determination circuit 207.
[0031]
The regulator 201 generates the potentials VDD and NWVDD based on the power supply potential VDD from the potential supply circuit 100 and a control signal from the monitor device 300. Here, the generated potential VDD is equal to the power supply potential VDD supplied from the potential supply circuit 100, and the potential NWVDD is higher than the power supply potential VDD supplied from the potential supply circuit 100 (NWVDD = VDD + α). The generated potential VDD is supplied to the power supply potential supply line 7 as a power supply potential, and the potential NWVDD is supplied to the substrate potential supply line 9 of the Pch transistor as the substrate potential of the Pch transistor.
[0032]
The regulator 202 generates the potentials VSS and PWVSS based on the ground potential VSS from the potential supply circuit 100 and a control signal from the monitor device 300. Here, the generated potential VSS is equal to the ground potential VSS given from the potential supply circuit 100, and the potential PWVSS is lower than the ground potential VSS given from the potential supply circuit 100 (PWVSS = VSS-α). . The generated potential VSS is supplied to the ground potential supply wiring 8 as a ground potential, and the potential PWVSS is supplied to the substrate potential supply wiring 10 of the Nch transistor as the substrate potential of the Nch transistor.
[0033]
It is desirable that the potential NWVDD applied to the substrate potential supply line 9 of the Pch transistor and the potential PWVSS applied to the substrate potential supply line 10 of the Nch transistor be determined as follows. The VBS dependence of IDDQ is examined for a certain transistor array. As shown in FIG. 8, when the substrate potential VBS is applied and the potential is raised, the drain leak current decreases, but the junction leak current and the gate leak current increase. As a result, IDDQ takes a minimum value at a point of a certain VBS potential, and increases before and after. By applying the potential at point A in the figure as VBS, the IDDQ value can be minimized, and defect detection can be facilitated.
[0034]
The current monitor circuit 203 measures a value of a current flowing through the power supply potential supply wiring 7 and outputs a signal I_VDD indicating the current value. The current monitor circuit 204 measures a current value flowing through the ground potential supply wiring 8, and outputs a signal I_VSS indicating the current value. The current monitor circuit 205 measures a current value flowing through the substrate potential supply wiring 9 of the Pch transistor, and outputs a signal I_NWVDD indicating the current value. The current monitor circuit 206 measures a current value flowing through the substrate potential supply wiring 10 of the Nch transistor, and outputs a signal I_PWVSS indicating the current value.
[0035]
The current value determination circuit 207 determines, as an inspection determination signal, a determination result as to whether a value IDDQ (= I_VDD-I_NWVDD-I_PWVSS) obtained by subtracting the signal I_NWVDD and the signal I_PWVSS from the signal I_VDD is higher or lower than a predetermined determination reference current value. Output.
[0036]
The signals I_VDD, I_VSS, I_NWVDD, and I_PWVSS from the current monitoring circuits 203 to 206 are also supplied to the monitor device 300.
[0037]
FIG. 9 is a diagram for explaining the principle of the present invention. The L level is input to the CMOS inverter inside the LSI 1 and the H level is output. At this time, the Pch transistor 25 is ON, and the Nch transistor 26 is OFF. When monitoring the current IDD_OFF flowing to the power supply potential 19 in the stationary state, if there is a failure circuit 39, the leakage current component I_LEAK due to the failure is included in IDD_OFF. Causes of the failure of the failure circuit 39 include a wiring short circuit, Tr destruction, and the like. At this time, in order to reduce the drain leak current I_DL, a reverse bias is applied to the substrate. Therefore, the gate leak current I_GL and the junction leak current I_JL increase. Since the increased I_GL and I_JL flow to the substrate of the Nch transistor 26, the current value can be determined by monitoring the current of the substrate potential supply wiring 22 of the Nch transistor. IDD_OFF is the sum of I_DL, I_GL, I_JL, and I_LEAK. As shown in Equation 1 below, by subtracting the steady-state leak current component, it is possible to confirm whether or not a fault current has occurred, and thus to determine whether or not there is a fault.
[0038]
I_LEAK = IDD_OFF- (I_DL + I_GL + I_JL) (Equation 1)
The current flowing through the substrate (hereinafter, I_WELL) is the sum of I_GL and I_JL, but I_DL can be made almost negligible by applying a reverse bias to the substrate. At this time, Equation 1 can be approximated as I_LEAK ≒ IDD_OFF- (I_GL + I_JL). In this embodiment, the current flowing through the power supply potential supply wiring 7 is measured as IDD_OFF, and the sum of the current flowing through the substrate potential supply wiring 9 of the Pch transistor and the current flowing through the substrate potential supply wiring 10 of the Nch transistor is defined as (I_GL + I_JL). Measuring.
[0039]
FIG. 10 is a diagram showing an inspection method according to the present invention. In FIG. 10A, the static power supply current is evaluated for each sample. Since the steady leak current component is large, it is impossible to determine whether or not there is a failure. FIG. 10B shows a result obtained by subtracting I_WELL from IDD_OFF. Since a steady leak current can be reduced, an abnormal current in the case of a faulty circuit can be detected, and it is determined whether or not there is a fault. be able to. FIG. 10C shows the dependence of I_WELL on the substrate bias, and it is considered that the type of the failure can be determined by checking this characteristic. This confirmation is performed by the monitor device 300. The potential NWVDD applied to the substrate potential supply line 9 of the Pch transistor and the potential PWVSS applied to the substrate potential supply line 10 of the Nch transistor are changed by a control signal applied from the monitor device 300 to the regulators 201 and 202 of the current inspection circuit 300. Do it.
[0040]
<VDD dependency of IDDQ>
In this embodiment, the VDD dependency of the IDDQ can be checked by the monitor device 300. The potential VDD supplied to the power supply line 7 is changed by a control signal supplied from the monitor device 300 to the regulators 201 and 202 of the current inspection circuit 300, and the IDDQ value at that time is monitored. The cause of the failure can be specified by evaluating the VDD dependency of the IDDQ. In general, a fault in a wiring short circuit has little dependency on VDD, a gate leak current is proportional to the square of VDD, and a drain leak current and a junction leak current are exponentially proportional to VDD. Based on these characteristics, it can be estimated that (1) in FIG. 11 is a wiring short-circuit failure, (2) is a failure related to a gate leak current, and (3) is a failure related to a drain leak current or a junction leak current. As described above, by taking the VDD dependency of the IDDQ, it is possible to easily identify the cause of the failure.
[0041]
<Temperature dependence of IDDQ>
Further, the temperature dependency of the IDDQ can be checked by the monitor device 300. The ambient temperature of the LSI 1 is changed, and the IDDQ value at that time is monitored. By evaluating the temperature dependency of the IDDQ, the cause of the failure can be specified. In general, the IDDQ increases as the temperature rises in a wiring short-circuit failure. The gate leak current has almost no dependence on temperature, and the drain leak current increases exponentially as the temperature rises. From this, it can be estimated that (1) in FIG. 12 is a wiring short-circuit failure and (2) is a failure related to drain leakage current. As described above, by determining the temperature dependency of the IDDQ, it is possible to easily identify the cause of the failure.
[0042]
<Monitoring of time change of IDDQ>
Further, the time change of the IDDQ can be checked by the monitor device 300. The IDDQ is changed over time and monitored, and the cause of the failure is specified by the change of the IDDQ. Generally, when a floating node is present in a circuit due to a short circuit or an open circuit, a through current flows in the circuit. This floating node stabilizes at a specific potential over time. As a result, the through current decreases with time, and as a result, the IDDQ decreases. Since {circle around (1)} in FIG. 13 has no time dependency, it can be seen that there is no failure due to the existence of the floating node. In (2), since the IDDQ decreases with the elapse of time, it can be seen that the floating node exists and is defective. As described above, by monitoring the time change of the IDDQ and evaluating the difference in the behavior, it is possible to easily identify the cause of the failure.
[0043]
(Second embodiment)
FIG. 14 is a diagram showing a semiconductor integrated circuit (LSI 1) according to the second embodiment. The current inspection circuit 200 provided outside the LSI 1 in the first embodiment is provided inside the LSI 1 and connected to the internal circuit block 40. The regulator 201 of the current test circuit 200 applies the potential VDD to the power supply potential supply terminal of the circuit block 40 and the potential NWVDD to the substrate potential supply terminal of the internal Pch transistor. The regulator 202 supplies the potential VSS to the ground potential supply terminal of the circuit block 40, and supplies the potential PWVSS to the substrate potential supply terminal of the internal Nch transistor. The current monitoring circuits 203 to 206 of the current inspection circuit measure currents flowing through the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Pch transistor, and the substrate potential supply terminal of the internal Nch transistor of the circuit block 40, respectively. .
[0044]
(Third embodiment)
FIG. 15 is a diagram showing a semiconductor integrated circuit according to the third embodiment. The configuration is such that a plurality of current inspection circuits 200 inside the LSI 1 shown in the second embodiment are provided. The current value inspection results from the respective current inspection circuits 200 are transmitted to the inspection determination circuit 42 via the current value monitor signal lines 1 to 4, and the result of the determination whether the sum of the current value inspection results falls below or exceeds the predetermined current value is determined. A signal is output to the outside to determine whether there is a defect. By having a plurality of current inspection circuits 200, the potential supplied to the circuit block 40 can be strengthened, and the internal power supply drop can be reduced.
[0045]
(Fourth embodiment)
FIG. 16 is a diagram showing a fourth embodiment of the present invention. Although the current inspection circuit 200 is provided outside the LSI 1, the inside of the LSI 1 is divided into a plurality of circuit blocks 40, and each circuit block 40 has a configuration in which each potential supply line is connected to the current inspection circuit 200. . Since the potential supply lines of each circuit block 40 are individually connected to the current test circuit 200, the potential supplied to the circuit block 40 can be strengthened, and the internal power supply drop can be reduced.
[0046]
FIG. 17 is a diagram showing the effect of dividing a circuit block. By dividing the circuit block 40 inside the LSI 1, it is possible to divide a steady-state leak current component, and to easily detect an abnormal current due to a defect.
[0047]
(Fifth embodiment)
FIG. 18 is a diagram showing a fifth embodiment of the present invention. In the third embodiment, the configuration is such that the internal circuit block 40 is divided into a plurality. By dividing the circuit block into a plurality, as described with reference to FIG. 17, an abnormal current due to a defect can be easily detected.
[0048]
(Sixth embodiment)
FIG. 19 is a diagram showing a sixth embodiment of the present invention. A current test circuit 200 and a plurality of circuit blocks 40 are provided inside the LSI 1, and each potential is supplied from the current test circuit 200 to the circuit block 40 through a power switch 43. The power switch 43 receives a selection signal from the current inspection circuit 200 through the circuit block selection signal lines 1 to 4 and can control power supply to the respective circuit blocks. As a result, an inspection can be performed for each circuit block 40, and an abnormal current due to a failed circuit can be easily detected.
[0049]
【The invention's effect】
Due to the miniaturization of the process, the leakage current component flowing constantly increases. In an IDDQ test, which is an effective means for detecting a failure, an abnormal current caused by a failure circuit is buried in a steady-state leak current component, and the IDDQ test becomes impossible.
[0050]
According to the present invention, it is possible to separate an increasing leak current component from an abnormal current due to a failure, and to perform an IDDQ test even in a process that has been further miniaturized in the future. Further, the cause of the failure can be easily determined.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a conventional IDDQ test.
FIG. 2 is a diagram illustrating a circuit configuration example of a VT-CMOS.
FIG. 3 is a diagram illustrating a device configuration example of a VT-CMOS.
FIG. 4 is a diagram showing a leakage current component of a transistor.
FIG. 5 is a diagram showing a change in leak current component of a transistor due to bias application.
FIG. 6 is a diagram showing a configuration of an inspection device according to the first embodiment.
7 is a diagram showing an internal configuration of the current test circuit shown in FIG.
FIG. 8 is a diagram for explaining a method for setting an optimum substrate potential.
FIG. 9 is a diagram showing the principle of the present invention.
FIG. 10 is a diagram for explaining the inspection method of the present invention.
FIG. 11 is a diagram illustrating an example of VDD dependency of IDDQ.
FIG. 12 is a diagram illustrating an example of temperature dependence of IDDQ.
FIG. 13 is a diagram illustrating an example of a temporal change of IDDQ.
FIG. 14 is a diagram illustrating a configuration of an LSI according to a second embodiment.
FIG. 15 is a diagram illustrating a configuration of an LSI according to a third embodiment.
FIG. 16 is a diagram showing an inspection device according to a fourth embodiment.
FIG. 17 is a diagram for describing an effect of circuit block division.
FIG. 18 is a diagram illustrating a configuration of an LSI according to a fifth embodiment.
FIG. 19 is a diagram illustrating a configuration of an LSI according to a sixth embodiment.

Claims (15)

(A) applying a predetermined potential to each of a power supply potential supply terminal, a ground potential supply terminal, a substrate potential supply terminal of an internal Nch transistor, and a substrate potential supply terminal of an internal Pch transistor of the semiconductor integrated circuit;
(B) measuring a current flowing through each of the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Nch transistor, and the substrate potential supply terminal of the internal Pch transistor;
Calculating a current value (IDDQ value) obtained by subtracting a current flowing through the substrate potential supply terminal of the internal Nch transistor and a current flowing through the substrate potential supply terminal of the internal Pch transistor from the current flowing through the power supply potential supply terminal; (C) a method for inspecting a semiconductor integrated circuit. In claim 1,
In the step (a),
A method for testing a semiconductor integrated circuit, wherein a reverse bias is applied to a substrate potential supply terminal of the internal Nch transistor and a substrate potential supply terminal of the internal Pch transistor. In claim 1,
The method further includes a step (d) of comparing the IDDQ value calculated in the step (c) with a predetermined reference value, and determining a good / defective product of the semiconductor integrated circuit based on the comparison result. An inspection method for a semiconductor integrated circuit. In claim 1,
The semiconductor integrated circuit includes a plurality of power supply potential supply terminals, a plurality of ground potential supply terminals, a plurality of substrate potential supply terminals of internal Nch transistors, and a plurality of substrate potential supply terminals of internal Pch transistors.
In the step (a),
Applying a predetermined potential to each of a plurality of power supply potential supply terminals, a plurality of ground potential supply terminals, a plurality of substrate potential supply terminals of an internal Nch transistor, and a plurality of substrate potential supply terminals of an internal Pch transistor of the semiconductor integrated circuit;
In the step (b),
Measuring currents flowing through the plurality of power supply potential supply terminals, the plurality of ground potential supply terminals, the plurality of substrate potential supply terminals of the internal Nch transistor, and the plurality of substrate potential supply terminals of the internal Pch transistor,
In the step (c),
A current value (IDDQ) obtained by subtracting the current flowing through the plurality of substrate potential supply terminals of the internal Nch transistor and the current flowing through the plurality of substrate potential supply terminals of the internal Pch transistor from the current flowing through the plurality of power supply potential supply terminals Value) is calculated. In claim 1,
The semiconductor integrated circuit includes a plurality of circuit blocks,
In the step (a),
Applying a predetermined potential to each of the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Nch transistor, and the substrate potential supply terminal of the internal Pch transistor of each of the plurality of circuit blocks;
In the step (b),
Measuring a current flowing through each of a power supply potential supply terminal, a ground potential supply terminal, a substrate potential supply terminal of an internal Nch transistor, and a substrate potential supply terminal of an internal Pch transistor of each of the plurality of circuit blocks;
In the step (c),
For each of the plurality of circuit blocks, a current value (IDDQ) obtained by subtracting the current flowing to the substrate potential supply terminal of the internal Nch transistor and the current flowing to the substrate potential supply terminal of the internal Pch transistor from the current flowing to the power supply potential supply terminal Value) is calculated. In claim 1,
In the step (a),
A method for testing a semiconductor integrated circuit, wherein a potential at which an off-leak current of a transistor is minimized is supplied to a substrate potential supply terminal of the internal Nch transistor and a substrate potential supply terminal of the internal Pch transistor. In claim 1,
Performing the steps (a) to (c) with a potential given to the power supply potential supply terminal as a first potential;
Next, the steps (a) to (c) are performed with the potential applied to the power supply potential supply terminal as a second potential, and the method for testing a semiconductor integrated circuit is performed. In claim 1,
Performing steps (a) to (c) with the ambient temperature of the semiconductor integrated circuit as a first temperature;
Next, the steps (a) to (c) are performed by setting the ambient temperature of the semiconductor integrated circuit to a second temperature, and the method for inspecting a semiconductor integrated circuit. In claim 1,
A method for inspecting a semiconductor integrated circuit, further comprising a step (d) of monitoring a time change of a current value flowing through the power supply potential supply terminal. A first circuit block, and a first current test circuit;
The first circuit block includes:
A first power supply potential supply terminal;
A first ground potential supply terminal;
A first substrate potential supply terminal of the internal Nch transistor;
A first substrate potential supply terminal of an internal Pch transistor;
The first current test circuit includes:
A predetermined potential is applied to each of the first power supply potential supply terminal, the first ground potential supply terminal, the first substrate potential supply terminal of the internal Nch transistor, and the first substrate potential supply terminal of the internal Pch transistor. Means (a);
Currents flowing through the first power supply potential supply terminal, the first ground potential supply terminal, the first substrate potential supply terminal of the internal Nch transistor, and the first substrate potential supply terminal of the internal Pch transistor are measured. Means (b);
A current obtained by subtracting a current flowing to a first substrate potential supply terminal of the internal Nch transistor and a current flowing to a first substrate potential supply terminal of the internal Pch transistor from a current flowing to the first power supply potential supply terminal. Means (c) for calculating a value (IDDQ value). In claim 10,
Said means (a)
A semiconductor integrated circuit device, wherein a reverse bias is applied to a first substrate potential supply terminal of the internal Nch transistor and a first substrate potential supply terminal of the internal Pch transistor. In claim 10,
The first current test circuit includes:
The apparatus further includes means (d) for comparing the IDDQ value calculated by the means (c) with a predetermined reference value, and for determining whether the first circuit block is good or defective based on the comparison result. Semiconductor integrated circuit device. In claim 10,
Further comprising a second current test circuit and a test determination circuit;
The first circuit block includes:
A second power supply potential supply terminal;
A second ground potential supply terminal;
A second substrate potential supply terminal of the internal Nch transistor;
A second substrate potential supply terminal of the internal Pch transistor;
The second current test circuit includes:
A predetermined potential is applied to each of the second power supply potential supply terminal, the second ground potential supply terminal, the second substrate potential supply terminal of the internal Nch transistor, and the second substrate potential supply terminal of the internal Pch transistor. Means (d);
Currents flowing through the second power supply potential supply terminal, the second ground potential supply terminal, the second substrate potential supply terminal of the internal Nch transistor, and the second substrate potential supply terminal of the internal Pch transistor are measured. Means (e);
A current obtained by subtracting a current flowing through a second substrate potential supply terminal of the internal Nch transistor and a current flowing through a second substrate potential supply terminal of the internal Pch transistor from a current flowing through the second power supply potential supply terminal. Means (f) for calculating a value (IDDQ value),
The inspection determination circuit,
Comparing the IDDQ value obtained by the first current determination circuit and the second current determination circuit with a predetermined reference value, and determining whether the first circuit block is good or defective based on the comparison result. A semiconductor integrated circuit device comprising: In claim 10,
A second circuit block, a second current test circuit, and a test determination circuit,
The second circuit block includes:
A power supply terminal,
A ground potential supply terminal,
A substrate potential supply terminal for an internal Nch transistor;
A substrate potential supply terminal of an internal Pch transistor;
The second current test circuit includes:
Means (d) for applying a predetermined potential to each of a power supply potential supply terminal, a ground potential supply terminal, a substrate potential supply terminal of an internal Nch transistor, and a substrate potential supply terminal of an internal Pch transistor of the second circuit block;
Means (e) for measuring currents flowing through the power supply potential supply terminal, the ground potential supply terminal, the substrate potential supply terminal of the internal Nch transistor, and the substrate potential supply terminal of the internal Pch transistor of the second circuit block;
The current flowing from the power supply potential supply terminal of the second circuit block to the current flowing to the substrate potential supply terminal of the internal Nch transistor of the second circuit block and the substrate potential supply terminal of the internal Pch transistor of the second circuit block Means (f) for calculating a current value (IDDQ value) obtained by subtracting the flowing current,
The inspection determination circuit,
Whether the first circuit block is good or bad is determined based on a comparison result between the IDDQ value obtained by the first current determination circuit and a predetermined reference value, and obtained by the second current determination circuit. A semiconductor integrated circuit device for determining whether the second circuit block is good or bad based on a comparison result between an IDDQ value and a predetermined reference value. In claim 10,
A second circuit block, and a switch circuit;
The second circuit block includes:
A first power supply potential supply terminal;
A first ground potential supply terminal;
A first substrate potential supply terminal of the internal Nch transistor;
A first substrate potential supply terminal of an internal Pch transistor;
The means (a) of the first current test circuit includes:
A first power supply potential supply terminal, a first ground potential supply terminal, a first substrate potential supply terminal of an internal Nch transistor, a first substrate potential of an internal Pch transistor of the first circuit block or the second circuit block; Apply a predetermined potential to each of the supply terminals,
The switch circuit,
A semiconductor integrated circuit device which performs on / off control of potential supply from the first current test circuit to the first circuit block or the second circuit block.

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