KR100614646B1 - Built-in current sensor and current testing method thereof - Google Patents

Abstract

The present invention relates to a built-in current sensing circuit for current testing, and compares the fault current and the reference current to test whether a fault current is generated.

According to the present invention, a switch for delivering a fault current of a current generator and a test target device generating a first constant current, a second constant current, and a third constant current to a node and the node is supplied with the first constant current and supplied to the node. A current adder for summing the constant current and the fault current, a current subtractor for subtracting the summed current from the sum of the second constant current and the reference current, and a voltage determined by the difference between the third constant current and the subtracted current And a detector for detecting whether the detection voltage is lower than the detection voltage.

According to the present invention, a current detector is built in an integrated circuit, and high-speed testing is possible by detecting a fault current through current comparison without current-voltage conversion.

Description

Built-in current sensing circuit and its current testing method {BUILT-IN CURRENT SENSOR AND CURRENT TESTING METHOD THEREOF}

1 is a circuit diagram of a built-in current sensing circuit according to an embodiment of the present invention.

2 is a timing diagram of signals in the circuit according to FIG. 1.

* Description of the symbols for the main parts of the drawings *

100: inspection target device 10: switch

20: constant current generator 30: detector

40: first current mirror 50: second current mirror

The present invention relates to a test of a semiconductor integrated circuit, and more particularly, to a built-in current sensing circuit for testing a stationary current value of a semiconductor integrated circuit.

Recently, CMOS, which has advantages such as low power consumption and high integration ratio, has been widely used for implementing integrated circuits as an important circuit component. However, as the degree of integration and size of integrated circuits using CMOS technology increases greatly, many physical defects are caused by various factors in the manufacturing process of the chip, and failures are generated. The faults caused by the increased density are short-circuited between transistor terminals and bridging faults due to resistive shorts between internal nodes, rather than the stuck-at used in previous models. Short faults indicate more frequent occurrences. The increased likelihood of failure in CMOS integrated circuits has made testing very difficult to verify that the circuit is operating normally, which requires a lot of time, manpower and cost.

In particular, these failures are not detected by the conventional chip testing logic test, that is, voltage test. Therefore, the recent active research as a solution to this is a way to detect the various types of failures present in the circuit by comparing the current value of the stationary state. Current tests use fewer test patterns than voltage tests to detect physical defects such as bridging, as well as reliability-related failures such as gate leakage currents. Current test methods include measuring the current outside the chip and measuring the inside of the chip. In the external current testing method, it is difficult to detect a small amount of fault current precisely because the testing equipment has a significantly larger charging load than the circuit under test, and high-speed testing is impossible due to the delay caused by the impedance of the testing equipment. Do. In addition, the conventional testing equipment is to measure the voltage, there is a problem that requires a separate current testing equipment. On the other hand, the internal current testing method is advantageous in that it can use existing test equipment, enable high speed testing, and increase current sensing resolution.

Most of the existing built-in current detectors use a fault current as an input, convert the voltage internally, compare the converted voltage with a reference voltage, and output the result to an external output terminal. However, the voltage drop generated by the current-to-voltage converter used in this manner is an important obstacle to the ever-lower operating voltages.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a built-in current sensing circuit for testing a fault current in such a manner as to directly compare the current with a reference current without using a current-to-voltage converter. To provide its current testing method.

The built-in current sensing circuit for current testing according to the present invention for achieving the above-described technical problem is to transmit a fault current of the current generator and the inspection target device generating a first constant current, a second constant current, and a third constant current to the node. A switch and the node supplied with the first constant current, a current adder for summing the constant current and the fault current supplied to the node, and a current subtractor for subtracting the summed current from the sum of the second constant current and the reference current; and And a detector for detecting whether a voltage determined by the difference between the third constant current and the subtracted current is lower than a detection voltage.

In this embodiment, the switch is activated periodically by a test signal.

In this embodiment, the first constant current and the third constant current are quantitatively equal, and the second constant current is quantitatively twice the first constant current.

In this embodiment, the current adder and the current subtractor each include a current mirror.

In this embodiment, the constant current generator generates the first to third constant currents in response to a reference voltage.

In this embodiment, the detector comprises an inverter.

According to another feature of the invention, generating a first constant current, a second constant current, and a third constant current, transferring a fault current of the device under test to the node, and the node is supplied with the first constant current and the node Summing the constant current and the fault current supplied to the subtractor; subtracting the summed current from the sum of the second constant current and the reference current; and the voltage determined by the difference between the third constant current and the subtracted current. Detecting whether the detection voltage is lower than the detection voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a circuit diagram of a built-in current sensing circuit according to an embodiment of the present invention. This embodiment will be described with reference to a timing diagram of signals in the circuit according to FIG. 1 shown in FIG.

The built-in current sensing circuit of the present invention includes a switch 10, a constant current generator 20, a detector 30, a first current mirror 40, and a second current mirror 50.

The switch 10 includes a first transistor Q0 to which the test signal Test_in is applied to the gate and a second transistor Q1 to which the inverted test signal is applied to the gate. The drain of the first transistor is connected to the inspection target device 100, and the source is connected to a node where the constant current generator 20 and the first current mirror 40 meet. The drain of the second transistor Q1 is connected to the inspection target device 100 and the source is connected to the ground. The built-in current sense circuit has two modes of operation: normal operation mode and Iddq test mode. That is, the sensing circuit performs a function of operation or non-operation according to the test signal. Referring to FIG. 1, when the test signal is at a high level, the transistor Q0 is in a conductive state so that a fault current Idef flows through a current path, and this current is a node where the constant current generator 20 and the first current mirror 40 meet. Delivered. On the contrary, when the test signal is at the low level, the transistor Q0 is in the cutoff state and the transistor Q1 is in the conductive state, and the circuit under test is connected to the ground terminal. Therefore, the defect current Idef is not tested at this time.

In this circuit, the transient current is generated by the transition of the clock signal in the circuit under test. Since the transient current is different from the fault current, it should not be failed at the final output stage. Therefore, as shown in FIG. 2, the test signal is always kept at a low level to block the operation of the current sensing circuit in the timing at which the transient current occurs, that is, in a section in which the clock signal of the circuit to be inspected changes.

Referring to the constant current generator 20, the voltage Vref generated from the voltage generator is applied to the gates of the transistors Q6 to Q9, respectively, so that the current I flows in the current path of each transistor. This is a large amount of current source used for high speed comparison in differential current amplifiers.

When the test signal is at the high level, the sum of the defect current Idef and the current I flows in the current path of the transistor Q2. Transistor Q2 and transistor Q3 form a first current mirror 40. The gate and the drain of the transistor Q2 are connected, and the gate is also connected to the gate of the transistor Q3. As a result, the same amount of current I + Idef flows through the transistor Q3. The constant current flowing through the transistors Q7 and Q8 is combined at one node so that twice the constant current is at the node where the constant current generator 20, the first current mirror 40, and the second current mirror 50 meet. Inflow. This node also introduces a current Iref generated from the reference current generator. Since the current of the current I + Idef flows through the transistor Q3, the current of I + (Iref-Idef) flows through the transistor Q4. Transistors Q4 and Q5 form a second current mirror 50. The gate and the drain of the transistor Q4 are connected, and the gate is also connected to the gate of the transistor Q5. As a result, the same amount of current I + (Iref-Idef) flows through the transistor Q5.

Detector 30 is connected to the drain of transistor Q9, which duplicates the current in the PMOS current mirror pair, and the drain of transistor Q5, which duplicates the current in the NMOS current mirror pair. It has a structure connected to the input of the inverter to generate a. The constant value of the reference current Iref is equal to the value of the steady state current when the circuit under test is free of defects. As a result, the current I is a constant flowing current, so that the fault current is generated by the operation of the inverter connected to this node due to the voltage change depending on the magnitude of + or-of the (Iref-Idef) part of the current I + (Iref-Idef). It is judged.

Therefore, if there is a fault current Idef, it has a value larger than the reference current Iref, and the output signal path / fail becomes '1', and when the fault current has a value smaller than the reference current, it becomes '0'. Therefore, it can be seen that a fault current exists when the output signal path / fail becomes '1'.

 On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, according to the present invention, a current detector is built in an integrated circuit, and high-speed testing is possible by detecting a fault current through current comparison without current-voltage conversion.

Claims (8)

A current generator for generating a first constant current, a second constant current, and a third constant current; A switch for transferring a fault current of the inspection target device to the node; The node is supplied with the first constant current; A current adder for summing the constant current and the fault current supplied to the node; A current subtractor for subtracting the summed current from the sum of the second constant current and the reference current; and And a detector for detecting whether a voltage determined by the difference between the third constant current and the subtracted current is lower than a detection voltage. The method of claim 1, The switch is periodically activated by a test signal. The method of claim 1, And the first constant current and the third constant current are quantitatively equal, and the second constant current is quantitatively twice the first constant current. The method of claim 1, And the current adder and the current subtractor each include a current mirror. The method of claim 1, And the constant current generator generates the first to third constant currents in response to a reference voltage. The method of claim 1, And said detector comprises an inverter. Generating a first constant current, a second constant current, and a third constant current; Delivering a fault current of the device under inspection to the node; The node is supplied with the first constant current; Summing the constant current and the fault current supplied to the node; Subtracting the summed current from the sum of the second constant current and the reference current; and Detecting whether the voltage determined by the difference between the third constant current and the subtracted current is lower than a detection voltage. The method of claim 7, wherein And the first constant current and the third constant current are quantitatively equal, and the second constant current is quantitatively twice the first constant current.

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