KR100682750B1 - On-line testing apparatus embeded the circuit and Method thereof - Google Patents

Abstract

The present invention relates to a built-in on-line testing apparatus and method thereof of a target circuit for testing normal / abnormal of a chip such as an ASIC made of CMOS. This on-line testing device is formed as a package that is connected to the test target circuit and a test target circuit that performs a set function by receiving operating power, and compares another by detecting a current generated from the test target circuit. And a testing unit configured to generate a current, determine one of normal and abnormal from the currents, and output a determination signal corresponding thereto. Accordingly, since testing is performed using the output current of the target circuit regardless of whether it is operating or testing, it is possible to accurately determine not only the failure caused by the leakage current caused by the gate but also the bridging failure, thereby improving the reliability of the system.

CMOS, ASIC, Test, Current, Sensing, Embedded

Description

On-line testing apparatus embeded the circuit and method according to the present invention

1 is a circuit diagram showing a built-in on-line testing device of the target circuit according to the present invention,

2 is a circuit diagram showing in detail the amplifier according to the present invention,

3 is a circuit diagram showing in detail the comparator according to the present invention,

4 is a timing diagram illustrating a normal case in the operation of the target circuit or the environment under test according to the present invention;

FIG. 5 is a timing diagram illustrating an abnormal case in an operation of a target circuit or an environment under test according to the present invention.

Explanation of symbols on the main parts of the drawing

10: circuit under test 11: amplifier

12 comparator 13 first transistor

14 second transistor 18 inverter

20: testing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a built-in on-line testing apparatus and method of the target circuit, and more particularly, a target circuit for testing normal / abnormal of a chip such as an application specific integrated circuit (ASIC) manufactured by CMOS (Complementray Matal Oxide Semiconductor). The present invention relates to a built-in online testing apparatus and a method thereof.

In general, CMOS is a semiconductor memory device having a very small operating current, and is widely used in memory and custom semiconductors.

In this CMOS technology, as the complexity and size of integrated circuits gradually increase, the complexity increases, and many physical defects occur due to various factors in the manufacturing process of the chip. And accordingly abnormal operation, that is, failures are occurring. The faults caused by the increased density are more likely to be caused by bridging faults due to resistive shorts between internal nodes and between transistor terminals, rather than the stuck-at used in previous models. Short faults due to shorts indicate more frequent occurrences. As the likelihood of failure in CMOS integrated circuits increases, testing of whether circuits operate normally becomes very difficult, which requires a lot of time, manpower, and cost.

Due to the structure of the CMOS technology, a transient current flows only in a transient state, and no current flows except for a pn junction leakage current in a steady state. However, if a bridging fault or a short circuit fault occurs in the CMOS circuit, an abnormal phenomenon occurs in which a constant current path is formed from the power supply VDD to the ground GND, and a current I _DDQ flows even in a normal state. These phenomena are the cause of secondary failures due to signal delay, heat generation, etc. without causing failures due to logical errors in most cases. This results in critical failures within the electronic system, resulting in reduced system and integrated circuit reliability.

Therefore, the flow of I _DDQ is very difficult to detect by the conventional testing method, that is, logic testing, that is, voltage testing, and various types of failures existing in the circuit by observing steady-state current values changed by the failure of the CMOS circuit. The current testing method should be used to easily detect. Current testing uses fewer test patterns than voltage testing, but can detect physical failures, such as bridging failures, as well as failures related to circuit reliability, such as gate leakage current. In addition, it is not necessary to propagate the effect of the fault to the output stage, and has the advantage of detecting the fault by measuring only the current supplied from the power supply of the circuit, that is, the I _DDQ value and comparing it with the reference current value.

Current testing methods include off-chip current testing, which measures fault current outside the chip, and built-in current testing, which incorporates additional circuitry inside the chip for fault current testing. There is this. External current testing method has difficulty in detecting delicately small amount of fault current because the external testing equipment has a considerably larger capacitive load than the circuit under test (CUT). High speed testing is not possible because of the delay caused by the impedance of the equipment. In addition, conventional testing equipment is to measure the voltage requires a separate current testing equipment has a cost problem. To solve these shortcomings, we can consider a built-in current testing method, in which a built-in current sensor (BICS) is embedded in the chip to detect fault current.

Such a built-in current sensing method can observe changes in current values that are difficult to measure as changes in corresponding voltage values (logical values), so that existing testing equipment can be used as it is. Compared with, it is easy to determine the fault current. In addition, since there is no external load, high speed testing is possible. However, this method also has the disadvantage of increasing the area of the chip and degrading the operation performance of the circuit because the current sensing circuit is embedded inside the chip.

There are four general built-in current sensing circuits, each of which is described below.

First, Maly's built-in current sense circuit uses a differential amplifier and detects fault currents compared to a reference voltage. In this case, two control clocks are used and a horizontal NPN Bipolar Junction Transistor (BJT) is used to generate a voltage generated by the fault current. The advantage of this circuit is that the use of BJT enables the detection of very small fault currents, while requiring external reference voltages, two clocks, and a BiCMOS process, resulting in a long manufacturing process and reduced productivity. Accordingly, there is a problem that the cost is increased.

Second, Miura's built-in current sensing circuit consists of a V-I transducer, a level converter, and an integrator circuit. This circuit has the advantage of being able to test BICS itself by using an external current source, but the use of large capacitors and resistors has a large area consumption, and the integration circuit is used to determine whether there is a failure. It has a lot of problems.

Third, Tang's built-in current-sense circuit consists of an op amp, current-sense resistor, and current detector, and uses two different supply sources. Current resolution can be adjusted and no external reference current / voltage is required. However, since two supply power supplies are required, the BJT process is mixed, resulting in costly manufacturing and poor productivity.

Fourth, Kim's built-in current sensing circuit uses V-I transistors and current mirror circuits. This circuit has the smallest area in terms of area consumption by using very small transistors, but requires a mode selection and an external control terminal for this.

The above-described prior arts make it almost impossible to test each circuit as well as the above-mentioned problems while the circuit under test is in operation, i.e., in an online state of the circuit under test. Therefore, since the system supported by the circuit under test needs to temporarily stop its operation, there is a problem in that loss and damage occurs due to interruption of the system. There is a need for an apparatus and method for solving this problem.

The present invention has been devised to solve the above problems, and even if it is mounted as an embedded type, the productivity of the manufacturing process is improved while maintaining the characteristics of the small CMOS, and maintenance costs are required by using the power of the circuit under test. It is an object of the present invention to provide a built-in on-line testing apparatus and a method thereof for enabling a test even during operation of a circuit under test.

The object of the present invention is a test target circuit which is supplied with operating power and performs a set function, and is electrically connected to the test target circuit and formed as one package, and detects a current generated from the test target circuit to generate another comparison current. It is achieved by a built-in on-line testing device of the target circuit including a testing unit for generating a, and determining any one of normal and abnormal from the currents and outputs a corresponding determination signal.

In addition, it is preferable to further include a notification unit for receiving at least one of the visual and auditory signals received from the testing unit.

Here, the testing unit is located between the circuit under test and the ground to sense a first current and converts the first current into a first voltage (Vcut), an amplifier for amplifying the first voltage into a square wave-shaped voltage signal, the voltage of the amplifier An inverter that converts a transient current into a second current only when the signal transitions from low to high, a second transistor that converts a second current of the inverter into a second voltage Vinv, and a first of the first transistor It is preferable to include a comparator comparing the voltage Vcut with the second voltage Vinv of the second transistor and outputting a discrimination signal of one of normal and abnormal.

The capacity ratio of the first transistor to the second transistor is 10 to 1, and it is preferable that the first transistor, the second transistor, and the inverter have a CMOS structure.

In addition, the comparator has a structure of a differential amplifier, and it is preferable that a plurality of CMOS transistors are configured in series and in parallel in the amplifier and the comparator, respectively.

In addition, the circuit under test is preferably composed of a plurality of CMOS elements.

In the on-line testing method of the target circuit, the object is to detect a first current from the circuit under test, converting the first current into a first voltage (Vcut), and converting the first voltage into a square wave voltage. Amplifying the signal, converting the transient current into a second current which generates a transient current only when the signal transitions from low to high, converting the second current into a second voltage Vinv, and It is also achieved by a built-in on-line testing method of the target circuit which includes comparing the first voltage Vcut and the second voltage Vinv and generating a discrimination signal of either normal or abnormal according to the comparison. .

The method may further include informing at least one of visual and audio to the outside according to the discrimination signal to inform that the fault occurs due to an abnormal phenomenon in the target circuit supporting the system.

Hereinafter, with reference to the accompanying drawings will be described in detail the built-in online testing apparatus and method of the target circuit according to the present invention. 1 is a circuit diagram showing a built-in on-line testing apparatus of the target circuit according to the present invention, Figure 2 is a circuit diagram showing in detail the amplifier according to the invention, Figure 3 is a circuit diagram showing in detail the comparator according to the present invention.

As shown in FIG. 1, the built-in online testing apparatus of the present target circuit has a test target circuit 10 and a testing unit 20 to enable testing even in an online state corresponding to the above object. Here, the testing unit 20 is packaged together with the target circuit 10, receives power from the target circuit 10, and discriminates normal and abnormal from the power source.

The test target circuit 10 is for supporting a system that performs a specific function, and is composed of an ASIC (Custom Semiconductor) having a suitable number of CMOS devices arranged therein to support the system. ASICs can be customized to give designers the features they want.

The testing unit 20 is electrically connected to the target circuit 10 and disposed in a predetermined space in one package. The testing unit 20 senses a current generated from the target circuit 10 and detects one of normal and abnormal from the current. Judgment outputs a determination signal corresponding thereto. The current is converted into a voltage, the voltage is defined as a first voltage Vcut, the first voltage Vcut is amplified to a predetermined gain, the amplified voltage component is converted into a current, and converted back into a comparison voltage. Therefore, it is defined as the second voltage Vinv. At this time, the testing unit 20 compares the first voltage (Vcut) and the second voltage (Vinv) to determine whether the same, and if the same, generates a determination signal of 'normal', if not the same ' An abnormal signal is generated.

And, the testing unit 20 notifies at least one or more of the visual and auditory according to the determination signal to the outside to inform the target circuit 10 supporting the system that the failure caused by the abnormal phenomenon (not shown) City) is connected. The notification unit may be internal or external. In order to reduce costs, LEDs are commonly used.

The testing unit 20 includes a first transistor 13, an amplifier 11, an inverter 18, a second transistor 14, and a comparator 12. The function thereof is as follows.

The first transistor 13 is located between the target circuit 10 and the ground, and detects a first current operating from the target circuit 10 and converts it into a first voltage Vcut. In addition, even when a power source for testing is applied to the target circuit 10, the target circuit 10 detects a first current for testing and converts it to a first voltage Vcut. Since the target circuit is made of a CMOS device and the operating current is low, the CMOS device is used to convert the first current into the first voltage Vcut.

The amplifier 11 amplifies the magnitude and waveform of the first voltage Vcut from the first transistor 13 regardless of whether it is operating or testing. The first voltage Vcut is either normal or abnormal. To judge, amplify by a predetermined gain value so that a voltage signal capable of operating in inverter 18 is produced. As shown in FIG. 2, the amplifier 11 is configured as a differential amplifier in which a plurality of CMOS transistors are configured in series and in parallel.

The amplifier 11 includes a pair of nMOS transistors N1 and N2 configured in parallel and a pair of pMOS transistors P1 and P2 configured in a current mirror form in series, respectively, and the gate terminal of the nMOS transistor N2. The first voltage Vcut is input to the amplifier and amplified by a predetermined gain to output the amplified voltage signal at the connection point of the cathode terminal and the anode terminal corresponding to the nMOS transistor N2 and the pMOS transistor P2. The voltage signal is determined by the size of the nMOS transistor N1, and is amplified to have the size of the first voltage Vcut by adjusting the transistor N1.

The inverter 18 converts the voltage signal amplified from the amplifier 11 into a second current, and generates a second current during the transition from Low to High of the square wave portion of the voltage signal. The inverter 18 also uses a CMOS element as mentioned above, i.e., because it must be sensitively inverted with a second current. For example, in the case of a full CMOS circuit, current (I _DDT ) is generated when the input transitions, but in the case of the inverter 18, the size of the two transistors of the pMOS and nMOS is reduced and the ratio of the two transistors is the same. The transient current, i.e., the second current, is generated only when the input transitions from low to high, and vice versa. Because of this property, if there is no failure in the circuit under test 10, a second current waveform is formed in the same shape as the first current waveform of the circuit under test 10, but in the case where a failure exists, the part where the failure is activated Produces a different shape of the current waveform.

The second transistor 14 converts the second current output from the inverter 18 back to the second voltage Vinv in order to compare the second current output under the same condition as the first voltage Vcut.

The comparator 12 has a form of a differential amplifier similar to the amplifier 11, and receives a first voltage Vcut of the first transistor 13 and a second voltage Vinv of the second transistor 14, respectively, and determine a discrimination signal. Outputs That is, when the signal has the same signal, a normal signal indicating that the test target circuit 10 is normal, and if not, output an abnormal signal indicating that the test target circuit 10 is abnormal.

As shown in FIG. 3, the comparator 12 compares the output current of the circuit 10 to be tested, that is, the first voltage Vcut converted by receiving the first current and the second voltage Vinv generated by copying the same. The N-type CMOS transistor N3 that receives the first voltage Vcut and the N-type CMOS transistor N4 that receives the second voltage Vinv are disposed symmetrically with each other. The P-type CMOS transistors P3 and P4 connected in series with the CMOS transistors N3 and N4 are formed in the form of current mirrors. The discrimination signal is output between the N-type CMOS transistor N4 and the P-type CMOS transistor P4.

Then, the notification unit may recognize at least any one of visual and hearing to a user who uses the system or an administrator who manages the system by the determination signal of any one of a normal signal and an abnormal signal.

On the other hand, since the first current generated in the test target circuit 10 is much larger than the second current generated in the inverter, in the present invention, the first transistor does not significantly affect the operation of the test target circuit 10. It is preferable to keep the size ratio of the 13 and the second transistor 14 to about 10: 1. Therefore, even if the test target circuit 10 is changed, if only the size of the first transistor 13 and the second transistor 14 is adjusted according to the size and current of the test target circuit 10, it can be applied immediately without modification of the testing unit. Can be.

As described above, the method of the embedded online testing apparatus of the circuit to be tested of the present invention is as shown in FIGS. 4 and 5. 4 is a timing diagram illustrating a normal case in the operation of the target circuit according to the present invention or in an environment under test, and FIG. 5 is a timing diagram illustrating an abnormal case in the environment of the target circuit according to the present invention during operation or testing.

First, the first current is output to the testing unit 20 both in the test target circuit 10 and during the testing. Then, the testing unit 20 detects the first current to determine whether the test target circuit 10 is normal or abnormal.

As shown in FIG. 4, when the test target circuit 10 is normal, that is, when there is no failure, when the input signal is changed, that is, in the transient state, a conductive path is formed from the power supply to the ground to generate the first current and is normal. In the state, no current flows. For example, the first current generated in the test target circuit 10 has the same triangular wave shape as the waveform changed from the first transistor 13 to the first voltage Vcut, and the current is in a steady state except for the triangular wave area. Does not flow, but a transient current, or a current, flows in a transient state in the triangular wave region.

While the first voltage Vcut is applied to the comparator 12, the amplitude and waveform of the first voltage Vcut are amplified by the amplifier 11 into a voltage signal in the form of a square wave. Here, in the output signal of the amplifier 11, that is, the voltage signal, one square wave is continuously generated in one triangular waveform. The voltage signal is applied to the inverter 18 and converted into a second current which generates a transient current only during the transition from Low to High. The second current has the same waveform as the triangular wave shape of the first current and the first voltage Vcut.

In order to compare the second current under the same condition as the first voltage Vcut, the second current is again converted from the second transistor 14 to the second voltage Vinv. As a result, the first current is converted from the first transistor 13 to the first voltage Vcut, and the second current is converted from the second transistor 14 to the second voltage Vinv. You will have a waveform.

Therefore, since the first voltage Vcut and the second voltage Vinv have the same magnitude and waveform, they are applied to the comparator 12 to maintain a normal signal, that is, a high signal. When the notification unit receives a high signal as a discrimination signal, it notifies the system that the system is operating normally. The method makes it possible to recognize either vision or hearing.

On the other hand, as shown in FIG. 5, when the circuit under test 10 is abnormal, that is, when a failure occurs, the conduction path from the power supply to ground even in a normal state is activated while a failure in the circuit under test 10 is activated. The fault current is generated, and I _DDQ is applied to the testing unit 20 in the form of a first current having a value equal to or greater than the pn junction leakage current in a section where the fault is activated.

That is, when a first current connected to the test unit 20 is connected to a leakage current that is much larger than a normal magnitude between the current and the current which is a transient portion of the triangular waveform, the first current is transferred from the first transistor 13. It has the same waveform as the waveform of the converted first voltage (Vcut), an abnormal current, that is, a leakage current flowing at a value higher than a reference, is connected between two transient currents between a triangular wave and a triangular wave in one region, and a leakage current is generated. In the triangular wave region except for one region, a transient current, that is, a current flows in a transient state, but no current flows in a steady state except the triangular wave region.

While the first voltage Vcut is applied to the comparator 12, the amplitude and waveform of the first voltage Vcut are amplified by the amplifier 11 into a voltage signal in the form of a square wave. Here, the amplifier 11 is amplified by an abnormal voltage signal formed of one square wave in which two transient currents are merged by a leakage current. The voltage signal is applied to the inverter 18 and converted into a second current which generates a transient current only during the transition from Low to High. That is, the second current is converted into a current in which one transient is removed because one square wave in which two transients are merged transitions from low to high in the inverter 18 once.

In order to compare the second current under the same condition as the first voltage Vcut, the second current is converted back from the second transistor 14 to the second voltage Vinv. As a result, the first current is converted from the first transistor 13 to the first voltage Vcut, and the second current is converted from the second transistor 14 to the second voltage Vinv. Will have

Therefore, since the first voltage Vcut and the second voltage Vinv have different waveforms, the comparator 12 changes to an abnormal signal, that is, a low signal. When the notification unit receives the low signal as a discrimination signal, it notifies the system that the system is operating abnormally. The method makes it possible to recognize either vision or hearing.

The present invention has the effect of improving the productivity according to the manufacturing process while maintaining the characteristics of the small CMOS, even if mounted as a built-in, not only maintenance costs using the power of the circuit under test, but also operation of the circuit under test Since the test is possible during the test, it is convenient to perform the test at any time, to prevent the loss and damage caused by the system stop, and to maximize the stable operation of the system.

In addition, since the test is performed using the output current of the target circuit regardless of whether it is operating or testing, it is possible to accurately determine the bridging failure as well as the failure caused by the leakage current caused by the gate, thereby improving the reliability of the system.

In addition, there is no need for a separate control terminal except for one output terminal for transmitting a determination signal to the outside, so that the user can apply the system to a desired system more efficiently.

Claims (8)

In the built-in testing device that is electrically connected to the test target circuit for receiving the operating power to perform a set function is formed as a package, the failure test of the target circuit, A first transistor disposed between the test target circuit and the ground and configured to sense a first current generated from the target circuit and convert the first current into a first voltage; An amplifier for amplifying the first voltage into a square wave shaped voltage signal; An inverter for converting a transient current into a second current generated only when the voltage transitions from a low voltage to a high voltage among the output voltage signals of the amplifier; A second transistor converting a second current of the inverter into a second voltage; And And a testing unit including a comparator configured to compare the first voltage of the first transistor with the second voltage of the second transistor and output a discriminating signal of one of normal and abnormal. Device. The method of claim 1, And a notification unit which receives a discrimination signal from the testing unit and informs at least one of visual and auditory information. delete The method of claim 1, The capacity ratio of the first transistor and the second transistor is composed of 10 to 1, wherein the first transistor, the second transistor and the inverter has a CMOS structure, embedded online testing apparatus of the target circuit. The method of claim 1, And the comparator has a structure of a differential amplifier, and the amplifier and the comparator have a plurality of CMOS transistors each configured in series and in parallel. The method of claim 1, And the test target circuit comprises a plurality of CMOS elements. In the online testing method of the circuit under test, Sensing a first current from the test target circuit; Converting the first current into a first voltage Vcut; Amplifying the first voltage into a square wave shaped voltage signal; Converting the amplified voltage signal into a second current that generates a transient current only when the low voltage transitions from a low voltage to a high voltage; Converting the second current into a second voltage Vinv; Comparing the waveforms with each other by receiving the first voltage Vcut and the second voltage Vinv; And And generating a discriminating signal of one of normal and abnormal according to the comparison. The method of claim 7, wherein Built-in online testing of the target circuit further comprising notifying at least one of visual and auditory to the outside according to the discrimination signal to indicate that a failure due to an abnormal phenomenon has occurred in the target circuit supporting the system. Way.

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