CN108169661B - Integrated circuit design method and integrated circuit latch-up test method - Google Patents
Integrated circuit design method and integrated circuit latch-up test method Download PDFInfo
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- CN108169661B CN108169661B CN201711455300.9A CN201711455300A CN108169661B CN 108169661 B CN108169661 B CN 108169661B CN 201711455300 A CN201711455300 A CN 201711455300A CN 108169661 B CN108169661 B CN 108169661B
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Abstract
The invention provides an integrated circuit design method and an integrated circuit latch-up test method, belonging to the technical field of integrated circuit design, wherein the integrated circuit design method comprises the steps of selecting a designated port from an integrated circuit as a control end of a latch-up test mode, and establishing an incidence relation between the control end and the rest ports except a reset port in the integrated circuit so as to enable the control end to control the states of the rest ports in the latch-up test mode.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to an integrated circuit design method and an integrated circuit latch-up effect test method.
Background
As shown in FIG. 1, N-Well is a collector region of both lateral NPN and longitudinal PNP, and P-Sub is a base region of both lateral NPN and longitudinal PNP, and also is a collector region of both lateral NPN and longitudinal PNP, each collector region generates a voltage drop between collector-base and collector contacts, so that L atch up (latch-up) refers to a path between a power supply (VDD) and a ground (GND or VSS) due to the mutual influence of parasitic PNP and NPN transistors, and the existence of a low-impedance path generates a large current between VDD and GND.
As integrated circuit manufacturing processes evolve, and the packaging density and integration become higher, the probability of generating L atch ups increases, L atch ups are most likely to occur at I/O circuits that are susceptible to external interference, and also occur occasionally at internal circuits, the excessive amount of current generated by L atch ups may cause permanent damage to the chip.
At present, a test method for L atch up is mainly a L atch up test method established by referring to standard EIA/JESD 78D. due to the complexity of an integrated circuit, when L atch-up test is carried out on the circuit, interference of undesired signals, such as interference of leakage currents, such as pull-up current, pull-down current, I/O port output current and the like, on an I/O port is likely to exist, so that the L atch up test is inaccurate, and whether L atch up occurs in the circuit cannot be accurately judged.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an integrated circuit design method and an integrated circuit latch-up test method, which increase the design aiming at L atch up test in the design stage of the integrated circuit, so that the integrated circuit can better meet the requirement of L atch up test, thereby improving the accuracy and reliability of L atch up test.
In a first aspect, an embodiment of the present invention provides an integrated circuit design method, including:
selecting a designated port from the integrated circuit as a control end of a latch-up test mode;
and establishing an association relationship between the control end and the rest ports except the reset port in the integrated circuit, so that the control end controls the states of the rest ports in the latch-up test mode.
With reference to the first aspect, an embodiment of the present invention provides a first possible implementation manner of the first aspect, wherein the step of selecting a designated port from an integrated circuit as a control terminal of the latch-up test mode includes:
selecting a plurality of appointed ports from an integrated circuit as control ends of a latch-up test mode; when the combinational logic of the plurality of ports meets the set condition of entering the latch-up test mode, the integrated circuit enters the latch-up test mode.
With reference to the first aspect, an embodiment of the present invention provides a second possible implementation manner of the first aspect, where the step of establishing an association relationship between the control end and remaining ports of the integrated circuit except for a reset port includes:
establishing an incidence relation between the control end and an I/O port in an integrated circuit, so that the control end turns off a pull-up resistor circuit and a pull-down resistor circuit of the I/O port in a latch-up test mode, and turns off an output enabling end of the I/O port;
establishing an incidence relation between the control end and an analog circuit module connected with an I/O port in the integrated circuit, so that the control end closes the analog circuit module in a latch-up test mode and the I/O port connected with the analog circuit module is in a high-impedance state;
establishing an incidence relation between the control end and a phase-locked loop in the integrated circuit; so that the control terminal turns off the phase-locked loop in the latch-up test mode.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, where the step of establishing an association relationship between the control end and an I/O port in an integrated circuit includes:
setting a control variable related to an input of a control terminal, and using the control variable to control a selector to close an output enabling terminal of the I/O port when the control terminal meets the set condition of entering the latch-up test mode.
In a second aspect, an embodiment of the present invention further provides a latch-up testing method for an integrated circuit, including:
when the condition that the input of the control end meets the set condition of entering the latch-up test mode is detected, the rest ports except the reset port in the integrated circuit are controlled to enter the latch-up test mode according to the input of the control end;
and in the latch-up test mode, controlling the integrated circuit to operate so as to complete the latch-up test.
With reference to the second aspect, an embodiment of the present invention provides a first possible implementation manner of the second aspect, wherein the step of controlling remaining ports of the integrated circuit except for the reset port to enter a latch-up test mode includes:
a pull-up resistor circuit and a pull-down resistor circuit that turn off an I/O port in the integrated circuit;
closing an output enabling end of an I/O port in the integrated circuit;
closing an analog circuit module connected with an I/O port in an integrated circuit, and enabling the I/O port connected with the analog circuit module to be in a high-impedance state;
a phase locked loop in the integrated circuit is turned off.
With reference to the first possible implementation manner of the second aspect, an embodiment of the present invention provides a second possible implementation manner of the second aspect, where the step of turning off an output enable terminal of an I/O port in an integrated circuit includes:
and controlling a selector to close an output enabling end of the I/O port by adopting a control variable.
The embodiment of the invention has the following beneficial effects:
according to the integrated circuit design method and the integrated circuit latch-up test method provided by the embodiment of the invention, the control end of the latch-up test mode is arranged for the integrated circuit, the control end is utilized to control the state of the port of the integrated circuit in the latch-up test mode, the controllability of signals inside the circuit is increased, the requirement of L atch up test can be better met, the latch-up resistance of the circuit can be objectively and accurately evaluated, and the quality of devices is ensured.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of an internal structure of a CMOS chip;
FIG. 2 is a schematic circuit diagram of a parasitic transistor forming an SCR (silicon controlled rectifier);
FIG. 3 is a flowchart of an integrated circuit design method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an I/O port as an input or output in an integrated circuit;
FIG. 5 is a schematic circuit diagram of a control variable controlling an output enable of an I/O port via a selector;
FIG. 6 is a flowchart illustrating an integrated circuit latch-up testing method according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With the increasing complexity of integrated circuits, L atch up is more and more likely to occur, L atch up is generated according to the principle shown in fig. 2, in which Q1 is a vertical PNP transistor, the base is nwell, the gain from the base to the collector can be hundreds of times, Q2 is a side NPN transistor, the base is P substrate, the gain from the base to the collector can be tens of times, Rwell is parasitic resistance of nwell, Rsub is parasitic resistance of P substrate, Q1, Q2, Rwell, and Rsub form a Silicon Controlled Rectifier (SCR) circuit, when no external disturbance and no triggering are caused, the two transistors are in an off state, the collector current is a reverse leakage current of C-B, the current gain is very small, at this time, L atch up does not occur, when the triggering current reaches the base of Q2, the current flowing through Rsub resistor Rsub causes a voltage drop on the Rsub resistor, if Q2 is reached, the emitter junction of the transistor turns on, the transistor turns on the transistor on, the transistor turns on the collector resistance of the transistor on, the transistor turns on the transistor, the transistor Q9 causes a voltage drop on the voltage of the rsup, the transistor is further, the transistor reaches the collector resistance of the transistor, the transistor Q9, the transistor reaches the collector resistance of the transistor, the transistor reaches the transistor, the transistor reaches the transistor, the.
The L atch up is generated mainly because when the chip starts to work, enough current is generated in parasitic capacitance between nwell and Psubstrate due to VDD change, L atch up is generated when the VDD change rate is large to a certain degree, large current is generated in the chip when the signal change of an I/O pin exceeds the range of VDD-GND, the thyristor is triggered, a small amount of charged carriers are introduced into nwell or P substrate from protective current during electrostatic pressurization in the electrostatic discharge process, the thyristor is triggered, and when a plurality of drivers act simultaneously, VDD and GND change suddenly due to overlarge load, one transistor in the thyristor can be turned on, and L atch up is caused.
Because the trigger mechanism of L atch up is complicated and has various inducing reasons, it is difficult to avoid it by simple safety calculation or simple process measures, therefore, the L atch up effect is a potentially serious problem that always and continuously affects the reliability of the CMOS device.
Therefore, L atch up test needs to be performed on the integrated circuit, and due to the complexity of the integrated circuit, when L atch-up test is performed on the circuit, interference of undesired signals, such as interference of leakage currents, such as pull-up current, pull-down current, output current of an I/O port and the like, is likely to exist, so that L atch up test is inaccurate, and whether L atch up occurs in the circuit cannot be accurately judged.
Example one
The embodiment provides an integrated circuit design method, which adds testability design aiming at L atch up test in the integrated circuit design stage, wherein the method is mainly designed according to the principle of L atch up effect generation and the L atch up test method, because L atch up effect is mainly concentrated on I/O pins, when the testability design of L atch up is carried out, the integrated circuit is required to meet the following conditions:
condition 1 all pins and input-output related modules except the control pin and reset pin of the latch-up test mode should support L atch up test mode.
Condition 2: the pull-up resistance circuit and the pull-down resistance circuit of the I/O pin are directly controlled by a control pin in a latch-up test mode and do not depend on other conditions. When entering the latch-up test mode, the pull-up resistance circuit and the pull-down resistance circuit of all the I/O pins are turned off.
In general, the leakage current generated in the non-latch-up state is much smaller than the static current generated by the pull-up resistor circuit and the pull-down resistor circuit. If the pull-up resistor circuit and the pull-down resistor circuit inside the I/O pin are not turned off, the latch up test may not pass, and the current value obtained by the test cannot truly reflect whether the latch up condition occurs or not.
Condition 3, the enable terminals (output enable) on the output paths of all I/O pins are to be turned off in the L atch up test mode, and the input paths of the I/O pins may not be controlled.
As shown in fig. 4, when IO is used as an output, TN is 1, a is a set logic value, and when a is 1, the MOS transistors from GND to IO are turned on; when A is 0, the MOS tube from VCC to IO is opened. Therefore, if TN is 1, a current flows to IO regardless of whether a is 0 or 1.
When IO serves as input, when TNI is equal to 1, IO is a set logic value, and when IO is equal to 1, MOS (metal oxide semiconductor) tubes from VCC to ZI are opened; when IO is 0, the MOS tube from GND to IO is opened. Therefore, no matter IO is 0 or 1, as long as TNI is 1, a current flows to ZI.
When performing the latch up test, it is necessary to measure the leakage current of the I/O pin, so that when IO is input, even if TNI is 1, the current flows inside the chip, and the measurement of the leakage current of the I/O pin is not affected. When IO is used as an output, when TN is 1, a current flows to IO, which affects the measurement of the leakage current of the I/O pin. Thus, in the latch up test mode, the drive on the output path of the I/O pin needs to be turned off.
Condition 4: for a serial-parallel conversion module and a parallel-serial conversion module which are connected with an I/O port in an integrated circuit, in a latchup test mode, the serial-parallel conversion module and the parallel-serial conversion module need to be closed, and the I/O port related to the closing of the serial-parallel conversion module and the parallel-serial conversion module is in a high impedance state.
Condition 5. in the latch up test mode, all P LL (Phase L ocked L oop ) modules need to be turned off.
As shown in fig. 3, in order to make the designed integrated circuit satisfy the above 5 conditions, the integrated circuit design method provided in this embodiment adds the following steps, or includes the following steps, in the integrated circuit design stage:
in step S301, a designated port is selected from the integrated circuit as a control terminal for the latch-up test mode.
Generally, when designing an integrated circuit, several test pins, or test ports, are reserved for different test experiments. One port can be selected from reserved test ports of the integrated circuit as a control end of the latch-up test mode, and a plurality of ports can be selected from reserved test ports of the integrated circuit as control ends of the latch-up test mode. If no suitable test pins are reserved in the integrated circuit, additional test pins can be added to the integrated circuit, and then the control terminal of the latch-up test mode can be selected from the additional test pins.
When a port is selected as the control terminal of the latch-up test mode, the port may be set to enter the latch-up test mode when the port is at a high level, or to enter the latch-up test mode when the port is at a low level. When a plurality of designated ports are selected as control terminals of the latch-up test mode, the integrated circuit enters the latch-up test mode when the combinational logic of the ports meets the set conditions. For example, if three ports P1, P2, and P3 are selected as control terminals for the latchup test mode, it can be set that the integrated circuit enters the latchup test mode when all three ports are high. Of course, other combinational logic conditions may be set as a trigger condition for the integrated circuit to enter the latch-up test mode.
Step S302, establishing an association relationship between the control end and the remaining ports of the integrated circuit except the reset port, so that the control end controls the states of the remaining ports in the latch-up test mode.
Except for the control pin and the reset pin of the latch-up test mode, all the pins and the modules related to the input and output should support L atch up test mode (hereinafter, the pins and the modules related to the input and output are collectively referred to as ports).
Establishing an incidence relation between a control end and an I/O port in an integrated circuit, so that the control end turns off a pull-up resistor circuit and a pull-down resistor circuit of the I/O port in a latch-up test mode, and turns off an output enabling end of the I/O port;
establishing an incidence relation between a control end and an analog circuit module connected with an I/O port in an integrated circuit, so that the control end closes the analog circuit module in a latch-up test mode and the I/O port connected with the analog circuit module is in a high-impedance state; the analog circuit module comprises a serial-parallel conversion module, a parallel-serial conversion module and other transmission mode conversion modules;
establishing an incidence relation between a control end and a phase-locked loop in an integrated circuit; so that the control terminal turns off the phase-locked loop in the latch-up test mode.
Specifically, the establishing of the association relationship between the control terminal and the I/O port in the integrated circuit includes establishing the association relationship between the control terminal and a pull-up resistor circuit and a pull-down resistor circuit of the I/O port, and establishing the association relationship between the control terminal and an output enable terminal of the I/O port.
When the association relationship between the control terminal and the pull-up resistor circuit and the pull-down resistor circuit of the I/O port is established, the control terminal can be directly associated with the pull-up resistor circuit and the pull-down resistor circuit of the I/O port in the integrated circuit. For example, when all three ports P1, P2, and P3 are high, the pull-up resistor circuit and the pull-down resistor circuit of the I/O port are turned off. The association between the control terminal and the pull-up resistor circuit and the pull-down resistor circuit of the I/O port in the integrated circuit may also be established by setting the control variable.
The control terminal can be directly associated with the output enable terminal of the I/O port in the integrated circuit when the association relationship between the control terminal and the output enable terminal of the I/O port is established, for example, when all three ports P1, P2 and P3 are high, the output enable terminal of the I/O port is turned off, or a control variable is set to establish the association between the control terminal and the output enable terminal of the I/O port in the integrated circuit, for example, as shown in fig. 5, a control variable L U mode2 and L U mode2 associated with the input of the control terminal are set to control the output of the selector, when the control terminal is in a Normal use state, L U mode2 is equal to 0, TN (output enable terminal) is connected to the terminal by the selector, and when the control terminal meets the set condition for entering the latch effect test mode, L U mode2 is equal to TN 1, 5391 is equal to TN 2, i.e., when the control terminal is connected to the output enable terminal 6851, i.e., when the control terminal is connected to the integrated circuit 0.
When the association relationship between the control terminal and the analog circuit module in the integrated circuit is established, the control terminal and the analog circuit module in the integrated circuit can be directly associated. For example, when all three ports P1, P2 and P3 are high, the analog circuit module is turned off. The association between the control terminal and the analog circuit module can also be established by setting a control variable.
When the incidence relation between the control end and the phase-locked loop in the integrated circuit is established, the control end can be directly associated with the phase-locked loop in the integrated circuit. For example, when all three ports P1, P2, and P3 are high, the phase locked loop is turned off. The association between the control terminal and the phase-locked loop can also be established by setting a control variable.
When the integrated circuit designed by the integrated circuit design method provided by the embodiment is used for performing the latch-up test, the control end of the integrated circuit controls the port of the integrated circuit to work in the latch-up test mode, so that the controllability of signals inside the circuit is improved, the internal interference current is reduced, the requirement of L atch up test can be better met, the latch-up resistance of the circuit can be objectively and accurately evaluated, and the quality of devices is ensured.
Example two
In correspondence with the first embodiment, the present embodiment provides a method for testing latch-up of an integrated circuit, as shown in fig. 6, the method includes:
step S601, when the input of the control end is detected to meet the set condition of entering the latch-up test mode, the rest ports except the reset port in the integrated circuit are controlled to enter the latch-up test mode according to the input of the control end;
step S602, in the latch-up test mode, the integrated circuit is controlled to operate to complete the latch-up test.
The step of controlling the rest ports except the reset port in the integrated circuit to enter the latch-up test mode comprises the following steps:
a pull-up resistor circuit and a pull-down resistor circuit that turn off an I/O port in the integrated circuit;
closing an output enabling end of an I/O port in the integrated circuit; the selector can be controlled to close the output enabling end of the I/O port by adopting a control variable;
closing an analog circuit module connected with an I/O port in the integrated circuit, and enabling the I/O port connected with the analog circuit module to be in a high-impedance state;
a phase locked loop in the integrated circuit is turned off.
And after the interference signal source is closed, carrying out latch-up test in a latch-up test mode.
According to L atchup principle, after the circuit enters L atch up state, the current on the power line will increase sharply, and finally the circuit is burnt out, so L atch up test has the main principle that interference current pulse or voltage pulse is applied to each pin of the circuit to simulate various possible situations of the circuit L atch-up in actual use, and whether the circuit enters L atch up state is judged according to the change of the current on the power line, the specific steps are as follows:
firstly, providing corresponding level for a control terminal according to the combinational logic condition of the control terminal set in the integrated circuit design method. For example, if the integrated circuit design method sets the three control ports to all be high level as the condition for entering the latch-up test mode, the three control ports are provided with high level to make the integrated circuit enter the latch-up test mode.
And secondly, sequentially testing all I/O pins of the integrated circuit under the following four conditions.
Setting all I/O pins as working voltage, sometimes 10% higher, measuring current value I1. of the I/O pin to be measured, adding overvoltage for a short time and 1.5 times of working voltage on the I/O pin to be measured, then returning to the working voltage, measuring current value I2 at the moment, if (I2> I1 x 1.4) or (I2> I1+100ma) is met, judging that L atch up effect occurs in the circuit, and L atch up test fails.
And secondly, setting other I/O pins as working voltages, sometimes increasing by 10%, biasing the I/O pin to be tested by 0v, measuring the current value I1. of the I/O pin to be tested, adding overvoltage for a short time, namely 1.5 times of working voltage, on the I/O pin to be tested, returning to 0v, measuring the current value I2 at the moment, and if the current value I2, I1, 1.4 or (I2, I1 and 100ma) is met, judging that the circuit generates L atch up effect, and the L atch up test fails.
Setting other I/O pins to be 0v, setting the I/O pin to be tested to be working voltage, measuring the current value I1. of the I/O pin to be tested, adding overvoltage for a short time and working voltage which is 1.5 times of the overvoltage on the I/O pin, then returning to the working voltage, measuring the current value I2 at the moment, and if (I2> I1 x 1.4) or (I2> I1+100ma) is met, judging that the circuit generates L atch up effect, and L atch up test fails.
Setting all the I/O pins to be 0v, measuring the current value I1. of the I/O pin to be measured, adding overvoltage for a short time on the I/O pin to be measured, the working voltage is 1.5 times, then returning to 0v, measuring the current value I2 at the moment, and if (I2> I1 x 1.4) or (I2> I1+100ma) is met, judging that the circuit generates L atch up effect, and L atch up test fails.
And thirdly, testing each group of power supply pins under the following two conditions.
And a test condition V, setting all the I/O pins to be working voltage, sometimes 10% higher, measuring the current value I1. of the test power supply pin plus the working voltage which is 1.5 times of the short time, then switching back to the working voltage, measuring the current value I2 at the moment, and if (I2> I1 x 1.4) & (I2> I1+100ma) is met, judging that the L atch up effect occurs in the circuit, and the L atchup test fails.
Test conditions six are that all I/O pins are set to 0v, the current value I1. of the test power supply pin is measured plus an operating voltage 1.5 times the operating voltage for a short period of time, and then switched back to the operating voltage, the current value I2 at this time is measured, if (I2> I1 x 1.4) & (I2> I1+100ma) is satisfied, it is determined that L atch up effect has occurred in the circuit, and L atch up test fails.
In order to save Test time, L atch up Test can also be performed under ATE (Automatic Test environment). when the Test is performed under the ATE environment, latch up latch-up effect of all I/O pins is not generally tested, and Static IDD (Static leakage current) is measured by using L atch up Test mode, so-called SIDD (Static leakage current) is to enter L atch up Test mode, and then leakage current on the power supply pins is measured, which reflects leakage current of all I/O pins and internal circuits in the power supply control region.
L atch up test mode just satisfies this state, all I/O pins have no output current, and many circuit blocks are in a power-only reset state, which can also be understood by testing SIDD, the test steps are as follows:
firstly, providing corresponding level for a control terminal according to the combinational logic condition of the control terminal set in the integrated circuit design method. For example, if the integrated circuit design method sets the three control ports to all be high level as the condition for entering the latch-up test mode, the three control ports are provided with high level to make the integrated circuit enter the latch-up test mode.
And secondly, testing the current of each power supply pin as the SIDD current under the normal voltage.
When ATE L atch up test is carried out, special requirements are not required, only the SIDD of the power control area can be tested, the SIDD of an I/O pin cannot be tested, and only the SIDD of the power control area can be tested during mass production.
The pass/fail criteria for the SIDD test is a variable number. The standard of ATE is that chips of each project are produced, and pass/fail standards are determined by using some determined good chips, and generally the range is determined more loosely and is compared with the empirical values of other projects.
The integrated circuit design method and the integrated circuit latch-up test method provided by the embodiment of the invention have the same technical characteristics, so the same technical problems can be solved, and the same technical effect can be achieved.
It should be noted that, in the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments provided by the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (5)
1. A method of designing an integrated circuit, comprising:
selecting a designated port from the integrated circuit as a control end of a latch-up test mode;
establishing an incidence relation between the control end and the rest ports except the reset port in the integrated circuit, so that the control end controls the states of the rest ports in a latch-up test mode;
the step of establishing an association relationship between the control terminal and the remaining ports of the integrated circuit except the reset port includes:
establishing an incidence relation between the control end and an I/O port in an integrated circuit, so that the control end turns off a pull-up resistor circuit and a pull-down resistor circuit of the I/O port in a latch-up test mode, and turns off an output enabling end of the I/O port;
establishing an incidence relation between the control end and an analog circuit module connected with an I/O port in the integrated circuit, so that the control end closes the analog circuit module in a latch-up test mode and the I/O port connected with the analog circuit module is in a high-impedance state;
establishing an incidence relation between the control end and a phase-locked loop in the integrated circuit; so that the control terminal turns off the phase-locked loop in the latch-up test mode.
2. The method of claim 1, wherein selecting the designated port from the integrated circuit as the control terminal for the latchup test mode comprises:
selecting a plurality of appointed ports from an integrated circuit as control ends of a latch-up test mode; when the combinational logic of the plurality of ports meets the set condition of entering the latch-up test mode, the integrated circuit enters the latch-up test mode.
3. The method of claim 1, wherein the step of establishing the association between the control terminal and the I/O port in the integrated circuit comprises:
setting a control variable related to an input of a control terminal, and using the control variable to control a selector to close an output enabling terminal of the I/O port when the control terminal meets the set condition of entering the latch-up test mode.
4. A method for testing latch-up of an integrated circuit, comprising:
when the condition that the input of the control end meets the set condition of entering the latch-up test mode is detected, the rest ports except the reset port in the integrated circuit are controlled to enter the latch-up test mode according to the input of the control end;
under the latch-up test mode, controlling the integrated circuit to operate so as to complete the latch-up test;
the step of controlling the rest of the integrated circuit except the reset port to enter the latch-up test mode comprises the following steps:
a pull-up resistor circuit and a pull-down resistor circuit that turn off an I/O port in the integrated circuit;
closing an output enabling end of an I/O port in the integrated circuit;
closing an analog circuit module connected with an I/O port in an integrated circuit, and enabling the I/O port connected with the analog circuit module to be in a high-impedance state;
a phase locked loop in the integrated circuit is turned off.
5. The method of claim 4, wherein the step of turning off the output enable of the I/O port in the integrated circuit comprises:
and controlling a selector to close an output enabling end of the I/O port by adopting a control variable.
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| CN100395555C (en) * | 2004-08-19 | 2008-06-18 | 信息产业部电子第五研究所 | Latching effect detecting method for CMOS circuit |
| US7474011B2 (en) * | 2006-09-25 | 2009-01-06 | Integrated Device Technologies, Inc. | Method for improved single event latch up resistance in an integrated circuit |
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