JP3262651B2 - Latch-up resistance evaluation method for CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating the latch-up resistance of a CMOS semiconductor integrated circuit device.

[0002]

2. Description of the Related Art As shown in FIG. 1, an N-type well 4 and a P-type well 4 are formed on a surface of a P-type silicon substrate 2 in order to evaluate the latch-up resistance of a CMOS type semiconductor integrated circuit device other than a product.
Forming wells 6 are formed so that boundaries 5 are in contact with each other. P-type diffusion region 10 is formed in N-type well 4 and N-type diffusion region is formed in P-type well 6 with field oxide film 8 on boundary 5 between both wells. In each of the wells 4 and 6, an element having contact diffusion regions 14 and 16 is formed. Using this device, the switching current or holding current of the parasitic thyristor is measured to evaluate the latch-up resistance.

A specific method is as follows. In FIG. 1A, the contact region 14 of the N type well 4 is
c, by connecting the contact region 16 of the P-type well 6 to the low voltage side power supply potential GND (Vss), connecting the N-type diffusion region 12 to GND, and applying a voltage of Vcc or higher to the P-type diffusion region 10 As the current is injected, the amount of the injected current with respect to the applied voltage is measured as shown in FIG. The current value Is that causes snapback as shown in FIG. 2A is referred to as a switching current. The higher the switching current value Is, the higher the latch-up resistance. Instead of the switching current Is, a holding current can be measured to evaluate the latch-up resistance. The switching current (same for the holding current) is related to the distances X and Y from the boundary 5 between the two wells to the diffusion regions 10 and 12, but mainly depends on the distance X when the current is injected from the P-type diffusion region 10, The switching current decreases as X becomes shorter.

Further, the contact region 14 is set to a Vcc potential,
When the contact region 16 is fixed at the GND potential, the P-type diffusion region 10 is fixed at the Vcc potential, and the potential of the N-type diffusion region 12 is lowered from GND, and the current is drawn from the N-type diffusion region 12. The same result as that of FIG. At this time, the applied voltage becomes negative. When a current is extracted from the N-type diffusion region 12, the current mainly depends on the distance Y, and the smaller the Y, the smaller the switching current.

When the switching current is measured while changing X and Y in this manner, a result as shown in FIG. 2B is obtained. If the lower limit value of the switching current is determined according to the purpose of the device, the minimum value of X and Y can be obtained from the measurement result of FIG. For example, the lower limit of the switching current is 1 m
If A is determined, it can be seen from the results of FIG. 2B that the minimum values of the distances X and Y are each about 1 μm.

[0006]

Since the latch-up resistance of all the various devices of the CMOS type semiconductor device is evaluated using the measurement pattern shown in FIG. 1, the result may not be appropriate depending on the device. Accordingly, it is an object of the present invention to provide a method for evaluating latch-up resistance using a circuit pattern closer to an actual device.

[0007]

When the present invention is applied to the evaluation of the latch-up resistance of a CMOS inverter circuit,
With the input gate at the low-voltage power supply potential, the output gate at the high-voltage power supply potential, and the source electrode of the NMOS transistor at the low voltage power supply potential, a current is injected from the source electrode of the PMOS transistor to switch or hold current. With the input gate set to the high voltage side power supply potential, the output gate set to the constant voltage side power supply potential, and the source electrode of the PMOS transistor set to the high voltage side power supply potential, current is drawn from the source electrode of the NMOS transistor. Measuring the switching current or the holding current.

When the present invention is applied to the evaluation of the latch-up resistance of a CMOS type SRAM memory cell, the gates of the flip-flops of the SRAM memory cell are connected in common, the bit line and the opposite bit line are connected in common, and the word line is connected. A high-voltage power supply potential is applied to the bit line and the gate is set to the low-voltage power supply potential, and the source electrode of the NMOS transistor of the flip-flop is set to the low-voltage power supply potential. Measuring the switching current or the holding current by injecting a current from the NMOS transistor of the flip-flop with the gate at the high voltage side power supply potential and the source electrode of the flip-flop PMOS transistor at the high voltage side power supply potential. Extract current from source electrode And a step of measuring the switching current or holding current, the.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to the evaluation of latch-up resistance of a CMOS inverter circuit will be described. FIG. 3 shows C
In this figure, a parasitic transistor and a parasitic resistance are written in a MOS inverter circuit. An N-type well 22 and a P-type well 24 are formed on a P-type silicon substrate 20 so as to be in contact at a boundary 26. 27 is a field oxide film for element isolation;
8 is a channel stop layer.

In the N-type well 22, a PMOS transistor is formed, and the source region 30 is formed by a P-type diffusion region.
A polysilicon gate electrode 34 is formed on a channel region between drain and drain region 32 via a gate oxide film. 36 is a contact region of the well 22. An NMOS transistor is formed in the P-type well 24,
Source region 40 and drain region 42 by N-type diffusion region
A polysilicon gate electrode 44 is formed on a channel region between the gate electrodes via a gate oxide film. 46 is well 2
4 is a contact area.

The gate electrodes 34 and 44 are connected to each other to form an input gate, and the drain regions 32 and 42 are connected to each other to form an output gate. The N-type well 22 is applied with the high-voltage side power supply potential Vcc via the contact region 36, and the P-type well 24 is connected via the contact region 46 to the low-voltage side power supply potential GND which is the substrate potential Vss. .

The drain region 32 of the PMOS transistor
And the distance between the drain region 42 of the NMOS transistor and the well boundary 26 is Y. FIG. 4 shows only a transistor and a resistor parasitic on this inverter circuit.

In order to evaluate the latch-up resistance in the present invention, a switching current when a current is injected into the parasitic transistor VT1 is measured. For that, NMO
In order to fix the source region 40 of the S transistor to the potential Vss and forcibly turn on the PMOS transistor and turn off the NMOS transistor, Vin is set to V
Connect the ss terminal and Vout to the Vcc terminal. In this state, the potential of the source region 30 of the PMOS transistor is set to Vc
The current is injected from the source region 30 by increasing the height from c. At this time, the current injected into the source region 30 is the transistor VT1 → the resistance Rs4 → Rs3 → Rs2 → Rs
Flow through one. Since Rs1 is a shunt resistance between the base and the emitter of the transistor LT1, when the current increases and the voltage drop due to the resistance Rs1 increases, the transistor LT1 is turned on to enter the latch-up mode. The switching current at the time of the latch-up mode is measured. In the measurement of the switching current under this condition, both the distances X and Y act. However, since the dependence on the distance X is particularly large, an element in which the distance X is changed while keeping the distance Y constant at 1.4 μm is prepared. The result of measuring the current is shown in the left part of FIG.

As an evaluation of the latch-up resistance of the inverter circuit shown in FIG.
The switching current when the current is extracted from is also measured. In this measurement, Vin is connected to the Vcc terminal and Vout is connected to the Vss terminal in order to forcibly turn off the PMOS transistor and forcibly turn on the NMOS transistor. Then, the potential of the source region 30 of the PMOS transistor is fixed at Vcc, and the potential of the source region 40 of the NMOS transistor is lowered from Vss, thereby drawing a current from the source region 40 and measuring the switching current at that time. At this time, the current is Rw in the circuit of FIG.
It flows through 1 → Rw2 → Rw3 → LT1. Since Rw1 is a shunt resistance between the base and the emitter of the transistor VT1, if the voltage drop due to the resistance Rw1 increases, VT1 is turned on, and a latch-up mode is set. Latch-up resistance when current is drawn from the source region 40 depends on both the distances X and Y.
Is large, and the result of measuring a switching current by preparing an element in which X is fixed at 1.1 μm and Y is changed is shown in the right part of FIG.

According to the results of FIG. 5 in which the switching current is measured as described above, the switching current is 2.5
If mA or more is required, it can be defined that X is 0.8 μm and Y is 1.0 μm, respectively.

The present invention relates to a 6-transistor type CMOS.
An embodiment applied to the evaluation of the latch-up resistance of a type SRAM memory cell will be described. FIG. 6 shows an SRAM memory cell, and FIG. 6A shows a normal memory cell. For it,
In the memory cell for latch-up resistance evaluation according to the present invention, the gates of the flip-flops are commonly connected by a wiring 50, and the bit line and the opposite bit line are commonly connected by a wiring 52, as shown in FIG. . FIG. 7 is a plan view of the evaluation memory cell of FIG. 6B.

FIG. 8 is a sectional view taken along the line AA 'in FIG. In FIG. 8, an N-type well 6 is formed on a P-type silicon substrate 60.
2 and a P-type well 64 are formed in contact with a boundary 66. The distance between the source region 70 of the PMOS transistor formed in the N-type well 62 and the boundary 66 of the well is defined as X, and the distance between the source region 74 of the NMOS transistor formed in the P-type well 64 and the boundary 66 of the well is defined as Y. And Reference numeral 72 denotes a contact region of the N-type well 62, and reference numeral 76 denotes a contact region of the P-type well 64. 80 is a field oxide film for element isolation, and 82 is a channel stop layer. FIG. 9 shows the parasitic transistor and the parasitic resistance in FIG.

To evaluate the latch-up resistance with respect to the distances X and Y, the contact region 72 of the N-type well 62 is connected to the Vcc terminal, the contact region 76 of the P-type well 64 is connected to the Vss terminal, The line WL and the bit line are connected to the Vcc terminal. The gate wiring 50 is Vc
The potential is fixed by connecting to the c terminal or the Vss terminal.

The source region 76 of the NMOS transistor is fixed at the potential Vss, the potential of the source region 70 of the PMOS transistor is set higher than Vcc, and a current is injected from the source region 70 to measure a switching current. When a current is injected from the source region 70, the current is Tr1 → Rs
2 → The current flows through Rs1, and when the voltage drop due to Rs1 increases, the transistor Tr2 is turned on to enter the latch-up mode. The latch-up resistance depends on both the distances X and Y. In particular, in this case, since the distance Y greatly depends on the distance X, the distance Y is fixed at 1.4 μm and the distance X is changed.
The result of measuring the magnitude of the switching current with respect to the distance X by creating a RAM memory cell is shown on the left side of FIG.

Next, the source region 70 of the PMOS transistor is fixed at the Vcc potential, and the source region 74 of the NMOS transistor is lowered from the Vss potential to draw a current from the source region 74 and measure the switching current. At this time, the current is Rw1 → Rw2 → Tr2
Flows through the transistor and when the voltage drop of Rw1 increases, Tr1
Is turned on to enter the latch-up mode. In the mode in which the current is drawn from the source region 74, the dependence on the distance Y is large, so the distance X is fixed at 1.1 μm and the distance Y
The results of measuring the switching current by preparing an element having a different value are shown on the right side of FIG.

According to the results shown in FIG. 10, if the minimum value of the switching current is, for example, 1 mA, X is 0.5 μm, and Y is 0.5 μm.
Can be defined as 0.7 μm being the minimum value.
The present invention is not limited to the twin-tub type CMOS semiconductor device shown in the embodiment, but may be an N-well type or P-well type CMOS device.
The present invention can be applied to an S-type semiconductor device.

[0022]

According to the evaluation method of the present invention, the latch-up resistance can be directly measured by the switching current or the holding current in the CMOS inverter circuit, and the minimum value of the interval between the N-type diffusion region and the P-type diffusion region can be measured. Can be determined. Even when the present invention is applied to an SRAM memory cell, the minimum value of the interval between the N-type diffusion region and the P-type diffusion region is determined by measuring the switching current or the holding current of the cell itself in the same manner. Can be.

[Brief description of the drawings]

FIG. 1 is a view showing an element for evaluating latch-up resistance of a conventional CMOS semiconductor device, wherein FIG.
(B) is a plan view.

FIGS. 2A and 2B show a method for evaluating latch-up resistance, in which FIG. 2A shows a switching current and a holding current, and FIG. 2B shows an X and Y dependency of the switching current in FIG. is there.

FIG. 3 is a sectional view of a semiconductor device when the present invention is applied to the evaluation of a CMOS inverter.

FIG. 4 is a circuit diagram showing a parasitic circuit in the embodiment of FIG.

FIG. 5 shows X and Y of a switching current according to the embodiment of FIG. 3;
It is a figure which shows dependency.

6A and 6B are diagrams showing a CMOS type SRAM memory cell, in which FIG. 6A is a circuit diagram showing a normal memory cell, and FIG. 6B is a circuit diagram showing an evaluation memory cell according to the present invention.

FIG. 7 is a plan view of the memory cell of FIG. 6B.

8 is a cross-sectional view taken along the line AA 'in FIG.

FIG. 9 is a circuit diagram showing a parasitic circuit in the embodiment of FIG. 7;

FIG. 10 is a diagram showing X and Y dependence of a switching current in the embodiment of FIG. 7;

[Explanation of symbols]

 26 Well boundary 30, 32, 70 P-type diffusion region 40, 42, 74 N-type diffusion region XP Distance from P-type diffusion region to well boundary Y Distance from N-type diffusion region to well boundary

Claims (2)

(57) [Claims] An input gate of a CMOS inverter circuit has a low-voltage power supply potential, an output gate has a high-voltage power supply potential,
A step of measuring a switching current or a holding current by injecting a current from the source electrode of the PMOS transistor with the source electrode of the NMOS transistor being at the low voltage side power supply potential; A step of extracting a current from the source electrode of the NMOS transistor and measuring a switching current or a holding current in a state where the constant voltage side power supply potential and the source electrode of the PMOS transistor are set to the high voltage side power supply potential. Latch-up resistance evaluation method. 2. A CMOS type SRAM memory cell, wherein the gates of flip-flops are commonly connected, the bit line and the reciprocal bit line are commonly connected, and a high voltage side power supply potential is applied to the word line and the bit line. The gate is connected to the low-voltage side power supply potential and the flip-flop N
A step of measuring a switching current or a holding current by injecting a current from the source electrode of the PMOS transistor of the flip-flop with the source electrode of the MOS transistor being at the low power supply potential; P
A step of extracting a current from the source electrode of the NMOS transistor of the flip-flop and measuring a switching current or a holding current with the source electrode of the MOS transistor at the high voltage side power supply potential, and measuring the latch-up resistance. Method.