JPH07235608A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To select a standby current by a method wherein a signal is given from an outer terminal, and a depletion type MOS transistor is operated as an enhancement type MOS transistor by changing threshold voltage. CONSTITUTION:A power supply terminal 3A and a power supply side control terminal 3B are provided on an N-well 2A, and a ground terminal 4A and a ground side control terminal 4B are provided on a P-well 2B. Accordingly, the potential of power feeding of the P-well 2A can be controlled by either of the power supply side control terminal 3B and the ground side control terminal 4B in this constitution. As the potential of the well is separated from the power supply and the ground and it can be controlled by an external terminal, the threshold voltage (Vth) can be controlled by the substrate effect of a MOS Tr, a depletion type MOS Tr can be operated as an enhancement MOS Tr, and a standby current selection can be performed by suppressing the standby current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device using a depletion type MOS transistor (Tr) (including Tr having a low threshold voltage Vth) in order to speed up the operation, and particularly to an external terminal at the time of selection. The threshold voltage Vth is changed by applying a signal from the depletion type M
The present invention relates to a semiconductor integrated circuit device in which an OSTr (low Vth) is operated as an enhancement type MOSTr to enable a standby current Idds test.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit device such as a VLSI has been highly integrated, and various methods for improving the driving capability of a transistor have been proposed. One of them is the reduction of Vth. A MOS device with a reduced Vth can be realized as a normally-on (depletion type) MOSTr by designing a circuit to realize a high-speed LSI.

[0003]

The present inventor has found the following problems as a result of studying the conventional semiconductor integrated circuit device.

In an integrated circuit using a normally-on (depletion type: including low Vth) MOSTr, the standby current Idds flows in the order of several tens to several hundreds uA during the selection, and the standby current selection (wafer probe inspection) cannot be performed. Standby current selection is an important test item for ensuring the reliability of MOS integrated circuits.

An object of the present invention is to provide a standby current Idds in a high speed depletion type semiconductor integrated circuit device.
An object is to provide a semiconductor integrated circuit device that enables a test.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows.

A semiconductor integrated circuit device using a depletion type MOSTr is provided with means for applying a signal from an external terminal at the time of selection to change the threshold voltage to operate the depletion type MOSTr as an enhancement type MOSTr. .

[0009]

According to the above-mentioned means, the WELL is connected from the external terminal.
Vth is controlled by controlling the potential of the MOSTr by the base effect of the MOSTr, and the normally-on (depletion type: including low Vth) MOSTr is operated as the enhancement-type MOSTr to suppress the standby current Idds and select the standby current. Because I was able to do it,
A standby current Idds test can be performed in a high-speed depletion type semiconductor integrated circuit device.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a plan view showing the structure of a main part of a CMOS inverter which is an embodiment of a depletion type semiconductor integrated circuit device according to the present invention, and FIG. 2 is a sectional view taken along the line AA of FIG. , 1 is a silicon substrate, 2A is N-
WELL (WELL on the power supply side), 2B is P-WELL
(WELL on the ground side), 3A is a power supply terminal (Vdd),
3B is a power supply side control terminal, 4A is a ground terminal,
Reference numeral 4B is a ground side control terminal, 5 is an element isolation insulator (LOCOS), 6 is a gate electrode, 7 is an input terminal, 8 is an output terminal, and X is a contact.

As shown in FIGS. 1 and 2, the CMOS inverter of this embodiment has an N-WELL (WEL on the power supply side).
L) 2A, the power supply terminal (Vdd) 3A and the power supply side control terminal 3B, similarly, P-WELL (ground side WE
LL) 2B is provided with a ground terminal 4A and a ground side control terminal 4B, respectively, so that the power supply potential of the N-WELL 2A can be controlled by at least one of the power supply side control terminal 3B and the ground side control terminal 4B. Has become.

At the time of selection, a normally ON (depletion) MOSTr, which has a low Vth by applying a voltage to at least one of the power supply side control terminal 3B and the ground side control terminal 4B, operates as an enhancement MOSTr. Then, the standby current Idds is suppressed and the standby current selection is performed.

In actual operation, N-WELL on the NMOS side
(WELL on the power supply side) 2A to the ground terminal 4A, PM
By connecting the N-WELL (WELL on the power supply side) 2A on the OS side and the power supply terminal (Vdd) 3A respectively, it is possible to operate in the normal mode.

FIG. 3 shows Vg during the standby current Idds test of the depletion type semiconductor integrated circuit device of this embodiment.
It is a figure showing -Idds characteristic, a solid line is a characteristic curve of this example, and a dotted line is a conventional characteristic curve.

As can be seen from FIG. 3, the conventional Vth point moves in parallel in the 0 direction and becomes smaller, and the standby current Idds becomes larger. For example, if 3.3V is applied to the power supply terminal (Vdd) 3A, 2V is applied to the power supply side control terminal 3B, 0V is applied to the ground terminal 4A, -2V is applied to the ground side control terminal 4B, and the conventional Vth is 0.5V, then The Vth of the invention was 0.1V.

The standby current Idds expressed by the equation 1 is as follows.

[0018]

In Equation 1] Idds = wμCox / L {(Vg -Vth) Vdd-Vdd 2/2} Number 1, Vg is a gate voltage, Vth is the threshold, Vd
d is the power supply voltage, w is 20 μm, μ is 1500 cm ² / VS,
Cox is 384 nF / m and L is 0.5 μm.

The conventional standby current is Idds = wμCo
x / L {(3.3-0.5) 3.3-3.3 2/2} , and the standby current of the present embodiment, Idds = wμCox / L {( 3.
A 3-0.1) 3.3-3.3 ^2/2}. That is, the standby current Idds of this embodiment can be improved by about 35%.

As can be seen from the above description, according to this embodiment, the potential of WELL is set to the power supply and the ground (GND).
Since it is separated from the external terminal and can be controlled from the external terminal, Vth is controlled by the base effect of MOSTr.
Normally ON (depletion type) MOSTr,
By operating as an enhancement MOSTr, the standby current Idds can be suppressed and the standby current can be selected.

Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor.

[0022]

As described above, according to the present invention, the normally ON (depletion type) MOSTr is controlled by controlling the potential of WELL from the external terminal to control the normally ON (depletion type) MOSTr.
By operating as Tr, the standby current can be suppressed and the standby current can be selected.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration of a main part of a CMOS inverter which is an embodiment of a depletion type semiconductor integrated circuit device according to the present invention.

FIG. 2 is a cross-sectional view taken along the line AA of FIG.

FIG. 3 is a diagram showing Vg-Idds characteristics during a standby current Idds test of the CMOS inverter of the present embodiment.

[Explanation of symbols]

1 ... Silicon substrate, 2A ... N-WELL (WE on power supply side)
LL), 2B ... P-WELL (WEL on the ground side)
L), 3A ... Power supply terminal (Vdd), 3B ... Power supply side control terminal, 4A ... Ground terminal, 4B ... Ground side control terminal, 5 ... Element isolation insulator (locos), 6 ... Gate electrode, 7 ... Signal input terminal , 8 ... Signal output terminal, X mark ... Contact, Vdd ... Power supply voltage, Vss ... Reference voltage (ground voltage).

Continuation of the front page (51) Int.Cl. ⁶ Identification code Reference number within the agency FI Technical indication location H01L 21/66 V 7630-4M 27/04 21/822 29/78 9170-4M H01L 27/08 321 B 7514- 4M 29/78 301 J

Claims (1)

[Claims] 1. A semiconductor integrated circuit device using a depletion type MOS transistor, comprising means for applying a signal from an external terminal at the time of selection to change the threshold voltage to operate the depletion type MOS transistor as an enhancement type MOS transistor. A semiconductor integrated circuit device characterized by comprising.