JPS6012787B2 - integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuit devices that require a plurality of different bias sources, and more particularly to integrated circuit devices that require a plurality of different bias sources.
Trasentor is abbreviated as IGFET, hereinafter "FET"
That's what it means.

This invention relates to an integrated circuit device that performs bias biasing in a complementary logic circuit using a novel method. Conventionally, when a complementary FET circuit is integrated into an integrated circuit, a power electrode is required in the well region in addition to the power electrode applied to the circuit board of the wafer, and therefore the pellet is mounted on a base such as a lead frame. Since the external lead is connected to each electrode of the pellet to produce a product, the number of pins inevitably increases as the scale of the integrated circuit increases.

FIG. 1a is a sectional view of a substrate showing an example of a complementary FET circuit, and the substrate 1 uses an N-type wafer. An N-channel FET is formed within a P-type well region 2 formed in this substrate 1, and a P-channel FET is formed outside thereof. In this case, the substrate electrode 3 of the P-channel FET connects the N+ diffusion layer 4 provided as a stopper to the P-F
A power supply Vss is supplied by connecting the source electrode of the ET, while the well electrode 5 of the N-channel FET is connected to the P diffusion layer 6, which is also provided as a stopper, to the N-FE.
Power supply VDo is supplied by connecting it to the source electrode of T. Therefore, in the complementary FET circuit with the above configuration, in addition to the input terminal 7 for the input signal and the output terminal 8, there are a total of four external lead-out terminals: the terminal 3' for the substrate electrode 3 and the terminal 5' for the well electrode 5. It cannot be driven without a lead. Incidentally, FIG. 1b shows an equivalent circuit of the inverter circuit having the above configuration. Currently, semiconductor integrated circuit devices are often used by supplying various power supply voltages to the same chip. Since the number of pins in the circuit increases, it is difficult to use and manufacture.

In other words, pattern design performed for higher level integration must always take into consideration the electrode pads corresponding to the number of pins, which becomes an obstacle in design and also reduces yield.
The disadvantage is that the number of operation tests, etc. increases, and therefore the manufacturing cost increases. Further, on the user side of the integrated circuit device, complications and difficulties arise in use and handling. This invention has been made in view of the above points, and by utilizing the junction capacitance of the PN junction region formed within the integrated circuit board, each element can be connected without increasing the number of electrodes of power supply that must be supplied from the outside. An object of the present invention is to provide an integrated circuit device in which the number of pins is reduced by supplying a bias to the semiconductor device.

An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 2a shows a complementary FE corresponding to the conventional example shown in Figure 1.
FIG. 2B is a sectional view showing a logic circuit made up of T, and an equivalent circuit diagram thereof is shown in FIG. 2B. The substrate 11 is an N type substrate, and a P type well region 12 is formed therein, and a P+ drain 13 and source 14 are provided outside this region 12 to form a P channel FET. Ha, N
+ drain 15 and source 16 are provided to create an N-channel FET. The drain 13 of the above P-FET and N-
The output electrode 17 is connected to the drain 15 of the FET. The source 14 of the P-FET is supplied with the substrate potential Vss from the electrode 19 as a reference potential together with the N+ layer 18 provided as a stopper of this FET. On the other hand, the source 16 of the N-FET is only connected to the P+ layer 20 provided as a stopper by a conductive path 21, and no bias is directly supplied thereto from the outside. Reference numeral 22 designates N10 layers provided in the P-type well region 12, and constitutes a diode 23 shown in the circuit diagram of FIG. 2b.

An electrode 24 is connected to this N+ layer 22 in common with the gate electrodes G and G of the N-FET and P-FET, and an input signal voltage supplied from an input terminal 25 is applied thereto. In the figure, 26 is an output terminal, 27 is a reference power supply terminal, and a capacitor 28 shown by a broken line represents the PN junction capacitance generated between the substrate 11 and the well region 12. Consider the case where the input waveform IN shown in FIG. 3 is applied to the input terminal 25 in the complementary FET circuit having the above configuration.

It is assumed that this input waveform IN is treated as a negative logic with a "1" level as Voo and a "0" level as Vss. Said N
Since the diode 23 connected to the channel FET is in the opposite direction to the input terminal 25, when the input waveform IN is at Voo potential, the capacitor 2
8 is charged through this diode 23. after that,
When the input waveform IN changes to the "0" level, the N-channel FET, which had been off until then, turns on and the potential of the capacitor 28 appears at the output terminal 26. At this moment, a small amount of current 1 flows, causing the above-mentioned The potential of the capacitor 28, that is, the well potential Voo of the well region 12 slightly approaches Vss. However, when the input waveform changes to the "1" level so that the N-channel FET is turned off again, the shortfall in the well potential Voo is charged. Since the input waveform IN is used to supply power instead of the conventional power source Voo, it is only necessary to supply the reference potential Vss from the terminal 27, and this capacitor 28 is connected to an N-channel FET. Since the diffusion capacitance between the well region 12 and the substrate 11 is used for the When designing a logic circuit that requires different bias sources, an electrode terminal that supplies the substrate voltage as the substrate reference potential Vss and an electrode terminal that supplies the substrate voltage as the reference potential Vss
. . (A diode may be provided on the P-channel FET side), and only the terminals for each input signal need to be brought out to the outside, and the design can be easily performed without increasing the number of pins. Note that this invention is based on the above-mentioned complementary FE.
Although this method has a remarkable effect on T circuits, it can also be applied to logic circuits (not limited to inverters) using only N- or P-channel FETs.

However, in order to supply a predetermined voltage to a predetermined position from an input signal source, it is necessary to first create a PN junction in the opposite direction inside the substrate, and then provide a diode thereon. As described above, according to the present invention, ``a logic circuit using FETs that operates with a plurality of different bias sources is operated using a reference voltage and bias obtained from each input signal, so that integrated circuits It is possible to provide an integrated circuit device that can prevent an increase in the number of pins when the number of pins is increased and has many advantages both in terms of circuit design and in actual use.
Figure a is a sectional view showing the structure of a conventional complementary FET circuit, Figure 1b is its equivalent circuit diagram, Figure 2a is an explanatory diagram of an inverter using complementary FETs showing an embodiment of the present invention,
FIG. b is an equivalent circuit diagram thereof, and FIG. 3 is a waveform diagram for explaining the operation of the above embodiment.

1 1... Substrate, 12... Well region, 23... Diode, 25... Input terminal (second electrode), 26... Output terminal, 27...
...・Reference power supply terminal (first electrode), 28....

capacitor. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A first electrode that supplies a first reference potential to the substrate of the integrated circuit, a second electrode group that supplies input signals from the outside to each element of the integrated circuit, and a second electrode group that corresponds to the first reference potential. a diode connected between a well region to which a second reference potential is to be supplied and the second electrode group; An integrated circuit device characterized in that the integrated circuit device is held by a PN junction capacitance between the regions.