JPH02122562A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for making a substrate bias generating circuit and miniaturize an integrated circuit by causing a voltage at the high logic voltage side in an NMOS or a CMOS circuit located on a semiconductor substrate to be supplied directly by a power source terminal and the voltage at its low logic voltage side to be supplied by a step-down circuit and further, the voltage on a P-type semiconductor substrate or at a P-type well in which the NOS of the NMOS or the CMOS circuit is formed to be supplied by a grounding terminal. CONSTITUTION:A power source terminal 3 and a high voltage side of a CMOS circuit in which an NMOS circuit 1 and PMOS circuit 2 are made up are connected through a PMOS 8 and then the low voltage side of the CMOS circuit is connected to the output side of a step-down circuit 4. Further, the P-type semiconductor substrate of the NMOS circuit or a P-type well is connected directly to a connecting terminal 6. This configuration allows the voltage amplitude of a MOS circuit to be expressed by means of a following equation: Amplitude voltage = Voltage VCC of power source- generating voltage V1 of step-down circuit. And then voltage difference between the P-type substrate or the P-type well and the source side of the NMOS circuit is impressed to the NMOS circuit as a substrate bias and its bias is obtained by the following equation: Substrate bias = Grounding voltage VSS-generating voltage VL of step- down circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Application in M Industry) The present invention relates to semiconductor integrated circuits such as dynamic RAM, static RAM, and microprocessors configured with NMOS, PMOS, or CMOS circuits.

(Prior Art) This type of conventional semiconductor integrated circuit will be explained with reference to the main circuit diagram of FIG. 4.

In FIG. 4(a), the semiconductor integrated circuit is composed of a plurality of N-channel MOS transistors (hereinafter referred to as NMOS) or a plurality of P-channel transistors (hereinafter referred to as PMO8) each surrounded by a dashed line. N.M.
O5 circuit and PMOS circuit 2, external power supply voltage vc
A step-down circuit 4 connected to the power supply terminal 3 for supplying an operating voltage several times lower than c, and the NMOS and PM shown in
Low level side of CMOS circuit composed of O8 and NMOS
5, and a substrate bias generation port wI7 for supplying a negative potential to the p-type semiconductor substrate. Note that the output side of the step-down circuit i#34 is connected to the high level side of the CMOS circuit described above via PMOS8.

FIG. 4(b) is a circuit diagram showing the internal configuration of the above-mentioned substrate bias generation circuit 7. The substrate bias generation circuit has a ring oscillator 9 connected to the power supply terminal 3, and two oscillators connected in series. The ring oscillator 9 described above is connected to the middle of NMOSIO and ]1 through an amplifier 12 and a capacitor 13, and the other end of a smoothing capacitor 14 whose one end is grounded is connected to the source of the NMOSII described above, and the p-type +14 described above It consists of a charge pumping circuit connected to a conductive substrate.

(711gl1 to be solved by the invention) However, the step-down circuit 4 and the substrate bias generation circuit 7 described above are
Reducing the junction capacitance with the semiconductor substrate that acts as a load for the NMOS circuit 1 and PMOS circuit 2, reducing the substrate bias effect coefficient, and reducing the dynamic RAM and static R
This is provided to prevent malfunctions caused by injection of electrons into the semiconductor substrate due to signal undershoot, which is a particular problem in AM, and as described above, the substrate bias generation circuit 7 using the charge pumping circuit is From the time the power supply voltage is turned on until the operation stabilizes, the output resistance is extremely high, and since sufficient reverse bias is not applied to the semiconductor substrate, the semiconductor substrate or well becomes almost floating, resulting in latch-up. There was a problem that it was easy to cause There is also the problem that minority carriers generated in the smoothing circuit section of one circuit can also trigger the latch amplifier.

Further, there is a problem in that the current consumption of the ring oscillator 9 and the like for operating the substrate bias generation port M7 is too large for a dynamic RAM circuit that requires low power consumption.

Furthermore, the smoothing capacitor 14 required for the substrate bias generation circuit 7 requires a large area, which poses an obstacle to miniaturization in a dynamic RAM circuit where the semiconductor chip area is limited.

The present invention solves the above problem and provides a semiconductor integrated circuit that does not require the use of the substrate bias generation circuit 7 consisting of a charge pumping circuit.

(Means for Solving Problem R) In order to solve the above problem, the present invention provides that the logic high level voltage of an NMOS or CMOS circuit integrated on a semiconductor substrate is directly supplied from a power supply terminal, Further, the voltage on the low level side is supplied from the step-down circuit formed on the semiconductor substrate, and further.

NMO3 constituting the NMOS circuit or CMOS circuit
The voltage of the p-type semiconductor substrate or P-well formed with is supplied from the ground terminal.

(Function) With the above configuration, the logic high level side of the NM, OS circuit or CMOS circuit is connected to the VCC of the external power supply, and
The low level side is supplied with vL, which is obtained by stepping down the external power supply voltage ■ce with a step-down circuit, and is further supplied with the NMOS p-type semiconductor substrate or P for the above-mentioned NMOS circuit or CMO8 circuit.
- Since the ground voltage V□ which is lower than vL is supplied to the well, the operating voltage of the MOS transistor inside the integrated circuit is equal to the external power supply vce and the stepped-down voltage v1. Therefore, it is reduced. In addition, the external ground V□ and the stepped-down voltage vL, that is, a negative voltage, are applied to the NMOS substrate formed on the p-type semiconductor substrate or P-well, and a substrate bias is applied. This is equivalent to applying a substrate bias without using a substrate bias generation circuit.

(Example) A third example of the present invention will be described with reference to FIGS. 1 to 3.

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention. The difference from the conventional example shown in FIG. 4 is that a power supply terminal 3, an 8M08 circuit 1, and a PMO3 circuit 2 are configured. The high level side of 0MO8, ie, the source of PMOS, is connected via PMOS8, and the low level side of the CMOS, ie, the drain of NMOS, is connected via PMOS8.

There are three points: the point where it is connected to the output side of the step-down circuit 4, and the point where the NMOS p-type semiconductor substrate or P-well is directly connected to the connection terminal 6. Since the rest is the same as the conventional example, the same components are given the same reference numerals and their explanations will be omitted.

With the above configuration, the voltage amplitude of the MO8 circuit is as follows.

It is expressed by the following equation (1).

Amplitude voltage = voltage of power supply vcc - voltage generated by step-down circuit ■,
... (1) On the other hand, between the p-type substrate or P-well and the NM
The potential difference with the source side of the OS is applied to NMO5 as a substrate bias, and the voltage is expressed by the following equation (2) % Formula % Ground voltage for substrate bias v0 - Voltage generated by the step-down circuit VL
...(2) Specifically, the voltage values in the above equations (1) and (2) are determined when the power supply voltage vcc is 5V, the voltage generated by the step-down circuit 4 is 2V, and the applied voltage of the substrate bias is equal to It is set to a value of 2v.

As described above, according to this embodiment, the conventional problems of latch-up, power consumption, and area required for a smoothing capacitor can be solved without using a substrate bias generation circuit.

Next, a second embodiment of the present invention will be described with reference to FIG. In the same figure, the second embodiment is shown in FIG.
The difference from the embodiment shown in FIG.
One point is that it is connected to the source of the MO8 circuit 2, and the other is that the low level side, that is, the source of the 8M08 circuit 1, and the ground terminal 6 are connected via the NMOS 5.

Since the rest remains the same, the same components are given the same reference numerals and their explanations will be omitted.

With this configuration, the voltage of the p-type semiconductor substrate or P-well of NMO3 is equal to the voltage VMM of the ground terminal 6, and
PMOS n-type semiconductor substrate or.

The voltage of the N-well has the same potential as the voltage vcc of the power supply terminal 3. That is, the amplitude voltage of the MO3 circuit is
It is expressed by the following equation (3).

Amplitude voltage=voltage generated by the step-down circuit vll-voltage at the ground terminal VXS (3) Also, between the n-type semiconductor substrate or the N-well.

The potential difference with the source of the PMOS is applied to the PMOS as a substrate bias, and the voltage is expressed by the following equation (4).

Substrate bias power supply voltage vCc - voltage generated by the step-down circuit v
lI...(4) Specifically, the voltage values in equations (3) and (4) above are determined when the power supply voltage vcc is 5V and the step-down circuit 4
The generated voltage v3 is 3V, and the applied voltage of substrate bias is +2
A value of v is set.

As described above, according to the second embodiment, a substrate bias can be applied to a PMOS formed on an n-type semiconductor substrate or an N-well even without the substrate bias generation circuit 7 of the conventional example.

Next, a third embodiment of the present invention will be described with reference to FIG. In the figure, the third embodiment differs from the first and second embodiments shown in FIGS. 1 and 2 by providing two step-down circuits 4a and 4b, and The voltages v and I are applied to the high level side of the above CMO8 circuit, that is, the source of the PMO8 circuit 2, and the voltage vL generated by the step-down circuit 4b is applied to the low level side of the above 0M03 circuit, that is, the source of the 8M08 circuit 1. The point is that it is supplied to

Since the rest remains the same, the same components are given the same reference numerals and their explanations will be omitted.

With this configuration, the voltage of the NMOS p-type semiconductor substrate or P-well is the same potential as the voltage V□ of the ground terminal 6, and the voltage of the PMOS n-type semiconductor substrate or N-well is the same as the voltage V□ of the ground terminal 6. They have the same potential as the voltage VCe.

Therefore, the amplitude voltage of the MO8 circuit is determined by the following formula (5)% Formula % Amplitude voltage = voltage generated by the step-down circuit 4a v, I - step-down circuit 4
The generated voltage vL...(5) The substrate bias is for NMOS formed on a p-type semiconductor substrate or P-well.
The voltage represented by the above equation (2) also applies to the 2MO8 formed on the n-type semiconductor substrate or N-well.
4) The voltages shown in the equations are applied.

As described above, according to the third embodiment, NMOS and P
, a substrate bias is applied to the MOS even without the substrate bias generation circuit 7.

Further, since both the voltage step-down circuit 4a and the voltage step-down circuit 4b are connected to the common power supply terminal 3 and the common ground terminal 6.

The fluctuation of both output voltages is caused by the power supply voltage vee or the ground voltage V. Therefore, the relative value, that is, the difference between the voltage generated by the step-down circuit 4a and the voltage vL generated by the step-down circuit 4b is the power supply voltage VCC and the ground voltage V. The operating voltage of the transistors inside the integrated circuit is relatively constant, and the operation is stable.

(Effects of the Invention) As explained above, according to the present invention, the 2MO8
, NMOS, and can eliminate all problems such as substrate floating that causes latch-up caused by the substrate bias generation circuit, injection of minority carriers into the substrate, and increased power consumption.

[Brief explanation of drawings]

1, 2 and 3 illustrate the first embodiment according to the present invention. A circuit diagram of a semiconductor integrated circuit showing second and third embodiments,
FIG. 4 is a circuit diagram of a conventional semiconductor integrated circuit. 1...NMOS circuit, 2...PMO8 circuit,
3... Power supply terminal, 4, 4a, 4b... Step-down circuit,
5, 10.11...N channel MOS transistor (
NMOS), 6... Ground terminal, 7... Substrate bias generation circuit, 8... P channel MOS transistor (2MO8), 9... Ring oscillator, 12
...Amplifier, 13...Capacitor, 14...Smoothing capacitor. Patent applicant: Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] (1) The voltage on the high level side of the logic of the NMOS or CMOS circuit integrated on the semiconductor substrate comes from the power supply terminal, and the voltage on the low level side comes from the step-down circuit formed on the semiconductor substrate.
A semiconductor integrated circuit characterized in that the voltages of the NMOS p-type semiconductor substrate or P-well constituting the above-mentioned NMOS or CMOS circuit are supplied from a ground terminal. (2) The logic low-level voltage of the PMOS or CMOS circuit integrated on the semiconductor substrate is supplied from the ground terminal, and the high-level voltage is supplied from the step-down circuit formed on the semiconductor substrate to the PMOS or CMOS circuit. PMOS that constitutes
1. A semiconductor integrated circuit characterized in that voltages of the n-type semiconductor substrate or the N-well are respectively supplied from power supply terminals. (3) The logic high level voltage of the CMOS circuit integrated on the semiconductor substrate is supplied from the first step-down circuit formed on the semiconductor substrate, and the voltage of the n-type semiconductor substrate or N-well is supplied to the power supply terminal. A semiconductor integrated circuit characterized in that the voltage on the low level side is supplied from the second step-down circuit formed on the semiconductor substrate, and the voltage of the p-type semiconductor substrate or P-well is supplied from the ground terminal. (4) The semiconductor integrated circuit according to claim (3), wherein the first and second step-down circuits formed on the semiconductor integrated circuit are connected to a common power supply terminal and a common ground terminal. circuit.