JPH02122562A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH02122562A JPH02122562A JP63274366A JP27436688A JPH02122562A JP H02122562 A JPH02122562 A JP H02122562A JP 63274366 A JP63274366 A JP 63274366A JP 27436688 A JP27436688 A JP 27436688A JP H02122562 A JPH02122562 A JP H02122562A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- nmos
- substrate
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 abstract 7
Abstract
PURPOSE: To eliminate the need for making a substrate bias generating circuit and miniaturize an integrated circuit by causing a voltage at the high logic voltage side in an NMOS or a CMOS circuit located on a semiconductor substrate to be supplied directly by a power source terminal and the voltage at its low logic voltage side to be supplied by a step-down circuit and further, the voltage on a P-type semiconductor substrate or at a P-type well in which the NOS of the NMOS or the CMOS circuit is formed to be supplied by a grounding terminal.
CONSTITUTION: A power source terminal 3 and a high voltage side of a CMOS circuit in which an NMOS circuit 1 and PMOS circuit 2 are made up are connected through a PMOS 8 and then the low voltage side of the CMOS circuit is connected to the output side of a step-down circuit 4. Further, the P-type semiconductor substrate of the NMOS circuit or a P-type well is connected directly to a connecting terminal 6. This configuration allows the voltage amplitude of a MOS circuit to be expressed by means of a following equation: Amplitude voltage = Voltage VCC of power source- generating voltage V1 of step-down circuit. And then voltage difference between the P-type substrate or the P-type well and the source side of the NMOS circuit is impressed to the NMOS circuit as a substrate bias and its bias is obtained by the following equation: Substrate bias = Grounding voltage VSS-generating voltage VL of step- down circuit.
COPYRIGHT: (C)1990,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63274366A JP2906148B2 (en) | 1988-11-01 | 1988-11-01 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63274366A JP2906148B2 (en) | 1988-11-01 | 1988-11-01 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02122562A true JPH02122562A (en) | 1990-05-10 |
JP2906148B2 JP2906148B2 (en) | 1999-06-14 |
Family
ID=17540658
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63274366A Expired - Fee Related JP2906148B2 (en) | 1988-11-01 | 1988-11-01 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2906148B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02196469A (en) * | 1989-01-25 | 1990-08-03 | Fujitsu Ltd | Semiconductor device |
JPH04206659A (en) * | 1990-11-30 | 1992-07-28 | Toshiba Corp | Semiconductor memory |
JPH04253366A (en) * | 1991-01-29 | 1992-09-09 | Toshiba Corp | Gate array device, input circuit, output circuit, and voltage step down circuit |
JPH05145071A (en) * | 1991-09-30 | 1993-06-11 | Fujitsu Ltd | Mis field-effect semiconductor device and manufacture thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5749260A (en) * | 1980-09-09 | 1982-03-23 | Toshiba Corp | Semiconductor integrated circuit |
JPS62208715A (en) * | 1986-03-10 | 1987-09-14 | Fujitsu Ltd | Semiconductor integrated circuit |
-
1988
- 1988-11-01 JP JP63274366A patent/JP2906148B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5749260A (en) * | 1980-09-09 | 1982-03-23 | Toshiba Corp | Semiconductor integrated circuit |
JPS62208715A (en) * | 1986-03-10 | 1987-09-14 | Fujitsu Ltd | Semiconductor integrated circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02196469A (en) * | 1989-01-25 | 1990-08-03 | Fujitsu Ltd | Semiconductor device |
JPH04206659A (en) * | 1990-11-30 | 1992-07-28 | Toshiba Corp | Semiconductor memory |
JPH04253366A (en) * | 1991-01-29 | 1992-09-09 | Toshiba Corp | Gate array device, input circuit, output circuit, and voltage step down circuit |
JPH05145071A (en) * | 1991-09-30 | 1993-06-11 | Fujitsu Ltd | Mis field-effect semiconductor device and manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
JP2906148B2 (en) | 1999-06-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |