JPH06334124A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a integrated circuit wherein an input impedance can be made high so as to be set to the same state as a noncontact state by a method wherein an input circuit is constituted of a field transistor whose gate withstand voltage is higher than that of a circuit to be tested. CONSTITUTION:A field transistor 13 is constituted in such a way that its gate withstand voltage is higher than that of a transistor constituting a circuit 12 to be tested, and a node n1 corresponding to a gate electrode is connected to an external pin on an LS 1. A drain for the transistor 13 is connected to a power-supply potential Vcc, and its source is connected to a passive resistance element 14 for pull-down. The input terminal of a test circuit 11 is connected to the connecting node n2 of the source for the transistor 13 to the passive resistance element 14. Consequently, since the test input circuit is formed and constituted of the field transistor 13 whose gate withstand voltage is higher than that of the circuit 12 to be tested, it is possible to obtain the title integrated circuit whose input impedance is very high, which is set to the same state as a noncontact state and whose gate bias interconnection can be made inessential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a built-in test circuit, and more specifically, for inputting a signal to the test circuit from the outside during an operation test of the internal circuit at the time of product shipment. Related to the test input circuit.

[0002]

2. Description of the Related Art Conventionally, an LSI generally has a built-in test circuit for performing an operation test of its internal circuit. When performing a test using this test circuit, the test circuit is operated by a control signal from an external terminal, a test signal is supplied from this test circuit to the circuit under test, and the response of the circuit under test to this is confirmed. Therefore, the signal system for operating the test circuit from outside the LSI is the LS.
Naturally I have it.

FIG. 3 is an explanatory view of a test input circuit which was adopted at the earliest stage.

As shown in this figure, a test-dedicated pin 302 is provided in the external pin of the LSI 301.
A control signal is supplied from 02 to the circuit under test. The test function and the normal function are classified according to the voltage condition of the control signal. Therefore, for example, at the time of shipment, the external pin is set to the voltage condition of the test function to operate the circuit under test. After that, by mounting the external pins on the board in a state where the external pins are biased to the normal function voltage condition, the test circuit can be held in the inactive state and the internal circuits can be operated in the normal function.

However, as the degree of integration of LSIs is increasing, the number of external pins required tends to increase as they become multifunctional. Under such circumstances, there are times when it is annoying that it is necessary to provide bias wiring even for pins dedicated to testing that are not used in the normal function mode, especially as the number of wiring pins increases, which makes the mounting work redundant. .

Therefore, a method has been devised in which an external pin for a normal function is also used for a test.

FIG. 4 shows the configuration of a conventional test input circuit according to this method.

In the figure, 401 is a normal function input circuit, 402 is a circuit under test, and a node n2 which is an input end of the normal function input circuit 401 is connected to an external pin.

A test input circuit 403 includes an operating voltage setting circuit 404 and a buffer circuit 405.
The operating voltage setting circuit 404 is an NMOS transistor 4041-, which is diode-connected in the forward direction with respect to the node n41.
2 and a pull-down NMOS transistor 4043, and the potential of the common connection node n42 of the transistors 4042 and 4043 is equal to that of the transistors 4041 and 443.
It is lower than the potential of the node n41 by VGS of 042. The node n42 is connected to the input terminal of the buffer circuit 405, and the buffer circuit 405 is controlled by the voltage condition of the node n42. As a result, the normal function input circuit 401 and the buffer circuit 405 can be selectively operated depending on the voltage condition of the node n41.

FIG. 5 shows a normal function input circuit 4
01 and the buffer circuit 405 illustrate different operating voltage conditions.

In this figure, Vmin is the minimum value in the normal operation guarantee range (that is, the range in which the normal function input circuit 401 is operated), Vmax is the maximum value in the normal operation guarantee range, and ΔV1 is 2 VTH (Vmax) or more. The following voltage range, ΔV2, is a test operation allowable range (that is, a range in which the buffer circuit 405 is operated). As shown in the figure, the operation guarantee range of the normal function input circuit 401 is 2VTH of the transistors 4041 and 4042.
It is accommodated in the range of less than a minute. The maximum value Vmax of the operation guarantee range of the normal function input circuit 401 and this 2
The relationship with VTH is Vmax << 2VTH, and the buffer circuit 405 is operated with a voltage of 2VGS or higher, which is in this relationship. Therefore, during the test, it is much larger than 2VTH,
In addition, by applying the voltage of the external pin connected to the node n41 within the range of ΔV2 which is sufficiently smaller than the device limit, the normal function input circuit 401 is not operated, and only the buffer circuit 405 is operated. By applying a voltage to the external pin in the range of up to Vmax, only the normal function input circuit 401 can be operated without operating the buffer circuit 405.

However, since it becomes smaller as the miniaturization progresses, it is becoming difficult to obtain a sufficiently large test operation allowable range between the test mode and the normal mode.
External noise has become a cause of concern for stable operation in normal functions.

To obtain stable operation with the current technology, FIG.
There was no choice but to adopt the method shown in, and the emergence of some good plan was eagerly awaited.

[0014]

As described above, the conventional test input circuit is inconvenient for a miniaturized LSI in terms of mounting or securing reliability of operation.

The present invention has been made in view of the above problems of the prior art. The purpose of the present invention is to provide a test input which does not necessarily require wiring at the time of mounting and can ensure stable operation in a normal mode. To provide a circuit.

[0016]

A semiconductor integrated circuit of the present invention has a gate circuit having a higher gate breakdown voltage than a test circuit for supplying a test signal to a circuit under test and a transistor forming the circuit under test. A field transistor connected to the external input terminal and activating the test circuit by its output signal, and a resistance element for setting the potential of the field transistor output terminal when the field transistor is conducting. Is characterized by.

As the gate oxide film of the field transistor, an interlayer isolation oxide film may be adopted in addition to the element isolation oxide film.

The gate electrode of the field transistor is connected to an external input terminal defined as a non-connect pin or a test pin.

[0019]

According to the present invention, since the test input circuit is formed by the field transistor whose gate breakdown voltage is higher than that of the circuit under test, the input impedance is very high and the state is equivalent to the non-connected state. be able to. Therefore, at the time of mounting, to prevent the malfunction,
There is no need to provide gate bias wiring. Further, since it is not necessary to set the delicate operating voltage, stable operation in the normal mode can be secured.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

1A and 1B show the configuration of a test input circuit according to an embodiment of the present invention.

First, FIG. 1A is a circuit diagram,
Is a test circuit, 12 is a circuit under test, and the test circuit 11 is a buffer for supplying a test signal to the circuit under test 12.

Reference numeral 13 is a field transistor. This field transistor 13 has a higher gate breakdown voltage than the transistors constituting the circuit under test 12. The node n1 corresponding to the gate electrode thereof is a non-connect pin or a test pin on the LSI. Connected to a defined external pin. The drain of the transistor 13 is connected to the power supply potential Vcc, and the source thereof is connected to the passive resistance element 14 for pulling down.
The input terminal of is connected to the connection node n2 between the source of the transistor 13 and the passive resistance element 14.

FIG. 1B shows the device structure.
1 is an N-type substrate, and a P-type well 1
02 is formed, and an area isolation oxide film 103 for isolating the element area is formed. The buffer of the test circuit 11 is an N formed in one element region on the P-type well 102.
It is formed as a CMOS inverter composed of a MOS transistor 111 and a PMOS transistor 112 formed in one element region on the N-type region of the substrate 101. That is, a gate electrode made of a conductive film 113 made of polycrystalline silicon and a gate oxide film 114 is formed in the corresponding element region of the P-type well 102, and an N + type is formed on each side of the channel formation region immediately below the gate electrode. Source region 115 and N
A + type drain region 116 is formed. Board 10
A gate electrode composed of a conductive film 117 and a gate oxide film 118 is formed on the N-type region adjacent to the first P-type well 102, and the P + -type drain region 119 is formed on each side of the channel forming region immediately below the gate electrode. And P + type source region 120
And are formed. The common point between the gate electrode of the transistor 111 and the gate electrode of the transistor 117 serves as the input terminal of the inverter, which corresponds to the node n2 in FIG. A connection point between the drain region 116 of the transistor 111 and the drain region 119 of the transistor 112 serves as an output terminal of the inverter and corresponds to the node n3 shown in FIG.

Next, the transistor 13 is the P-type well 10
It is formed within 2. That is, the interlayer isolation oxide film 104 is formed on the entire surface of the substrate 101, and the region isolation oxide film 103 and the interlayer isolation oxide film 1 on the P-type well 102 are formed.
And 04 form the gate oxide film 131 of the transistor 12. A conductive film 130 as a gate electrode film is deposited on the gate oxide film 131 and corresponds to the node n1. The region isolation oxide film 103 forming the gate oxide film 131 and the region isolation oxide film 103 adjacent to each side.
An N + drain region 132 and an N + source region 133 are formed in the region between and. The source region 133 is connected to the node n2, and the passive resistance element 14 is commonly connected to the node n2.

The gate oxide film 131 is the region isolation oxide film 10.
3 and the interlayer isolation oxide film 104 have a total thickness of about 10000 angstroms or more. This normal gate oxide film thickness is 200 angstroms, and the gate breakdown voltage is 1
With respect to the value of 5 V, the gate oxide film of the transistor forming the strike circuit 12 has a sufficiently high gate breakdown voltage, so that electrostatic breakdown is not caused by the surge of the input terminal n1.

The Vth (threshold value) at which a current flows through the source / drain when an input voltage is applied to the input node n1 is determined by the impurity concentration in the region directly below the gate electrode 131 in the well 102, and should be set to 12 V, for example. You can Current ID determined by gm of the field transistor 13 when the input voltage Vin> 12V to the node n1
Flows.

Therefore, when the potential V1 of the node n2 determined by the passive resistance element 14 is V1> Vth, the test circuit is activated to enter the test mode, and the circuit under test 12 is passed through the test circuit 11 by changing the potential V1.
A test signal can be input to. On the contrary, when the input voltage V1 <12V, the test circuit is inactivated.

As described above, since the test input circuit is formed by the field transistor 13 whose gate breakdown voltage is higher than that of the circuit under test 12, the input impedance is very high and the state is similar to the non-connected state. be able to. Therefore, at the time of mounting, it is not necessary to provide the gate bias wiring to prevent the malfunction. Also,
Since it is not necessary to delicately set the operating voltage, stable operation in the normal mode can be secured. further,
Since it is not necessary to provide an input protection circuit for the field transistor 13 at the input terminal n1, the circuit structure can be simplified accordingly.

FIG. 2A shows the structure of a test input circuit according to the second embodiment of the present invention. The test input circuit shown in FIG. 2 includes a PMOS field transistor 13 'having a conductivity type opposite to that of the transistor 13. , A pull-down passive resistance element 14 'is inserted in its drain. Reference numeral n2 'is a connection node between the drain of the transistor 13' and the resistance element 14 ', which corresponds to the output terminal of the test input circuit.

The test input circuit of this embodiment is similar to that of the first embodiment, except that the polarity of the voltage applied to the gate is opposite to that of the first embodiment shown in FIG. An equivalent effect can be obtained.

FIG. 2B shows the configuration of the test input circuit according to the third embodiment of the present invention. The test input circuit shown in FIG. 2 is provided with an NMOS field transistor 13 ″ having the same conductivity type as the transistor 13. Here, the point that the pull-up passive resistance element 14 ″ is inserted in the drain thereof, in other words, the transistor 13 ″ is inserted in the ground line side is different from the first embodiment. Is a connection node between the drain of the transistor 13 ″ and the resistance element 14 ″, which corresponds to the output terminal of the test input circuit.

In the case of the test input circuit of this embodiment, except that the bias condition for the transistor 13 "is changed,
Similar to that of the first embodiment, the same effects can be obtained. Incidentally, in the circuit of the first embodiment, the transistor 13
The voltage higher than the ground potential VSS is set as the potential of the node n2 by the voltage drop caused by the current ID flowing through the resistor element 14, but in the circuit of the third embodiment, the current ID '' flowing through the transistor 13 "is set. Flowing into the resistance element 14 ", a voltage lower than the power supply potential Vcc by the voltage drop is set as the potential of the node n2. Therefore, the input voltage of the node n1 is set accordingly.

According to this embodiment, the same operational effect as the above embodiment can be obtained.

In the above embodiment, the passive resistance element is adopted as the pull-down or pull-up resistance, but the invention is not limited to this, and an active resistance element such as a diode or a transistor can be adopted.

[0036]

As described above, according to the present invention, since the test input circuit is formed by the field transistor whose gate breakdown voltage is higher than that of the circuit under test, the input impedance is very high and the non-connect The state can be the same as the state. Therefore, at the time of mounting, it is not necessary to provide the gate bias wiring to prevent the malfunction. Further, since it is not necessary to set the delicate operating voltage, stable operation in the normal mode can be secured. Further, since the input protection circuit is unnecessary, the circuit configuration is simplified accordingly.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a test input circuit according to a first embodiment of the invention as a circuit diagram (A) and an element sectional view (B).

FIG. 2 is a circuit diagram showing a configuration of a test input circuit according to a second embodiment (A) and a third embodiment (B) of the present invention.

FIG. 3 is a plan view showing the pin arrangement of an IC for explaining the configuration of a conventional test input circuit provided with test-dedicated pins.

FIG. 4 is a circuit diagram showing a configuration of a conventional test input circuit that also uses a normal function pin as a test pin.

5 is an explanatory diagram showing operating voltage ranges of the circuit shown in FIG. 4 during normal function operation and test function operation.

[Explanation of symbols]

11 test circuit 12 circuit under test 13, 13 ', 13 "field transistor 14, 14', 14" pull-down or pull-up passive resistance element for setting test circuit activation potential n1 input connected to non-connect pin or test pin Terminal node n2 Test circuit activation potential setting terminal node n3 Test circuit output terminal node 101 N-type substrate 102 P-type well 103 Element region isolation oxide film 104 Interlayer isolation oxide film 131 Gate oxide film 132 Drain region 133 Source region

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display area H01L 21/82

Claims (3)

[Claims] 1. A test circuit for supplying a test signal to a circuit under test, which has a gate breakdown voltage higher than that of a transistor forming the circuit under test, the gate electrode being connected to an external input terminal, and an output signal from the circuit A semiconductor integrated circuit comprising: a field transistor for activating a test circuit; and a resistance element for setting the potential of the field transistor output terminal when the field transistor is conducting. 2. The gate oxide film of the field transistor includes an interlayer isolation oxide film.
The semiconductor integrated circuit described. 3. The gate electrode of the field transistor is connected to an external input terminal defined as a non-connect pin or a test pin.
The semiconductor integrated circuit according to claim 1.