JP3272809B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a CMOS type semiconductor integrated circuit device, and more particularly to an interface with an external circuit device.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional connection between a semiconductor integrated circuit device 100 and an external circuit device 200. In this case, between the semiconductor integrated circuit device 100 and the external circuit device 200, a plurality of unidirectional or bidirectional buses 300 are provided.

[0006] As shown in FIG. 6, for example, data is exchanged between the semiconductor integrated circuit device 100 and the external circuit device 200 by being connected to each other via input / output terminals 101 and 201. Also, the external circuit device 200 is controlled from the semiconductor integrated circuit device 100.

For example, the E of the semiconductor integrated circuit device 100
When a high-level signal is input to the terminal, a signal from the D terminal is output from the output circuit 103 under the control of the control circuit 102.
Is output from the input / output terminal 101 via the.

This signal is transmitted to the input / output terminal 201 of the external circuit device 200 via the bus 300,
3 and is taken into the external circuit device 200. At this time, a low-level signal is supplied to the e terminal of the external circuit device 200, and the signal from the d terminal is not output from the output circuit 202 to the input / output terminal 201.

On the other hand, Hi is connected to the e terminal of the external circuit device 200.
When a gh level signal is input, a signal from the d terminal is output from the input / output terminal 201 via the output circuit 202. This signal is transmitted to the input / output terminal 101 of the semiconductor integrated circuit device 100 via the bus 300,
Through the semiconductor integrated circuit device 100.

At this time, E of the semiconductor integrated circuit device 100
A low-level signal is supplied to the terminal, and a signal from the D terminal is not output to the input / output terminal 101.

However, in such a configuration, for example, when the power supply voltage of the semiconductor integrated circuit device 100 is turned off and the semiconductor integrated circuit device 100 is brought into a non-operation state, the external circuit device 200 becomes
When a level signal is output, the semiconductor integrated circuit device 10
A current flows between the input / output terminal 101 and the power supply VDD1, and the potential of the power supply VDD1 rises due to a parasitic PN junction diode between the drain of the Pch transistor TP1 and the substrate which constitutes the output circuit 103 connected to the input / output terminal 101 of 0. Is done.

This is the same as turning on the power supply voltage to the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 malfunctions and outputs a signal to the external circuit device 200. As a result, the external Circuit device 200
There is a drawback that it causes a malfunction.

Normally, as shown in FIG. 7, for example, the output circuit of the semiconductor integrated circuit device 100 is an open drain circuit 103 'including only an Nch transistor TN1, and when not operating, a high level is applied to the E terminal of the semiconductor integrated circuit device 100. , The input / output terminal 101 is set to a high impedance state.

That is, by removing the Pch transistor TP1 from the output circuit 103, current is prevented from flowing between the input / output terminal 101 and the power supply VDD1, that is, the path of the current flowing from the outside to the power supply VDD1 is eliminated. I have.

However, in such a configuration, by inputting a low-level signal to the E terminal of the semiconductor integrated circuit device 100, a low-level signal can be output from the input / output terminal 101, but a high-level signal can be output. Signal cannot be output.

When a large voltage due to static electricity or the like is applied to the input / output terminal 101, the input / output terminal 101 is connected to the power supply VDD.
Since there is no PN junction diode between them, there is a drawback that electrostatic breakdown easily occurs.

[0014]

As described above, conventionally, when an Nch open drain circuit is used in order to prevent a malfunction of an external circuit device when it is not operating, the H
There has been a problem that a high-level signal cannot be output and that electrostatic breakdown is likely to occur.

Therefore, the present invention can reliably prevent a malfunction of the external circuit device when it is not operating, and at the same time, can provide a high-level operation.
It is an object of the present invention to provide a semiconductor integrated circuit device capable of outputting a / Low level signal.

[0016]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention comprises: an input / output terminal for exchanging signals with an external circuit device;
Nch transformer connected between this input / output terminal and ground
Connected in series with the transistor and this Nch transistor
Between the second power supply voltage and the input / output terminal.
An output circuit composed of a Pch transistor connected therebetween, and a first circuit for controlling the output circuit and outputting from the input / output terminal a signal having the same level as a signal input to a signal terminal.
Control circuit and does not vary even when the first power supply voltage drops
Having the second power supply voltage and dropping the first power supply voltage;
At times, the second power supply voltage is supplied to the output circuit.
An input / output terminal in a high-impedance state to cut off an electrical connection with the external circuit device.

[0017]

According to the present invention, since the path of the current flowing from the outside to the power supply in accordance with the change of the power supply voltage can be electrically disconnected by the above-described means, the output of the High / Low level signal is not impaired. It is possible to prevent the potential of the power supply from increasing during operation.

[0018]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows an input / output circuit section of the semiconductor integrated circuit device according to the first embodiment.

That is, the input / output of the semiconductor integrated circuit device 10
The output circuit section includes an input / output terminal 11, an input circuit 12, an output circuit 13, a control circuit 14, and a cutoff circuit 15, as shown in the drawing.

The output circuit 13 includes a Pch transistor TP1 connected between the power supply VDDB and the input / output terminal 11.
And Nc connected between the input / output terminal 11 and the ground.
h transistor TN1.

The control circuit 14 receives the output of the cutoff circuit 15 and the signals from the D and E terminals as inputs, and generates a base voltage of the Pch transistor TP1 of the output circuit 13 from the NAND circuit 14a. An inverting circuit 14b for inverting the signal of the above, and an inverted output of the inverting circuit 14b, an inverted output of the shutoff circuit 15, and a signal from the D terminal to generate a base voltage of the Nch transistor TN1 of the output circuit 13. And a NOR circuit 14c.

The shutoff circuit 15 detects a voltage drop of the power supply VDD1 and determines whether or not the semiconductor integrated circuit device 10 is in a non-operating state. And an inverting circuit 15b of the control circuit 14 for generating an inverted output to the NOR circuit 14c and an inverting circuit 15c for further inverting the inverted output to generate an output to the NAND circuit 14a.
And a power supply VDDB for constantly supplying a power supply voltage to the output circuit 13.

When the semiconductor integrated circuit device 10 is in the operating state, the power supply voltage detecting circuit 15a of the cutoff circuit 15 is operated.
A higher-level signal is output. This allows
Outputs a and b of the inverting circuits 15b and 15c are Lo, respectively.
It becomes w level and High level.

As a result, the NAND circuit 1 of the control circuit 14
4a and the output β of the NOR circuit 14c are determined by the inputs from the D terminal and the E terminal, and a signal of the same level as the signal input to the D terminal is output from the input / output terminal 11. You.

On the other hand, when the semiconductor integrated circuit device 10 is in a non-operating state (when the power supply voltage drops), a low level signal is output from the power supply voltage detection circuit 15a. As a result, the outputs a and b of the inverting circuits 15b and 15c become High level and Low level, respectively.

As a result, the output α of NAND 14a and NO
The output β of the R circuit 14c is fixed at a high level and a low level, and the input / output terminal 11 is set to a high impedance state.

As described above, when the voltage drop of the power supply VDD1 is detected and the non-operating state is determined based on the voltage drop, the output circuit 13 is supplied with a power supply VDD different from the power supply VDD1.
The power supply VDDB which is not affected by the voltage drop of DD1 is supplied.

Therefore, even when the semiconductor integrated circuit device 10 is not operating, it is possible to prevent a current from flowing from the input / output terminal 11 to the power supply. Malfunction can be prevented.

In operation, a signal having the same level as the signal input to the D terminal can be output, that is, a signal having both high and low levels can be output.

Next, a second embodiment of the present invention will be described. FIG. 2 shows an example in which the above-mentioned shutoff circuit is configured as a non-operating control circuit.

That is, the control circuit for controlling the output circuit 13 is separated into a control circuit 20 for operation and a control circuit 21 for non-operation, and the output circuit is controlled by different control circuits according to the voltage drop of the power supply VDD1. Thirteen controls are performed.

In this case, the control circuit 20 receives the signals from the D and E terminals as inputs and generates a NAND circuit 20 for generating a base voltage of the Pch transistor TP1 of the output circuit 13.
a, an inverting circuit 20b for inverting a signal from the E terminal,
And a NOR circuit 20c which receives an inverted output of the inverting circuit 20b and a signal from the D terminal and generates a base voltage of the Nch transistor TN1 of the output circuit 13.
Consists of

The control circuit 21 detects a voltage drop of the power supply VDD1 and determines whether or not the semiconductor integrated circuit device 10 is in a non-operating state, and an inversion for inverting the detection output. A circuit 21b, an inverting circuit 21c for further inverting the inverted output, and the input / output terminal 11
And a Pch transistor tp1 connected between the Pch transistor TP1 of the output circuit 13 and on / off controlled by the inverted output of the inverting circuit 21b; an input / output terminal 11 and an Nch transistor TN1 of the output circuit 13; And an Nch transistor tn1 that is on / off controlled by the output of the inverting circuit 21c.
And a power supply VDDB for constantly supplying a power supply voltage to the output circuit 13.

In this circuit, when the semiconductor integrated circuit device 10 is in the operating state, a high-level signal is output from the power supply voltage detection circuit 21a of the control circuit 21. As a result, the outputs a and b of the inverting circuits 21b and 21c become Low level and High level, respectively.

As a result, the transistors TP1 and TN1 of the output circuit 13 are turned on, and when the signal input to the E terminal is at the high level, the same signal as the signal input to the D terminal from the input / output terminal 11 is output. A level signal is output.

On the other hand, when the device 10 is in a non-operating state (when the power supply voltage drops), the power supply voltage detection circuit 21a outputs Lo.
A w-level signal is output. Thereby, the inverting circuit 2
The outputs a and b of 1b and 21c are respectively at High level and Low level.

As a result, both transistors TP1, TN1
Is in an off state, and the input / output terminal 11 is in a high impedance state. According to such a configuration, the first
Similarly to the embodiment, the semiconductor integrated circuit device 10 can be prevented from malfunctioning and the external circuit device from malfunctioning, and can output signals of both High / Low level, and the circuit configuration is very easy. It can be.

As described above, the path of the current flowing from the outside to the power supply according to the change in the power supply voltage can be electrically disconnected. That is, a voltage drop of the power supply is detected, and another power supply is supplied to the output circuit during non-operation. Thus, the input / output terminals can be maintained in a high impedance state, so that it is possible to prevent a current from flowing from the outside and increase the potential of the power supply. Therefore, it is possible to reliably prevent the semiconductor integrated circuit device from malfunctioning during non-operation and causing the external circuit device to malfunction.

In addition, during operation, a signal having the same level as the signal input from the input / output terminal to the D terminal can be output, and the output of the high / low level signal is not impaired.

Further, since a PN junction diode exists between the input / output terminal and the power supply, even if a large voltage is accidentally applied, the diode can be protected from electrostatic breakdown. In the above-described embodiment, the case has been described where the path through which the current flows electrically is cut off when the fluctuation (drop) of the power supply voltage is detected. However, the present invention is not limited to this. It is also possible to configure so that there is no current path.

FIG. 3 shows a conventional output circuit which is composed of two Nch
This is an example in which a transistor is used. That is, N connected between the input / output terminal 11 and the ground
The output circuit 31 is composed of the channel transistor TN1 and the Nch transistor TN2 connected between the input / output terminal 11 and the power supply VDD1.

A control circuit 32 for controlling the output circuit 31 receives the signal input from the terminal E and the signal input from the terminal D, and turns on / off the Nch transistor TN2 of the output circuit 31. AND to control
A circuit 32a, an inverting circuit 32b for inverting a signal input from an E terminal, and an inverted output thereof and a signal input from the D terminal are respectively input, and ON / OFF control of the Nch transistor TN1 of the output circuit 31 is performed. NOR
It is composed of a circuit 32c.

In this case, when the signal input to the E terminal is at the high level when the semiconductor integrated circuit device 10 is operating, the output from the input / output terminal 11 is at the level of the signal input to the D terminal. Is determined by

For example, if the signal from the D terminal is at a low level, the AND circuit 32a of the control circuit 32 and the NOR circuit 32a
The outputs of the circuit 32c are Low level and High level, respectively.
Since the signal becomes the h level, a signal of the Low level is output from the input / output terminal 11.

If the signal from the D terminal is at a high level, the outputs of the AND circuit 32a and the NOR circuit 32c are at a high level and a low level, respectively.
As a result, the transistor TN1 is turned off and the transistor TN2 is turned on.
A high-level signal is output.

On the other hand, when the device 10 is in a non-operating state, since the path of the current flowing into the power supply VDD1 does not exist, even if a high-level signal enters the input / output terminal 11 from the outside, the potential of the power supply VDD1 is reduced. Will not be raised.

As described above, the existence of the path changes according to the voltage drop of the power supply VDD1, that is, when the power supply VDD1 is not operating.
1 is eliminated, the semiconductor integrated circuit device 10 malfunctions due to the flow of current from outside during non-operation, and the external circuit device is not operated, as in the first and second embodiments. Can be prevented from erroneously operating, and both high and low level signals can be output during operation.

However, in the case of the above-described configuration, when a high-level signal is output from the input / output terminal 11, a signal having the same voltage as the power supply VDD1 cannot be output because of the NMOS circuit.

When a signal having the same voltage as the power supply VDD1 is output from the input / output terminal 11 in the circuit having such a configuration, the transistor TN2 connected to the power supply VDD1 of the output circuit 31 is controlled by, for example, a booster circuit. A boosted power supply may be used.

FIG. 4 shows an example of a circuit configuration when a signal having the same voltage as the power supply VDD1 is output from the input / output terminal 11. That is, the AND circuit 32a of the control circuit 32 for controlling the input to the gate of the transistor TN2
The booster circuit 33 is connected to the power supply of the transistor TN2 so that the input to the gate of the transistor TN2 becomes a voltage higher than the power supply VDD1. Of course, various modifications can be made without departing from the scope of the present invention.

[0051]

As described above in detail, according to the present invention, a semiconductor integrated circuit capable of reliably preventing a malfunction of an external circuit device during non-operation and capable of outputting a High / Low level signal. Equipment can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a main part of a semiconductor integrated circuit device according to a second embodiment.

FIG. 3 is a configuration diagram showing a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration example of a circuit in the case where a signal having the same voltage as a power supply is output.

FIG. 5 is a diagram showing a connection example of a semiconductor integrated circuit device and an external circuit device for explaining a conventional technique and its problems.

FIG. 6 is a configuration diagram showing a main part of the connection between the semiconductor integrated circuit device and an external circuit device.

FIG. 7 is a configuration diagram showing an Nch open drain circuit as an example of a main part of the semiconductor integrated circuit device.

[Explanation of symbols]

10: semiconductor integrated circuit device, 11: input / output terminal, 12:
Input circuit, 13 ... Output circuit, 14 ... Control circuit, 14a ...
NAND circuit, 14b inverting circuit, 14c NOR circuit, 15 interrupting circuit, 15a power supply voltage detecting circuit, 15
b, 15c: inverting circuit, VDD1: power supply, VDDB: separate power supply, TP1: Pch transistor, TN1: Nch transistor.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masanao Akutagawa 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics In-house (72) Inventor Koichi Notoya 25-1, Ekimae-Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba In-house Microelectronics Co., Ltd. (56) References JP-A-64-48556 (JP, A) JP-A-63-276325 (JP, A) JP-A-63-240124 (JP, A) JP-A-4-329024 ( JP, A) JP-A-62-18115 (JP, A) JP-A-6-232728 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 17/00-17/70 H03K 19/003

Claims (2)

(57) [Claims] An input / output terminal for exchanging signals with an external circuit device, and an Nch transformer connected between the input / output terminal and ground.
Connected in series with the transistor and this Nch transistor
Between the second power supply voltage and the input / output terminal.
An output circuit composed of a Pch transistor connected therebetween, a first control circuit for controlling the output circuit and outputting from the input / output terminal a signal having the same level as a signal input to a signal terminal ; The second power supply which does not change even when the power supply voltage drops
And when the first power supply voltage drops, the output is
An input / output terminal that is in a high impedance state by supplying the second power supply voltage to a power circuit to cut off an electrical connection with the external circuit device. Semiconductor integrated circuit device. 2. The control circuit according to claim 1, wherein the shut-off circuit is configured as a second control circuit for the first power supply voltage drop. 2. The semiconductor integrated circuit device according to claim 1 , wherein said output circuit is controlled.