CN105823977A - Latch detection circuit and integrated circuit - Google Patents
Latch detection circuit and integrated circuit Download PDFInfo
- Publication number
- CN105823977A CN105823977A CN201510449782.1A CN201510449782A CN105823977A CN 105823977 A CN105823977 A CN 105823977A CN 201510449782 A CN201510449782 A CN 201510449782A CN 105823977 A CN105823977 A CN 105823977A
- Authority
- CN
- China
- Prior art keywords
- pnpn structure
- test lead
- breech lock
- logical device
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The present invention discloses a latch detection circuit and an integrated circuit. The latch detection circuit comprises a current limiting resistor, a logic device, and a testing end. One end of the current limiting resistor is connected to one end of a PNPN structure to be detected. The other end of the current limiting resistor is connected to the positive electrode of a logic power supply. The other end of the PNPN structure is connected to the grounding end of the logic power supply. The first end of the logic device is connected to the positive electrode of the logic power supply. The second end of the logic device is connected to the grounding end of the logic power supply. The third end of the logic device is connected to one end of the PNPN structure. The testing end is connected to the fourth end of the logic device. When the PNPN structure normally works, the testing end outputs a low level. When the PNPN structure is latched, the logic device is switched on, and the testing end outputs a high level. According to the invention, the latch phenomenon of the PNPN structure can be accurately detected in real time, the circuit has the advantages of simple structure, low cost, high reliability, low system resource occupation, the design and layout difficulty of the integrated circuit can be reduced, and the flexibility of the integrated circuit layout is improved.
Description
Technical field
The present invention relates to IC design field, particularly relate to a kind of breech lock testing circuit and integrated circuit.
Background technology
Latch phenomenon refers to that the intrinsic parasitic bipolar transistor of cmos device is triggered conducting, exists a low impedance path, big electric current between power supply and ground, causes circuit normally to work, even burn circuit.
In IC design, comprise the PNPN structure of bipolar transistor it may happen that latch phenomenon.Under abnormal state, this bipolar transistor may be triggered, such as: the input of integrated circuit or output pin, on power supply or lower margin just or negative voltage spike, moment high load capacity electric current, can produce undesirable current path in PNPN structure, substantial amounts of electric current by and cause breech lock.
In order to prevent latch phenomenon, frequently with in the following manner in prior art, such as: minimizing substrate resistance is to produce relatively low voltage drop, or increases breech lock testing agency, releases bolt-lock by feedback mechanism.But increase the circuit of prevention breech lock on the integrated, and elasticity when can reduce IC design layout and motility, additionally need bigger chip area to accommodate the circuit increased.
Summary of the invention
In order to solve above-mentioned technical problem, the invention provides a kind of breech lock testing circuit and integrated circuit, solve the testing circuit complexity detecting PNPN structure breech lock in prior art in integrated circuits, affect the layout problem of integrated circuit.
According to one aspect of the present invention, it is provided that a kind of breech lock testing circuit, including: current-limiting resistance, logical device and test lead；Wherein,
One end of current-limiting resistance is connected with one end of PNPN structure to be detected, and the other end of current-limiting resistance and the positive pole of a logic power connect；Wherein, the other end of PNPN structure is connected with the earth terminal of logic power；
First end of logical device is connected with the positive pole of logic power, and the second end of logical device is connected with the earth terminal of logic power, and the 3rd end of logical device is connected with one end of PNPN structure；
Test lead is connected with the 4th end of logical device；
Wherein, when PNPN structure normally works, test lead exports a low level；
When PNPN structure generation breech lock, logical device turns on, and test lead exports a high level.
According to another aspect of the present invention, additionally provide a kind of integrated circuit, including breech lock testing circuit as above；Integrated circuit also includes: at least one PNPN structure, and controls the processor of PNPN structure；One end of current-limiting resistance is connected with the voltage output end of processor, and the other end of current-limiting resistance is connected with one end of PNPN structure；Test lead is connected with the control end of processor；The other end of PNPN structure is connected with the earth terminal of processor；
Wherein, when PNPN structure normally works, test lead inputs a low level to the control end of processor, and processor is not responding to；
When PNPN structure generation breech lock, test lead inputs a high level to the control end of processor, and processor controls voltage output end power-up initializing.
Embodiments of the invention provide the benefit that:
When PNPN structure normally works, the electric current that PNPN structure flows through is the least, thus the pressure reduction on current-limiting resistance is the least, and logical device is in cut-off state, and test lead exports a low level；When PNPN structure generation breech lock, the electric current that PNPN structure flows through is very big, thus the pressure reduction on current-limiting resistance is very big, and logical device is in the conduction state, and test lead exports a high level；Using this breech lock testing circuit can detect the latch phenomenon of PNPN structure in real time, and this circuit structure is simple, low cost, reliability is high, and occupying system resources is few, it is possible to decrease IC design layout difficulty, improves the motility of integrated circuit layout.
Accompanying drawing explanation
Fig. 1 represents the circuit theory diagrams of the breech lock testing circuit of the present invention；
Fig. 2 represents the circuit theory diagrams of the integrated circuit of the present invention.
Wherein in figure: R1, current-limiting resistance, D1, logical device, Vo, test lead, D2, PNPN structure, VDD, the positive pole of logic power, VSS, the earth terminal of logic power, D101, the first end, D102, the second end, D103, the 3rd end, D104, the 4th end, R2, load elements, Test, test lead.
Detailed description of the invention
It is more fully described the exemplary embodiment of the present invention below with reference to accompanying drawings.Although accompanying drawing showing the exemplary embodiment of the present invention, it being understood, however, that may be realized in various forms the present invention and should not limited by embodiments set forth here.On the contrary, it is provided that these embodiments are able to be best understood from the present invention, and complete for the scope of the present invention can be conveyed to those skilled in the art.
The embodiment provides a kind of breech lock testing circuit, when mainly utilizing breech lock, electric current and the difference of electric current when normally working, produce different voltage output and detect whether to there occurs breech lock.As it is shown in figure 1, this breech lock testing circuit specifically includes: current-limiting resistance R1, logical device D1With test lead Vo.Wherein,
Current-limiting resistance R1One end and PNPN structure D to be detected2One end connect, current-limiting resistance R1The other end and the positive pole V of a logic powerDDConnect；Wherein, PNPN structure D2The earth terminal V of the other end and logic powerSSConnect.The effect of this logic power is for this PNPN structure D2Power supply, in order to ensure when PNPN structure D2When there is latch phenomenon, whole circuit will not be burned and be provided with this current-limiting resistance R1。
Logical device D1The first end D101Positive pole V with logic powerDDConnect, logical device D1The second end D102Earth terminal V with logic powerSSConnect, logical device D1The 3rd end D103With PNPN structure D2One end connect.This logical device D1It is the core devices of whole breech lock testing circuit, the 3rd end D103For logical device D1Control end, the voltage controllable logic device D of this point1Gating, according to logical device D1Output detect the generation of breech lock.
Test lead VoWith logical device D1The 4th end D104Connect；Here, the 4th end D104For logical device D1Outfan.
Below, to this breech lock testing circuit, how the effect combining each device is detected latch phenomenon to be described in detail.When working properly, PNPN structure D2PNP and NPN all in closed mode, flow through PNPN structure D2Electric current the least, current-limiting resistance R1With PNPN structure D2Series connection, flows through current-limiting resistance R1Electric current also can be the least, therefore current-limiting resistance R1Dividing potential drop the least, logical device D1The first end D101With the 3rd end D103Pressure reduction the least, so this logical device D1Do not turn on, logical device D1The 4th end D104Export a low level, and then test lead VoExport a low level.
When PNPN structure D2In resistance occur because of interference when voltage is beated, PNPN structure D2PNP and NPN will form positive feedback, PNP pipe and NPN pipe and can simultaneously turn on, and quickly pin respective state and latch phenomenon occur, such PNPN structure D2It is externally a low resistance state, at this moment, flows through PNPN structure D2With current-limiting resistance R1Electric current very big, therefore current-limiting resistance R1Dividing potential drop very big, logical device D1The first end D101With the 3rd end D103Pressure reduction very big, cause this logical device D1Conducting, logical device D1The 4th end D104Export a high level, and then test lead VoExport a high level.
Using this breech lock testing circuit can detect the latch phenomenon of PNPN structure in real time, and this circuit structure is simple, low cost, reliability is high, and occupying system resources is few, it is possible to decrease IC design layout difficulty, improves the motility of integrated circuit layout.
In order to prevent from burning circuit because electric current is excessive, this breech lock testing circuit also includes a load elements R2, this load elements R2It is connected to test lead VoEarth terminal V with logic powerSSBetween.When PNPN structure D2Breech lock is occurred to cause logical device D1During conducting, due to logical device D1Resistance the lowest, therefore produce larger current, therefore a load elements R is set2As protection, prevent this circuit because electric current excessive and burn.
Alternatively, the above-mentioned logical device D mentioned1For the switching device controlled by voltage or electric current, such as: PNP type triode, logical device D1The first end D101For the exit of the emitter stage of this PNP type triode, logical device D1The second end D102With the 4th end D104It is the exit of the colelctor electrode of this PNP type triode, logical device D1The 3rd end D103Base stage for this PNP type triode.Therefore,
The base stage of PNP type triode and PNPN structure D2Connect；
The emitter stage of PNP type triode and the positive pole V of logic powerDDConnect；
The colelctor electrode of PNP type triode and test lead VoConnect.
Wherein, PNPN structure D2When normally working, PNP type triode is not turned on, test lead VoExport a low level；PNPN structure D2When there is breech lock, PNP type triode turns on, test lead VoExport a high level.
Alternatively, the load elements R played a protective role2Specifically may be designed as a protective resistance.
Above-mentioned mainly describe breech lock testing circuit implement circuit structure, the simple in construction of this breech lock testing circuit, can be integrated at IC interior, also can increase to the peripheral circuit of pcb board when Application of integrated circuit.The integrated circuit of this breech lock testing circuit it is integrated with below in conjunction with Fig. 2 introduction.
This integrated circuit includes: breech lock testing circuit as above, at least one PNPN structure D2, and control PNPN structure D2Processor.Wherein, the current-limiting resistance R of breech lock testing circuit1The voltage output end V of one end and processorDDConnect, current-limiting resistance R1The other end and PNPN structure D2One end connect；Test lead VoIt is connected with the control end Test of processor；PNPN structure D2The earth terminal V of the other end and processorSSConnect；
Wherein, when PNPN structure D2When normally working, PNPN structure D2PNP and NPN all in closed mode, flow through PNPN structure D2Electric current the least, current-limiting resistance R1With PNPN structure D2Series connection, flows through current-limiting resistance R1Electric current also can be the least, therefore current-limiting resistance R1Dividing potential drop the least, logical device D1The first end D101With the 3rd end D103Pressure reduction the least, so this logical device D1Do not turn on, logical device D1The 4th end D104Export a low level, and then test lead VoExport a low level, test lead VoA low level is inputted to the control end Test of processor.Wherein, the low level interrupt signal that the control end Test of processor receives, not as the trigger condition of processor, so being not responding to.
When PNPN structure D2In resistance occur because of interference when voltage is beated, PNPN structure D2PNP and NPN will form positive feedback, PNP pipe and NPN pipe and can simultaneously turn on, and quickly pin respective state and latch phenomenon occur, such PNPN structure D2It is externally a low resistance state, at this moment, flows through PNPN structure D2With current-limiting resistance R1Electric current very big, therefore current-limiting resistance R1Dividing potential drop very big, logical device D1The first end D101With the 3rd end D103Pressure reduction very big, cause this logical device D1Conducting, logical device D1The 4th end D104Export a high level, and then test lead VoExport a high level, test lead VoA high level is inputted to the control end Test of processor, the high level interrupt signal that the control end Test of processor receives, as the trigger condition of processor, voltage output end V can be controlledDDPower-up initializing.Wherein, how the interrupt signal (high or low level) controlling end Test controls voltage output end VDDImplement and can be realized by various encoding procedures ripe in prior art, such as: single-chip microcomputer or PLC etc..
Above is the preferred embodiment of the present invention, it should be pointed out that for the ordinary person of the art, can also make some improvements and modifications under without departing from the principle premise of the present invention, these improvements and modifications are the most within the scope of the present invention.
Claims (6)
1. a breech lock testing circuit, it is characterised in that including: current-limiting resistance, logical device and test lead；Wherein,
One end of described current-limiting resistance is connected with one end of PNPN structure to be detected, and the other end of described current-limiting resistance and the positive pole of a logic power connect；Wherein, the other end of described PNPN structure is connected with the earth terminal of described logic power；
First end of described logical device is connected with the positive pole of described logic power, and the second end of described logical device is connected with the earth terminal of described logic power, and the 3rd end of described logical device is connected with one end of described PNPN structure；
Described test lead is connected with the 4th end of described logical device；
Wherein, when described PNPN structure normally works, described test lead exports a low level；
When described PNPN structure generation breech lock, described logical device turns on, and described test lead exports a high level.
Breech lock testing circuit the most according to claim 1, it is characterised in that also include that a load elements, described load elements are connected between the earth terminal of described test lead and described logic power.
Breech lock testing circuit the most according to claim 1, it is characterised in that described logical device is PNP type triode,
The base stage of described PNP type triode is connected with described PNPN structure；
The emitter stage of described PNP type triode is connected with the positive pole of described logic power；
The colelctor electrode of described PNP type triode is connected with described test lead.
Breech lock testing circuit the most according to claim 3, it is characterised in that when described PNPN structure normally works, described PNP type triode is not turned on, and described test lead exports a low level；
During described PNPN structure generation breech lock, described PNP type triode turns on, and described test lead exports a high level.
Breech lock testing circuit the most according to claim 2, it is characterised in that described load elements is a resistance.
6. an integrated circuit, it is characterised in that include the breech lock testing circuit as described in any one of claims 1～5；Described integrated circuit also includes: at least one PNPN structure, and controls the processor of described PNPN structure；One end of described current-limiting resistance is connected with the voltage output end of described processor, and the other end of described current-limiting resistance is connected with one end of described PNPN structure；Described test lead is connected with the control end of described processor；The other end of described PNPN structure is connected with the earth terminal of described processor；
Wherein, when described PNPN structure normally works, described test lead inputs a low level to the control end of described processor, and described processor is not responding to；
When described PNPN structure generation breech lock, described test lead inputs a high level to the control end of described processor, and described processor controls described voltage output end power-up initializing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510449782.1A CN105823977A (en) | 2015-07-28 | 2015-07-28 | Latch detection circuit and integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510449782.1A CN105823977A (en) | 2015-07-28 | 2015-07-28 | Latch detection circuit and integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105823977A true CN105823977A (en) | 2016-08-03 |
Family
ID=56514505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510449782.1A Pending CN105823977A (en) | 2015-07-28 | 2015-07-28 | Latch detection circuit and integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105823977A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108169661A (en) * | 2017-12-28 | 2018-06-15 | 天津芯海创科技有限公司 | Method of designing integrated circuit and integrated circuit latching effect test method |
| CN113176749A (en) * | 2021-04-23 | 2021-07-27 | 广东天波信息技术股份有限公司 | Circuit for avoiding I/O port latch in power-on process of processor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101059767A (en) * | 2007-03-19 | 2007-10-24 | 北京航空航天大学 | Latch fault detection circuit suitable for satellite microprocessor |
| CN101102101A (en) * | 2007-07-09 | 2008-01-09 | 北京航空航天大学 | An automatic failure detection and removal circuit for plate-level single grain crossbar lock |
| CN101727122A (en) * | 2010-02-01 | 2010-06-09 | 哈尔滨工业大学 | Quadratic linear power system latching preventing circuit for system level CMOS integrated circuit |
| CN103762558A (en) * | 2014-01-21 | 2014-04-30 | 北京航空航天大学 | Recoverable power interface circuit resistant to single event latchup |
| CN104375549A (en) * | 2014-10-30 | 2015-02-25 | 中国电子科技集团公司第三十六研究所 | Latching-preventing circuit of CMOS device |
-
2015
- 2015-07-28 CN CN201510449782.1A patent/CN105823977A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101059767A (en) * | 2007-03-19 | 2007-10-24 | 北京航空航天大学 | Latch fault detection circuit suitable for satellite microprocessor |
| CN101102101A (en) * | 2007-07-09 | 2008-01-09 | 北京航空航天大学 | An automatic failure detection and removal circuit for plate-level single grain crossbar lock |
| CN101727122A (en) * | 2010-02-01 | 2010-06-09 | 哈尔滨工业大学 | Quadratic linear power system latching preventing circuit for system level CMOS integrated circuit |
| CN103762558A (en) * | 2014-01-21 | 2014-04-30 | 北京航空航天大学 | Recoverable power interface circuit resistant to single event latchup |
| CN104375549A (en) * | 2014-10-30 | 2015-02-25 | 中国电子科技集团公司第三十六研究所 | Latching-preventing circuit of CMOS device |
Non-Patent Citations (1)
| Title |
|---|
| 余永涛: "SRAM K6R4016V1D单粒子闩锁及防护试验研究", 《原子能科学技术》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108169661A (en) * | 2017-12-28 | 2018-06-15 | 天津芯海创科技有限公司 | Method of designing integrated circuit and integrated circuit latching effect test method |
| CN113176749A (en) * | 2021-04-23 | 2021-07-27 | 广东天波信息技术股份有限公司 | Circuit for avoiding I/O port latch in power-on process of processor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5955924B2 (en) | Electrostatic discharge protection circuit | |
| JP4651044B2 (en) | Circuit apparatus and method for protecting integrated semiconductor circuits | |
| CN103022996B (en) | Electronic static discharge protection circuit and electronic static discharge protection method | |
| WO2016112744A1 (en) | Anti-latch-up effect microprocessor reset circuit | |
| CN106451385B (en) | ESD protection circuit and integrated circuit | |
| CN109842103A (en) | ESD protection circuit | |
| CN101483339A (en) | Electrostatic protection method and circuit having detection control circuit | |
| CN106356823B (en) | The surge protection circuit being integrated in chip | |
| CN104332981A (en) | Power supply clamp ESD (Electronic Static Discharge) protection circuit combining direct current trigger and transient trigger | |
| CN103646945A (en) | Integrated circuit power supply esd protection circuit | |
| CN109756220A (en) | A kind of substrate electric potential selection circuit | |
| CN104577996A (en) | Power supply over-current protection circuit based on integrated circuit | |
| CN203675080U (en) | Trigger signal locking circuit | |
| CN105823977A (en) | Latch detection circuit and integrated circuit | |
| US20210265832A1 (en) | Leakage current detection and protection device, and power connector and electrical appliance employing the same | |
| CN112543021B (en) | Input-output circuit and circuit system | |
| CN107240913B (en) | Electrostatic discharge protection | |
| CN101938118B (en) | Electrostatic discharge protection circuit with multi-power area integrated circuit | |
| DE102013203076B4 (en) | Device with detection of the latch-up effect and method for forming this device | |
| CN208608973U (en) | A kind of current foldback circuit | |
| CN104836565A (en) | Output buffer capable of rapidly switching grid potential and electrostatic protection circuit | |
| US11418052B2 (en) | Power circuit and driving method thereof | |
| CN110794942B (en) | Reset chip circuit | |
| CN110058140B (en) | Go up electric voltage detection circuitry, electron device and thing networking device | |
| CN201336568Y (en) | Electrostatic protection circuit with detection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160803 |