CN112543021B

CN112543021B - Input-output circuit and circuit system

Info

Publication number: CN112543021B
Application number: CN202110190697.3A
Authority: CN
Inventors: 张昊
Original assignee: Kunyuan Microelectronics Nanjing Co ltd
Current assignee: Kunyuan Microelectronics Nanjing Co ltd
Priority date: 2021-02-20
Filing date: 2021-02-20
Publication date: 2021-05-11
Anticipated expiration: 2041-02-20
Also published as: CN112543021A

Abstract

The invention discloses an input-output circuit and a circuit system. The second input end of a first phase inversion unit of the input-output circuit is connected with the first end of a bias unit, the output end of the first phase inversion unit is connected with the control end of the first output unit, the input end of the first output unit is connected with a power signal input end, the first output end of the first output unit is connected with the first end of the bias unit, the second output end of the first output unit and the output end of the second output unit are used as the output ends of the input-output circuit, the second end of the bias unit is connected with the power signal input end, the third end of the bias unit is connected with the output end of the input-output circuit, the fourth end of the bias unit is connected with the ground end, and the bias unit is used for biasing the first output unit when a power signal provided by the power signal input end is equal to. The power-down protection of the input and output circuit can be realized on the basis of not increasing the power consumption, and meanwhile, the probability of damage to a circuit system is reduced.

Description

Input-output circuit and circuit system

Technical Field

The embodiment of the invention relates to the technical field of circuit protection, in particular to an input-output circuit and a circuit system.

Background

In a circuit system, a situation that an external signal is powered on before a power supply signal often occurs. For example, other circuits connected to an Input/Output (I/O) circuit in the circuit system operate normally after being started, and provide an external signal to an Output port of the I/O circuit. Or the driven port has a PULL-UP structure, and at this time, an external signal or the driven port reversely leaks electricity to a power supply in the circuit system through a driving transistor of the I/O circuit or an electrostatic protection structure, so that abnormal power-on or functional errors of the circuit system are caused, and the circuit system can even be burnt.

In the prior art, a current detection circuit may be disposed in a circuit system, and when the current detection circuit detects that an abnormal current flows into the I/O circuit, the current detection circuit may reset the circuit system to prevent the circuit system from malfunctioning. At this time, the circuit system is required to be in a power-on state, and the voltage and current brought by external signals cannot be inhibited, so that the circuit system is easily damaged by instantaneous large current. Or a backflow prevention circuit is arranged between the I/O circuit and other circuits to isolate the current backflow of the I/O circuit and other circuits. Or the voltage detection circuit is used for controlling the paths from each port of the driving transistor of the I/O circuit to the power supply in the circuit system through the switch, and the corresponding paths are cut off when abnormal voltage or current is detected, so that the protection function is realized. At this moment, the structure is complex, and power needs to be provided for the voltage detection circuit all the time, so that the power consumption is high.

Disclosure of Invention

The invention provides an input/output circuit and a circuit system, which are used for realizing power failure protection of the input/output circuit on the basis of not increasing the power consumption of the input/output circuit, inhibiting external signals and avoiding damage to the circuit system by abnormal signals through the input/output circuit.

In a first aspect, an embodiment of the present invention provides an input/output circuit, including a first inverting unit, a first output unit, a second output unit, and a biasing unit;

the control end of the first inverting unit is connected with a first control signal output end, the first input end of the first inverting unit is connected with the ground end, the second input end of the first inverting unit is connected with the first end of the biasing unit, the output end of the first inverting unit is connected with the control end of the first output unit, the input end of the first output unit is connected with a power signal input end, the first output end of the first output unit is connected with the first end of the biasing unit, the second output end of the first output unit and the output end of the second output unit are used as the output ends of the input and output circuit, the control end of the second output unit is connected with a second control signal output end, and the input end of the second output unit is connected with the ground end; the second end of the bias unit is connected with the power signal input end, the third end of the bias unit is connected with the output end of the input-output circuit, the fourth end of the bias unit is connected with the ground end, and the bias unit is used for biasing the first output unit when the power signal provided by the power signal input end is equal to zero.

Optionally, the bias unit comprises a first P-type transistor; the grid electrode of the first P-type transistor is connected with the power signal input end, the first pole of the first P-type transistor is connected with the second output end of the first output unit, and the second pole of the first P-type transistor and the base electrode of the first P-type transistor are connected with the second input end of the first inverting unit and the first output end of the first output unit.

Optionally, the bias unit further includes a second P-type transistor, a third P-type transistor, a fourth P-type transistor, a first N-type transistor, and a second N-type transistor;

the gate of the second P-type transistor is connected to the ground, the first pole of the second P-type transistor and the base of the second P-type transistor, the first pole of the third P-type transistor and the base of the third P-type transistor, the second pole of the fourth P-type transistor and the base of the fourth P-type transistor are connected to the first output terminal of the first output unit, the second pole of the second P-type transistor and the gate of the third P-type transistor and the second pole of the first N-type transistor are connected, the gate of the first N-type transistor and the second output terminal of the first output unit are connected, the first pole of the first N-type transistor and the gate of the second N-type transistor are connected to the power signal input terminal, the base of the first N-type transistor and the ground are connected, and the second pole of the third P-type transistor and the gate of the fourth P-type transistor and the gate of the second N-type transistor are connected to the ground The first pole of the second N-type transistor and the base of the second N-type transistor are connected to the ground terminal, and the first pole of the fourth P-type transistor is connected to the power signal input terminal.

Optionally, a channel width-to-length ratio of the second P-type transistor is smaller than a channel width-to-length ratio of the first N-type transistor.

Optionally, a channel width-to-length ratio of the third P-type transistor is greater than a channel width-to-length ratio of the second N-type transistor.

Optionally, the first inverting unit includes a fifth P-type transistor and a third N-type transistor;

a gate of the fifth P-type transistor and a gate of the third N-type transistor are used as control terminals of the first inverting unit, a first pole of the fifth P-type transistor and a base of the fifth P-type transistor are used as second input terminals of the first inverting unit, and a second pole of the fifth P-type transistor and a second pole of the third N-type transistor are used as output terminals of the first inverting unit; the first pole of the third N-type transistor and the base of the third N-type transistor are used as the first input end of the first inverting unit.

Optionally, the first output unit comprises a sixth P-type transistor; the second output unit comprises a fourth N-type transistor;

a gate of the sixth P-type transistor is used as a control terminal of the first output unit, a first pole of the sixth P-type transistor is used as an input terminal of the first output unit, a base of the sixth P-type transistor is used as a first output terminal of the first output unit, and a second pole of the sixth P-type transistor is used as a second output terminal of the first output unit; a gate of the fourth N-type transistor is used as a control terminal of the second output unit, a first pole and a base of the fourth N-type transistor are used as input terminals of the second output unit, and a second pole of the fourth N-type transistor is used as an output terminal of the second output unit.

Optionally, the input-output circuit further comprises a second inverting unit and a nor gate;

the power input end of the second phase reversal unit and the power input end of the NOR gate are connected with the power signal input end, the input end of the second phase reversal unit is connected with the data signal input end, the output end of the second phase reversal unit is connected with the first input end of the NOR gate, the second input end of the NOR gate is connected with the enabling signal input end, and the output end of the NOR gate serves as the first control signal output end.

Optionally, the input-output circuit further comprises a third inverting unit, a nand gate and a fourth inverting unit;

the power input end of the third inverting unit, the power input end of the NAND gate and the power input end of the fourth inverting unit are connected with the power signal input end, the input end of the third inverting unit is connected with the enable signal input end, the output end of the third inverting unit is connected with the first input end of the NAND gate, the second input end of the NAND gate is connected with the output end of the second inverting unit, the output end of the NAND gate is connected with the input end of the fourth inverting unit, and the output end of the fourth inverting unit serves as the second control signal output end.

In a second aspect, an embodiment of the present invention further provides a circuit system, including the input-output circuit described in any one of the first aspects.

According to the technical scheme of the embodiment of the invention, when the input/output circuit is powered off, the biasing unit controls the first output unit to bias, so that the backward flowing phenomenon of the output end of the input/output circuit to the power supply signal input end due to the influence of an external signal can be avoided, the power failure protection of the input/output circuit is realized, the external signal can be inhibited from being transmitted to the power supply signal input end through the first output unit, and the circuit system damage caused by other circuits for transmitting the external signal to the input/output circuit through the power supply signal input end is avoided. In addition, the bias unit has no power consumption when the power supply signal is at a high level, can work when the power supply signal is at zero, does not need to provide the power supply signal all the time, avoids the power consumption of the bias unit, and avoids the additional increase of the power consumption of input and output.

Drawings

FIG. 1 is a schematic diagram of an I/O circuit provided in the prior art;

fig. 2 is a schematic structural diagram of a current/voltage detection circuit provided in the prior art;

FIG. 3 is a schematic diagram of a protection circuit of an I/O circuit according to the prior art;

fig. 4 is a schematic structural diagram of an input/output circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another input/output circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another input/output circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of an alternative input/output circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another input/output circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of an I/O circuit provided in the prior art. As shown in fig. 1, the I/O circuit includes a first inverter 101, a nor gate 102, a second inverter 103, a first driving transistor MP1, a third inverter 104, a nand gate 105, a fourth inverter 106, and a second driving transistor MN 1. The power supply input ends of the first inverter 101, the nor gate 102, the second inverter 103, the third inverter 104, the nand gate 105 and the fourth inverter 106 are all connected with a power supply Vdd of the I/O circuit, the input end DATA of the I/O circuit is connected with the input end of the first inverter 101, the output end of the first inverter 101 is connected with the first input end of the nor gate 102 and the first input end of the nand gate 105, the enable end en of the I/O circuit is connected with the second input end of the nor gate 102 and the input end of the third inverter 104, the output end of the nor gate 102 is connected with the input end of the second inverter 103, the output end of the second inverter 103 is connected with the gate of the first driving transistor MP1, the source and the base of the first driving transistor MP1 are connected with the power supply Vdd, and the drain serves as the output end OUT of the I/O circuit. The output end of the third inverter 104 is connected to the second input end of the nand gate 105, the output end of the nand gate 105 is connected to the input end of the fourth inverter 106, the output end of the fourth inverter 106 is connected to the gate of the second driving transistor MN1, the source and the base of the second driving transistor MN1 are connected to the ground GND, and the drain is connected to the drain of the first driving transistor MP1, and is used as the output end OUT of the I/O circuit. As shown in fig. 1, when the power supply Vdd is not powered, i.e., when the power supply Vdd is zero, the power supply Vdd input to the power input terminal of the second inverter 103 is zero, and the signal output from the second inverter 103 is a low-level signal, the gate of the first driving transistor MP1 is a low-level signal, and the first driving transistor MP1 is turned on. If the external signal makes the output signal of the output terminal OUT of the I/O circuit greater than the difference of the forward conduction voltages of one PN junction of the power supplies Vdd, the PN junction between the drain and the base of the first driving transistor MP1 is turned on in the forward direction, the base of the first driving transistor MP1 is turned on with the power supply Vdd, and the external signal provided by the output terminal OUT of the I/O circuit flows back to the power supply Vdd through the first driving transistor MP1, which causes the abnormal power-on of the circuit system or the formation of a large current. Fig. 2 is a schematic structural diagram of a current/voltage detection circuit provided in the prior art. As shown in fig. 2, the current detection circuit includes a first comparator 201 and a reset circuit 202, a first input terminal of the first comparator 201 is connected to an output terminal OUT of the I/O circuit, a second input terminal of the first comparator 201 is connected to a reference voltage input terminal VREF, an output terminal of the first comparator 201 is connected to an input terminal of the reset circuit 202, and an output terminal of the reset circuit 202 is connected to the I/O circuit. When the output terminal OUT of the I/O circuit outputs an abnormal current or voltage, the abnormal current or voltage may be compared with the reference current or reference voltage provided by the reference voltage input terminal VREF, and an abnormal reset signal is formed and output to the reset circuit 202, and the reset circuit 202 outputs a reset signal according to the abnormal reset signal to reset the circuitry. When the current/voltage detection circuit shown in fig. 2 outputs a reset signal to reset the circuit system, the circuit system needs to be in a power-on state, and cannot suppress an abnormal signal output by the output terminal OUT of the I/O circuit, and when the abnormal signal is an instantaneous large current, the circuit system is easily damaged. Fig. 3 is a schematic diagram of a protection circuit of an I/O circuit according to the prior art. In conjunction with fig. 1 and 3, the protection circuit includes a second comparator 301, an inverter 302, and a first switch S1 and a second switch S2. A first input terminal of the second comparator 301 is connected to the output terminal OUT of the I/O circuit, a second input terminal of the second comparator 301 is connected to the reference voltage input terminal VREF, an output terminal of the second comparator 301 is connected to the input terminal of the inverter 302 and the control terminal of the first switch S1, an output terminal of the inverter 302 is connected to the control terminal of the second switch S2, two first switches S1 are respectively connected in series between the gate and the source, and the base and the drain of the first driving transistor MP1, and two second switches S2 are respectively connected in series between the source and the base, and the gate and the drain of the first driving transistor MP 1. When the output terminal OUT of the I/O circuit outputs an abnormal current or voltage, the abnormal current or voltage may be compared with the reference current or reference voltage provided by the reference voltage input terminal VREF, and the two first switches S1 may be controlled to be turned on, and the two second switches S2 may be turned off, so that the first driving transistor MP1 may be controlled to be in an off state, thereby implementing the abnormal protection of the I/O circuit. As can be seen from fig. 3, the protection circuit includes a plurality of switches, the structure is complex, and the reference voltage provided by the reference voltage input terminal VREF and the second comparator 301 require power, which increases the power consumption of the I/O circuit.

In view of the above technical problems, an embodiment of the present invention provides an input/output circuit. Fig. 4 is a schematic structural diagram of an input/output circuit according to an embodiment of the present invention. As shown in fig. 4, the input-output circuit includes a first inverting unit 110, a first output unit 120, a second output unit 130, and a biasing unit 140; the control terminal of the first inverting unit 110 is connected to the first control signal output terminal CTRL1, the first input terminal of the first inverting unit 110 is connected to the ground terminal GND, the second input terminal of the first inverting unit 110 is connected to the first terminal of the bias unit 140, the output terminal of the first inverting unit 110 is connected to the control terminal C1 of the first output unit 120, the input terminal of the first output unit 120 is connected to the power signal input terminal VDD, the first output terminal of the first output unit 120 is connected to the first terminal of the bias unit 140, the second output terminal of the first output unit 120 and the output terminal of the second output unit 130 are used as the output terminals OUT1 of the input and output circuit, the control terminal of the second output unit 130 is connected to the second control signal output terminal CTRL2, and the input terminal of the second output unit 130 is connected to the ground terminal GND; the second terminal of the bias unit 140 is connected to the power signal input terminal VDD, the third terminal of the bias unit 140 is connected to the output terminal OUT1 of the input/output circuit, the fourth terminal of the bias unit 140 is connected to the ground terminal GND, and the bias unit 140 is configured to bias the first output unit 120 when the power signal provided by the power signal input terminal VDD is equal to zero.

Specifically, the first control signal input CTRL1 provides a first control signal to the control terminal of the first inverting unit 110 for controlling the inverting state of the first inverting unit 110. The second control signal input CTRL2 provides a second control signal to the second output unit 130 for controlling the output state of the second output unit 130. When the input/output circuit is not powered on, the power signal provided by the power signal input terminal VDD is equal to zero, and the output signal output by the output terminal OUT1 of the input/output circuit can be provided to the second input terminal of the first inverting unit 110 through the biasing unit 140, so as to control the first inverting unit 110 to output the output signal to the control terminal C1 of the first output unit 120. When the signal output by the output end OUT1 of the input/output circuit is abnormal, the first output unit 120 can be controlled to be cut off, so that when the input/output circuit is not powered on, the output end OUT1 of the input/output circuit is influenced by an external signal to have a backward flow phenomenon to the power supply signal input end VDD, power failure protection of the input/output circuit is realized, meanwhile, the external signal can be inhibited from being transmitted to the power supply signal input end VDD through the first output unit 120, and circuit system damage caused by other circuits that the external signal is transmitted to the input/output circuit through the power supply signal input end VDD is avoided. Meanwhile, the bias unit 140 can operate when the power signal is zero, and the power signal does not need to be provided all the time, thereby reducing the power consumption of the bias unit 140.

In addition, after the input/output circuit is powered on, the power signal provided by the power signal input terminal VDD is at a high level, and the first output terminal of the first output unit 120 can output the high level to the first terminal of the bias unit 140, and since the first output unit 120 itself has a conduction voltage drop, the potential of the first terminal of the bias unit 140 is lower than the power signal. Meanwhile, the second end of the bias unit 140 is connected to the power signal, so that the first end of the bias unit 140 can be pulled up, the potential of the first end of the bias unit 140 is the power signal, the power consumption of the bias unit 140 after the input/output circuit is powered on is reduced, and the power consumption additionally increased when the input/output circuit normally works by the bias unit 140 can be reduced.

Fig. 5 is a schematic structural diagram of another input/output circuit according to an embodiment of the present invention. As shown in fig. 5, the bias unit 140 includes a first P-type transistor P1; a gate of the first P-type transistor P1 is connected to the power signal input terminal VDD, a first pole of the first P-type transistor P1 is connected to the second output terminal of the first output unit 120, and a second pole of the first P-type transistor P1 and a base of the first P-type transistor P1 are connected to the second input terminal of the first inverting unit 110 and the first output terminal of the first output unit 120.

Specifically, the first P-type transistor P1 is turned on at a low level and turned off at a high level. When the input/output circuit is not powered on, the power signal provided by the power signal input terminal VDD is equal to zero, the first P-type transistor P1 is turned on, and the signal output by the output terminal OUT1 of the input/output circuit can be transmitted to the second input terminal of the first inverting unit 110 through the first P-type transistor P1, so as to control the first inverting unit 110 to output the output signal to the control terminal C1 of the first output unit 120. When the signal output by the output end OUT1 of the input/output circuit is abnormal, for example, high level, the first output unit 120 may be controlled to be turned off, so that when the input/output circuit is not powered on, the output end OUT1 of the input/output circuit is influenced by an external signal to have a backward flow phenomenon to the power supply signal input end VDD, thereby implementing power failure protection of the input/output circuit, and simultaneously, the external signal may be inhibited from being transmitted to the power supply signal input end VDD through the first output unit 120, and avoiding damage to a circuit system caused by other circuits for which the external signal is transmitted to the input/output circuit through the power supply signal input end VDD.

With continued reference to fig. 5, the bias unit 140 further includes a second P-type transistor P2, a third P-type transistor P3, a fourth P-type transistor P4, a first N-type transistor N1, and a second N-type transistor N2; a gate of the second P-type transistor P2 is connected to a ground terminal GND, a first pole of the second P-type transistor P2 and a base of the second P-type transistor P2, a first pole of the third P-type transistor P3 and a base of the third P-type transistor P3, and a second pole of the fourth P-type transistor P4 and a base of the fourth P-type transistor P4 are connected to a first output terminal of the first output unit 120, a second pole of the second P-type transistor P2 and a gate of the third P-type transistor P3 and a second pole of the first N-type transistor N1 are connected, a gate of the first N-type transistor N1 is connected to a second output terminal of the first output unit 120, a first pole of the first N-type transistor N1 and a gate of the second N-type transistor N2 are connected to a power signal input terminal, a base of the first N-type transistor N1 and a ground terminal GND, a third pole of the third P-type transistor P3 and a gate of the fourth P3985 are connected to a second N-type transistor N1, a first pole of the second N-type transistor N2 and a base of the second N-type transistor N2 are connected to the ground GND, and a first pole of the fourth P-type transistor P4 is connected to the power signal input terminal VDD.

Specifically, the second P-type transistor P2, the third P-type transistor P3, and the fourth P-type transistor P4 are turned on at a low level and turned off at a high level. The first N-type transistor N1 and the second N-type transistor N2 are turned on at a high level and turned off at a low level. The gate of the second P-type transistor P2 is connected to the ground GND, so the second P-type transistor P2 is always in a conductive state. When the input/output circuit is not powered on, the power signal provided by the power signal input terminal VDD is equal to zero, the first P-type transistor P1 is turned on, and the output signal output by the output terminal OUT1 of the input/output circuit can be transmitted to the second input terminal of the first inverting unit 110 through the first P-type transistor P1, so as to control the first inverting unit 110 to output the output signal to the control terminal C1 of the first output unit 120. When the signal output by the output terminal OUT1 of the input/output circuit is abnormal, for example, high level, the first output unit 120 may be controlled to be turned off, so that the backflow phenomenon of the output terminal OUT1 of the input/output circuit to the power signal input terminal VDD due to the influence of an external signal may be avoided when the input/output circuit is not powered on. The first P-type transistor P1, the second P-type transistor P2, the third P-type transistor P3, the fourth P-type transistor P4, the first N-type transistor N1 and the second N-type transistor N2 are all powered by the power supply signal provided by the power supply signal input terminal VDD, and no switch or other large-resistance device exists in the signal transmission path, so the operating frequency of the input/output circuit is not affected.

In addition, when the input/output circuit is powered on, the power signal provided by the power signal input terminal VDD is at a high level, the first P-type transistor P1 is turned off, and the second N-type transistor N2 is turned on. The first output terminal of the first output unit 120 may output a high level to the first terminal of the bias unit 140, and since the first output unit 120 itself has a conduction voltage drop, the potential of the first terminal of the bias unit 140 is less than the power signal. The low level of the ground GND is transmitted to the gate of the fourth P-type transistor P4 through the second N-type transistor N2, which controls the fourth P-type transistor P4 to be turned on, and the power signal provided by the power signal input terminal VDD is transmitted to the first terminal of the bias unit 140 through the fourth P-type transistor P4. Moreover, when the fourth P-type transistor P4 transmits a high level, the threshold loss voltage drop is approximately zero, so that the potential of the first terminal of the bias unit 140 can be increased to the power signal provided by the power signal input terminal VDD, so that there is no voltage difference at a part of the bias unit 140, and the power consumption of the bias unit 140 can be reduced. Meanwhile, the bias unit 140 can operate when the power signal is zero, and the power signal does not need to be provided all the time, thereby further reducing the power consumption of the bias unit 140.

On the basis of the above technical solution, the channel width-to-length ratio of the second P-type transistor P2 is smaller than that of the first N-type transistor N1.

Specifically, the gate of the second P-type transistor P2 is connected to the ground terminal GND, so the second P-type transistor P2 is always in a conductive state. When the signal output from the output terminal OUT1 of the input/output circuit is an abnormal signal, for example, greater than the power supply signal, the signal output from the output terminal OUT1 of the input/output circuit controls the first N-type transistor N1 to be turned on, the second P-type transistor P2 and the first N-type transistor N1 are simultaneously turned on, the potential output from the second P-type transistor P2 and the first N-type transistor N1 is made close to the power supply voltage, i.e., close to zero, by setting the channel width-length ratio of the second P-type transistor P2 to be smaller than the channel width-length ratio of the first N-type transistor N1, the third P-type transistor P3 is turned on, and the power supply signal is input to the gate of the second N-type transistor N2 to be in an off state, so that the gate of the fourth P-type transistor P4 is the abnormal signal output from the output terminal OUT1 of the input/output circuit, and controls the fourth P-type transistor P4 to be turned off, thereby limiting the power supply current flowing to the output circuit from the output terminal OUT1, the abnormal power-on or large current input of the power supply is avoided, and the power-down protection function is realized.

The channel width-to-length ratio of the second P-type transistor P2 is much smaller than that of the first N-type transistor N1, so that the gate potential of the third P-type transistor P3 is zero, and the third P-type transistor P3 is controlled to be turned on. Illustratively, the width-to-length ratio of the second P-type transistor P2 may be set to be much less than 1, and at this time, the current flowing through the second P-type transistor P2 is controllable and small, and small power consumption of the bias unit 140 may be achieved.

On the basis of the above technical solution, the channel width-to-length ratio of the third P-type transistor P3 is larger than that of the second N-type transistor N2.

Specifically, when the input/output circuit is powered on, in the process that the power signal provided by the power signal input terminal VDD is raised from zero to a high level, the power signal controls the second N-type transistor N2 to be turned on, and the input/output circuit operates normally. When the signal output by the output terminal OUT1 of the input/output circuit is at a high level, the first N-type transistor N1 is controlled to be turned on, the gate potential of the third P-type transistor P3 gradually rises, and the third P-type transistor P3 and the second N-type transistor N2 may be turned on simultaneously. By setting the channel width-length ratio of the third P-type transistor P3 to be greater than the channel width-length ratio of the second N-type transistor N2, the output potential of the third P-type transistor P3 and the second N-type transistor N2 is close to the voltage provided by the first output terminal of the first output unit 120, and is at a high level, so that the fourth P-type transistor P4 can be ensured to be turned off, and the power consumption of the input-output circuit in the power-on process is reduced.

Optionally, the channel width-to-length ratio of the third P-type transistor P3 is much larger than that of the second N-type transistor N2, so that the output voltage of the third P-type transistor P3 and the second N-type transistor N2 is close to the voltage provided by the first output terminal of the first output unit 120, and the fourth P-type transistor P4 is guaranteed to be turned off.

Fig. 6 is a schematic structural diagram of another input/output circuit according to an embodiment of the present invention. As shown in fig. 6, the first inverting unit 110 includes a fifth P-type transistor P5 and a third N-type transistor N3; a gate of the fifth P-type transistor P5 and a gate of the third N-type transistor N3 are used as control terminals of the first inverting unit 110, a first pole of the fifth P-type transistor P5 and a base of the fifth P-type transistor P5 are used as second input terminals of the first inverting unit 110, and a second pole of the fifth P-type transistor P5 and a second pole of the third N-type transistor N3 are used as output terminals of the first inverting unit 110; a first pole of the third N-type transistor N3 and a base of the third N-type transistor N3 serve as a first input terminal of the first inverting unit 110.

Specifically, the fifth P-type transistor P5 and the third N-type transistor N3 form an inverter, the first P-type transistor P1 provides a signal output from the output terminal OUT1 of the input-output circuit to power the fifth P-type transistor P5, and the ground terminal GND provides power to the third N-type transistor N3. When the input/output circuit is not powered on, the power signal provided by the power signal input terminal VDD is equal to zero, the first P-type transistor P1 is turned on, and the signal output by the output terminal OUT1 of the input/output circuit can be transmitted to the fifth P-type transistor P5 through the first P-type transistor P1. At this time, the first control signal output terminal CTRL1 outputs a low level to control the fifth P-type transistor P5 to be turned on, and the third N-type transistor N3 is turned off, so that the signal output by the output terminal OUT1 of the input/output circuit is transmitted to the control terminal C1 of the first output unit 120 through the fifth P-type transistor, and when the signal output by the output terminal OUT1 of the input/output circuit is abnormal, for example, a high level, the first output unit 120 can be controlled to be turned off, so that the backward flow phenomenon of the output terminal OUT1 of the input/output circuit to the power signal input terminal VDD due to the influence of an external signal can be avoided when the input/output circuit is not powered on.

In addition, when the input/output circuit is not powered on and the power signal provided by the power signal input terminal VDD is equal to zero, the second control signal output terminal CTRL2 outputs a low level to control the second output unit 130 to be turned off.

Fig. 7 is a schematic structural diagram of another input/output circuit according to an embodiment of the present invention. As shown in fig. 7, the first output unit 120 includes a sixth P-type transistor P6; the second output unit 130 includes a fourth N-type transistor N4; a gate of the sixth P-type transistor P6 is used as the control terminal of the first output unit 120, a first pole of the sixth P-type transistor P6 is used as the input terminal of the first output unit 120, a base of the sixth P-type transistor P6 is used as the first output terminal of the first output unit 120, and a second pole of the sixth P-type transistor P6 is used as the second output terminal of the first output unit 120; a gate of the fourth N-type transistor N4 serves as a control terminal of the second output unit 130, a first pole and a base of the fourth N-type transistor N4 serve as input terminals of the second output unit 130, and a second pole of the fourth N-type transistor N4 serves as an output terminal of the second output unit 130.

Specifically, the sixth P-type transistor P6 is turned on at a low level and turned off at a high level. When the input/output circuit is not powered on, a power signal provided by a power signal input end VDD is equal to zero, the first P-type transistor P1 is turned on, a signal output by an output end OUT1 of the input/output circuit can be transmitted to the fifth P-type transistor P5 through the first P-type transistor P1, at this time, the fifth P-type transistor P5 is turned on, a signal output by an output end OUT1 of the input/output circuit is transmitted to the gate of the sixth P-type transistor P6 through the fifth P5, when the signal output by the output end OUT1 of the input/output circuit is abnormal, for example, greater than the power signal, the sixth P-type transistor P6 is turned off, so that a backflow phenomenon of the power signal input end VDD caused by the influence of an external signal at the output end OUT1 of the input/output circuit can be avoided when the input/output circuit is not powered on, and power-down protection of the input. When the input/output circuit is not powered on and the power signal provided by the power signal input terminal VDD is equal to zero, the second control signal output terminal CTRL2 outputs a low level to control the fourth N-type transistor N4 to be turned off, thereby preventing the fourth N-type transistor N4 from inputting a low level of the ground GND.

Fig. 8 is a schematic structural diagram of another input/output circuit according to an embodiment of the present invention. As shown in fig. 8, the input-output circuit further includes a second inverting unit 150 and an nor gate 160; a power input terminal of the second inverting unit 150 and a power input terminal of the nor gate 160 are connected to the power signal input terminal VDD, an input terminal of the second inverting unit 150 is connected to the data signal input terminal IN, an output terminal of the second inverting unit 150 is connected to a first input terminal of the nor gate 160, a second input terminal of the nor gate 160 is connected to the enable signal input terminal EN, and an output terminal of the nor gate 160 serves as a first control signal output terminal CTRL 1.

Specifically, the power input terminal of the second inverting unit 150 and the power input terminal of the nor gate 160 are connected to the power signal input terminal VDD, and when the input/output circuit is not powered on and the power signal provided by the power signal input terminal VDD is equal to zero, the output terminal of the nor gate 160 outputs a low level, i.e., the first control signal output terminal CTRL1 outputs a low level. At this time, the fifth P-type transistor P5 can be controlled to be turned on, the third N-type transistor N3 is turned off, and the signal output by the output terminal OUT1 of the input/output circuit controls the sixth P-type transistor P6 to be turned off, so that the phenomenon that the output terminal OUT1 of the input/output circuit is influenced by an external signal to flow backwards to the power signal input terminal VDD when the input/output circuit is not powered on is avoided.

With continued reference to fig. 8, the input-output circuit further includes a third inverting unit 170, a nand gate 180, and a fourth inverting unit 190; the power input end of the third inverting unit 170, the power input end of the nand gate 180 and the power input end of the fourth inverting unit 190 are connected to the power signal input end VDD, the input end of the third inverting unit 170 is connected to the enable signal input end EN, the output end of the third inverting unit 170 is connected to the first input end of the nand gate 180, the second input end of the nand gate 180 is connected to the output end of the second inverting unit 150, the output end of the nand gate 180 is connected to the input end of the fourth inverting unit 190, and the output end of the fourth inverting unit 190 serves as a second control signal output end CTRL 2.

Specifically, the power input terminal of the third inverting unit 170, the power input terminal of the nand gate 180, and the power input terminal of the fourth inverting unit 190 are connected to the power signal input terminal VDD, and when the input/output circuit is not powered on and the power signal provided by the power signal input terminal VDD is equal to zero, the output terminal of the fourth inverting unit 190 outputs a low level, that is, the second control signal output terminal CTRL2 outputs a low level, so as to control the fourth N-type transistor N4 to be turned off, and avoid a low level of the ground GND at the input terminal of the fourth N-type transistor N4.

In addition, when the input/output circuit is powered on and the power supply signal provided by the power supply signal input end VDD is at a high level, the input/output circuit works normally. When the enable signal input terminal EN provides a low level, the data signal provided by the data signal input terminal IN is inverted by the second inverting unit 150, then passes through the nor gate 160, is inverted again, passes through the first inverting unit 110, and is transmitted to the gate of the sixth P-type transistor P6. Meanwhile, the low level provided by the enable signal input end EN passes through the third inverting unit 170 and is output to the nand gate 180, the second input end of the nand gate 180 is connected with the output end of the second inverting unit 150, that is, the second input end of the nand gate 180 inputs the inverted signal of the data signal. The nand gate 180 inverts the data signal again, and then the data signal is inverted by the fourth inverting unit 190 and transmitted to the gate of the fourth N-type transistor N4. When the data signal is at a high level, the gate of the sixth P-type transistor P6 is at a low level, the gate of the fourth N-type transistor N4 is at a low level, the sixth P-type transistor P6 is controlled to be turned on, the fourth N-type transistor N4 is controlled to be turned off, and the output terminal OUT1 of the input/output circuit outputs the power signal at a high level. When the data signal is at a low level, the gate of the sixth P-type transistor P6 is at a high level, the gate of the fourth N-type transistor N4 is at a high level, the sixth P-type transistor P6 is controlled to be turned off, the fourth N-type transistor N4 is controlled to be turned on, and the output terminal OUT1 of the input/output circuit outputs the ground GND signal, which is at a low level. Thereby realizing the normal operation of the input and output circuit.

When the enable signal input terminal EN is supplied with a high level, the gate of the sixth P-type transistor P6 is at a high level and the gate of the fourth N-type transistor N4 is at a low level regardless of whether the data signal is at a high level or a low level, the sixth P-type transistor P6 and the fourth N-type transistor N4 are both turned off, and the input/output circuit stops operating.

The embodiment of the invention also provides a circuit system. The circuit system comprises the input-output circuit provided by any embodiment of the invention.

Specifically, the circuitry may be integrated on a wafer to form a chip. The chip comprises the input and output circuit, and the input and output circuit comprises the biasing unit, so that the first output unit can be biased when the input and output circuit is powered down, and other circuit output reverse currents connected with the input and output circuit in the chip are prevented from being transmitted to a power supply through the first output unit, so that the input and output circuit can be subjected to power failure protection, and the power supply abnormity or large input current of the chip is avoided. And simultaneously, the power consumption of the biasing unit can be reduced.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An input-output circuit is characterized by comprising a first inverting unit, a first output unit, a second output unit and a biasing unit;

the control end of the first inverting unit is connected with a first control signal output end, the first input end of the first inverting unit is connected with the ground end, the second input end of the first inverting unit is connected with the first end of the biasing unit, the output end of the first inverting unit is connected with the control end of the first output unit, the input end of the first output unit is connected with a power signal input end, the first output end of the first output unit is connected with the first end of the biasing unit, the second output end of the first output unit and the output end of the second output unit are used as the output ends of the input and output circuit, the control end of the second output unit is connected with a second control signal output end, and the input end of the second output unit is connected with the ground end; the second end of the bias unit is connected with the power supply signal input end, the third end of the bias unit is connected with the output end of the input-output circuit, the fourth end of the bias unit is connected with the ground end, and the bias unit is used for biasing the first output unit when the power supply signal provided by the power supply signal input end is equal to zero;

the bias unit comprises a first P-type transistor; the grid electrode of the first P-type transistor is connected with the power supply signal input end, the first pole of the first P-type transistor is connected with the second output end of the first output unit, and the second pole of the first P-type transistor and the substrate of the first P-type transistor are connected with the second input end of the first inverting unit and the first output end of the first output unit;

the bias unit further comprises a second P-type transistor, a third P-type transistor, a fourth P-type transistor, a first N-type transistor and a second N-type transistor;

the gate of the second P-type transistor is connected to the ground, the first pole of the second P-type transistor and the substrate of the second P-type transistor, the first pole of the third P-type transistor and the substrate of the third P-type transistor, and the second pole of the fourth P-type transistor and the substrate of the fourth P-type transistor are connected to the first output terminal of the first output unit, the second pole of the second P-type transistor and the gate of the third P-type transistor and the second pole of the first N-type transistor are connected, the gate of the first N-type transistor and the second output terminal of the first output unit are connected, the first pole of the first N-type transistor and the gate of the second N-type transistor are connected to the power signal input terminal, the substrate of the first N-type transistor and the ground are connected, and the second pole of the third P-type transistor and the gate of the fourth P-type transistor and the gate of the second N-type transistor are connected to the ground The first pole of the second N-type transistor and the substrate of the second N-type transistor are connected to the ground terminal, and the first pole of the fourth P-type transistor is connected to the power supply signal input terminal;

the first inverting unit comprises a fifth P-type transistor and a third N-type transistor;

a gate of the fifth P-type transistor and a gate of the third N-type transistor are used as control terminals of the first inverting unit, a first pole of the fifth P-type transistor and a substrate of the fifth P-type transistor are used as second input terminals of the first inverting unit, and a second pole of the fifth P-type transistor and a second pole of the third N-type transistor are used as output terminals of the first inverting unit; a first pole of the third N-type transistor and a substrate of the third N-type transistor are used as a first input end of the first inverting unit; the first control signal input end provides a first control signal to control the fifth P-type transistor and the third N-type transistor to be switched on or switched off;

the first output unit includes a sixth P-type transistor; the second output unit comprises a fourth N-type transistor;

a gate of the sixth P-type transistor is used as a control terminal of the first output unit, a first pole of the sixth P-type transistor is used as an input terminal of the first output unit, a substrate of the sixth P-type transistor is used as a first output terminal of the first output unit, and a second pole of the sixth P-type transistor is used as a second output terminal of the first output unit; a gate of the fourth N-type transistor is used as a control terminal of the second output unit, a first pole and a substrate of the fourth N-type transistor are used as input terminals of the second output unit, and a second pole of the fourth N-type transistor is used as an output terminal of the second output unit.

2. The input-output circuit of claim 1, wherein the channel width-to-length ratio of the second P-type transistor is smaller than the channel width-to-length ratio of the first N-type transistor.

3. The input-output circuit of claim 2, wherein the third P-type transistor has a channel width-to-length ratio that is greater than a channel width-to-length ratio of the second N-type transistor.

4. The input-output circuit of claim 1, further comprising a second inverting unit and an nor gate;

5. The input-output circuit of claim 4, further comprising a third inverting unit, a NAND gate, and a fourth inverting unit;

6. A circuit system comprising the input-output circuit of any one of claims 1 to 5.