JPH10341141A - Output stage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an output stage circuit for a power supply circuit or the like through the adoption of a MOS transistor(TR) so as to reduce the power consumption where no reverse drain current flows as in the case of adoption of a bipolar TR and no loss voltage is provided like a reverse flow prevention circuit using a diode. SOLUTION: A current interrupting switch 36 is placed in series with a P- channel MOS output TR 100 and a power supply voltage monitor circuit 37 conducts ON/OFF control of the current interrupting switch 36. Thus, even when a level at a power terminal 1 is reduced, a reverse current flowing due to a parasitic diode between a drain 13 and a back gate 11 of the P-channel MOS output TR 100 can be blocked. Also a reverse current due to a decreased level of a gate 10 resulting from a power supply voltage drop of a differential amplifier 9 is prevented. A P-channel MOS TR is employed as a current interrupting switch.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output stage circuit using a MOS output transistor.

[0002]

2. Description of the Related Art In recent years, portable devices such as portable telephones have rapidly spread. In response to the demand for long-term operation of these portable devices, there is an increasing demand for lower current consumption of electric circuits. However, in the case where an output stage circuit such as a power supply circuit requiring a current supply capability is configured using a bipolar transistor circuit which has conventionally been the mainstream in an analog circuit,
Even when the output current is small, since the base current for extracting the maximum output current is supplied to the base of the output transistor, it is difficult to reduce the current consumption of the circuit.

Therefore, in applications where current consumption is particularly a problem, the current consumption is often reduced by using a MOS transistor as a voltage control device for an output element in an output stage circuit. Less than,
As an example of a conventional output stage circuit having a MOS output transistor as an output element, a constant voltage circuit using a P-channel MOS output transistor as an output element, that is, a constant voltage circuit for supplying a source (discharge) current to an external circuit The configuration and operation will be described with reference to FIG.

In FIG. 4, reference numeral 1 denotes a power supply terminal of an output stage circuit, to which an external power supply 2 is connected. The external power supply 2 is mainly a battery in the case of a portable device, and may be removed during use. Reference numeral 3 denotes a reference voltage terminal of the constant voltage circuit, to which a reference voltage of a reference voltage source 4 is applied. Reference numeral 5 denotes a constant voltage output terminal. In the case of a constant voltage circuit, a bypass capacitor 6 and a load 7 for improving high frequency characteristics are connected. Reference numeral 8 denotes a constant current source, which is necessary for biasing the constant voltage circuit, but does not need to be adjusted to the maximum current unlike the output stage circuit using the bipolar transistor. Alternatively, the condition for the P-channel MOS output transistor 100 or the output stage control differential amplifier 9 to be in the active state may be satisfied. 10,1
Reference numerals 1, 12, and 13 denote the gate, back gate, source, and drain of the P-channel MOS output transistor 100 in the output stage, respectively.

Next, the basic operation of the circuit shown in FIG. 4 will be described. First, the differential amplifier 9 compares the voltage of the reference voltage terminal 3 with the voltage of the constant voltage output terminal 5. When the voltage at the constant voltage output terminal 5 is higher than the voltage at the reference voltage terminal 3, the voltage at the gate 10 of the P-channel MOS output transistor 100 is increased to turn off the P-channel MOS output transistor 100. To lower the voltage of the constant voltage output terminal 5. Conversely, when the voltage at the constant voltage output terminal 5 is lower than the voltage at the reference voltage terminal 3, the voltage at the gate 10 of the P-channel MOS output transistor 100 is reduced, and the voltage at the constant voltage output terminal 5 is increased. As a result, the voltage of the constant voltage output terminal 5 is controlled so as to be always equal to the voltage of the reference voltage terminal 3, and the entire circuit of FIG. 4 operates as a constant voltage circuit.

[0006]

However, in the conventional configuration using the P-channel MOS output transistor 100 shown in FIG. 4 as an output element, the external power supply voltage applied to the power supply terminal 1 decreases due to a momentary interruption of the power supply. When the voltage of the constant voltage output terminal 5 becomes higher than the external power supply voltage of the power supply terminal 1, the current flows backward from the constant voltage output terminal 5 toward the power supply terminal 1 in the two modes described below. There is. As a specific example where this is particularly problematic, it is necessary to hold the internal power supply voltage for a certain period in order to save information of the microcomputer at the moment of a power failure such as when the battery is disconnected in a portable device or the like. In such a case, it is conceivable that the internal power supply voltage rapidly drops due to the reverse flow of the current, the internal power supply voltage cannot be held, and the microcomputer cannot save the information.

[0007] In the above description, the expression that the current flows backward means that the capacitance of the bypass capacitor 6 and the like connected to the constant voltage output terminal 5 originally tries to maintain the electric charge, while the power supply voltage is By lowering, it is expressed that the parasitic diode described in FIGS. 5 and 6 is extracted by energizing toward the power supply. In this figure, it is said that the electric current accumulated by the bypass capacitor 6 flows backward.

The reason why the current flows backward even when the battery is disconnected is that there are many circuits such as a constant current source circuit through which the current flows even when the battery is removed. In this case, since the bypass capacitor 6 works as a substitute for the power supply, the charge is normally discharged through all the circuits that consume current when there is a battery (the circuit through which current flows even if the battery is removed). In particular, when an instantaneous large current flows to lower the power supply terminal voltage, the current is a reverse current to that of a low impedance, so that the problem becomes more serious.

Before describing the first current reverse mode, a parasitic diode in a P-channel MOS output transistor will be described. FIG. 5 shows a P channel M
FIG. 2 is a schematic diagram showing a cross-sectional structure of an OS output transistor 100. However, parts that are not essential to the present invention, such as LOCOS, are not shown. In FIG.
Reference numerals 10 and 14 indicate a gate and a gate terminal of the P-channel MOS output transistor 100, respectively, reference numerals 12 and 16 indicate a source and a source terminal of the P-channel MOS output transistor 100, and reference numerals 13 and 17 indicate a P-channel MOS output transistor 100, respectively. A drain and a drain terminal are shown, and each symbol corresponds to FIG. In this case, the source and the drain are determined for the purpose of explanation, but actually, which is the source and which is the drain is determined by the direction in which the voltage is applied, and there is essentially no difference in structure.

Reference numerals 11 and 15 denote a back gate and a back gate terminal of the P-channel MOS output transistor 100, respectively.
The back gate of 00 is N-type. 20 is a gate oxide film. As can be seen from FIG. 5, the P-channel MOS output transistor 100 has a parasitic diode 1 between the source 12 and the drain 13 and the back gate 11.
It has essentially 8,19.

Based on the above, the first current reverse flow mode will be described. In the case of a standard output circuit configuration as shown in FIG. 4, the back gate 11 of the P-channel MOS output transistor 100 is connected to the power supply terminal 1 which is the maximum voltage of the circuit.
Or the common connection with the source 12 of the P-channel MOS output transistor 100. In the case of FIG. 4, both connections are the same.

Hereinafter, the first current reverse mode will be described with reference to FIG. 6 in which the output stage is extracted and includes a parasitic diode. FIG. 6B corresponds to the connection state of FIG. In this state, as described with reference to FIG. 5, since the parasitic diodes 18 and 19 are present and the parasitic diode 18 is short-circuited, only the parasitic diode 19 is eventually present. .

Therefore, when the voltage of the power supply terminal 1 is higher than that of the constant voltage output terminal 5, the parasitic diode 19 is reverse-biased and has no effect on the circuit, but the voltage of the constant voltage output terminal 5 is higher than the voltage of the power supply terminal 1. It can be seen that, under conditions that increase the forward voltage of the PN junction by about 0.6 V or more, the parasitic diode 19 is biased in the forward direction and a large current flows. This is equivalent to a power supply being short-circuited, so that in the worst case such as when there is no current limitation, there is a possibility of element destruction. The element destruction means that, for example, when a large capacitor is used in the output stage and the power supply terminal becomes 0 V in some time, the parasitic diode in the output stage is turned on by using the capacitor as a power supply. This parasitic diode is the same as a short circuit between the power supply and the ground, so that if a current density exceeding an allowable value occurs, the PN junction may be destroyed. Its frequency is expected to be low.

There are several methods for preventing the current from flowing backward in the first current reverse mode. As a first method, as shown in FIG. 6A, there is a method in which the back gate 11 of the P-channel MOS output transistor 100 is floated without being connected to anywhere. As a second method, there is a method of adding a backflow prevention diode 21 as shown in FIG. As a third method, as shown in FIG. 6D, a method of connecting two P-channel MOS output transistors 100 and 101 in series and connecting the parasitic diodes 19 and 26 in opposite directions is used. is there. Further, as a fourth method, FIG.
As shown, two P-channel MOS output transistors 100 and 102 are connected in series,
There is a method of connecting the terminals 33 so that they are opposite to each other.

In FIG. 6D, reference numeral 22 denotes a gate of the P-channel MOS output transistor 101;
Back gate of the channel MOS output transistor 101; 24, the source of the P-channel MOS output transistor 101; 25, the P-channel MOS output transistor 10;
Reference numeral 26 denotes a parasitic diode between the source and the back gate of the P-channel MOS output transistor 101;
27 is a parasitic diode between the drain and back gate of the P-channel MOS output transistor 101, and 28 is a common gate of the P-channel MOS output transistors 100 and 101.

In FIG. 6E, reference numeral 29 denotes a gate of the P-channel MOS output transistor 102;
The back gate of the channel MOS output transistor 102, 31 is the source of the P channel MOS output transistor 102, 32 is the P channel MOS output transistor 10
2, a parasitic diode between the source and the back gate of the P-channel MOS output transistor 102;
34 is a parasitic diode between the drain and back gate of the P-channel MOS output transistor 102, and 35 is a common gate of the P-channel MOS output transistors 100 and 102.

Although FIGS. 6 (a) and 6 (c) to 6 (e) have a circuit configuration in which the parasitic diode does not work, each of them has problems. First, the floating state of the back gate 11 shown in FIG. 6A does not fix the back gate potential.
Characteristics and operations are likely to be unstable, for example, the threshold voltage of the S output transistor fluctuates or is affected by other parasitic elements.

In FIG. 6 (c), since there is a voltage loss of one backflow prevention diode 21, it can be used where voltage loss is allowed, but cannot be used for other applications. Next, as shown in FIGS. 6D and 6E, the P-channel MOS output transistors 100 and 101 are connected in series in the opposite direction, or the P-channel MOS output transistors 100 and 102 are connected in series in the opposite direction. The case will be described. First, FIG. 6D essentially shows FIG.
It is close to the structure of (a) and tends to be unstable in characteristics and operation. 6E is similar to the structure of FIG. 6C in terms of the orientation of the parasitic diodes 19 and 33, but is different from FIG. Since the output transistors 100 and 102 are respectively connected in parallel, if the voltage of the gate 29 is sufficiently low, the P-channel MOS output transistors 100 and 102
Is turned on, no voltage loss occurs. Since the back gates 11 and 30 are connected to the power supply terminal 1 and the constant voltage output terminal 5, respectively, the characteristics and operation are stable.
As described above, regarding the first current reverse mode,
It is possible to avoid the problem by devising a circuit.

Next, the second current reverse mode will be described. This mode is a case where the P-channel MOS output transistor itself conducts due to the original operation of the P-channel MOS output transistor, that is, a decrease in the gate potential. In the example of FIG. 6, the potential of the gate 10 or 28, 35 is reduced, and each of the P-channel MOS output transistors 100, 101, 102 is conducting. It is considered that such a case appears when the power supply voltage of the power supply terminal 1 decreases and the power supply voltage of the circuit also decreases in FIG. Can be In this case, the P-channel MOS output transistor 10 in the large current output stage
Since the sizes of 0, 101, and 102 are large and the on-resistance is small, the backflow current is also large.

In a portable device, there is a case where a process of saving the setting information of the microcomputer at the moment when the power supply is momentarily interrupted or the battery is removed is performed. In such a case, the reverse flow of the current becomes a serious problem. Therefore, a backflow prevention means for preventing the gate potential from being lowered is separately required, but it is difficult to realize the circuit using the external power supply 2 because its own power supply is lowered.

Accordingly, a first object of the present invention is to provide an output stage circuit capable of preventing both a reverse current of a current flowing through a parasitic diode and a reverse current of a current due to conduction of a MOS output transistor itself. A second object of the present invention is to provide an output stage circuit which can easily prevent the reverse current of the current flowing through the parasitic diode and the reverse current caused by the conduction of the MOS output transistor itself.

A third object of the present invention is to provide an output stage circuit capable of preventing a reverse current of a current flowing through a parasitic diode and a reverse current caused by conduction of a MOS output transistor itself with a simple circuit configuration. It is to be.
A fourth object of the present invention is to quickly detect a decrease in the external power supply voltage even when the decrease in the external power supply voltage is gradual, and to detect the reverse current of the current flowing through the parasitic diode and the reverse current of the current due to the conduction of the MOS output transistor itself. Is to provide an output stage circuit capable of promptly preventing the output stage.

[0023]

According to a first aspect of the present invention, there is provided an output stage circuit comprising: a MOS output transistor; a current cutoff switch inserted between the MOS output transistor and a power supply terminal to which an external power supply voltage is applied; And a power supply voltage monitoring circuit for monitoring the external power supply voltage applied to the power supply and forcibly shutting off the current cutoff switch when the value falls below a predetermined value.

According to this configuration, the external power supply voltage is monitored by the power supply voltage monitoring circuit, and when the external power supply voltage falls below a predetermined value, the current cutoff switch is forcibly shut off. As a result, when the external power supply voltage falls below a predetermined value, the path of the reverse current through the MOS output transistor itself or its parasitic diode is opened. As described above, since the current cutoff switch and the power supply voltage monitoring circuit are provided and the current cutoff switch is opened when the external power supply voltage falls below a predetermined value, even if the external power supply voltage falls below the voltage of the output terminal, the MOS output It is possible to prevent the backflow of the current due to the conduction of the transistor itself and the backflow of the current passing through the parasitic diode.

Moreover, in order to prevent a reverse current, a MOS
Since it is only necessary to insert a current cutoff switch between the output transistor and the power supply terminal and to provide a power supply voltage monitoring circuit that monitors the external power supply voltage and forcibly cuts off the current cutoff switch when the external power supply voltage drops, the MOS output transistor It is possible to easily prevent the backflow of the current due to the conduction of itself and the backflow of the current passing through the parasitic diode.

According to a second aspect of the present invention, in the output stage circuit of the first aspect, the current cutoff switch comprises a MOS switch transistor having a back gate connected to the drain, and the power supply voltage monitoring circuit is connected to the MOS output transistor. An inverter using the output terminal voltage as a power supply voltage and an external power supply voltage as an input voltage, and outputting the output voltage of the inverter to the gate of the MOS switch transistor.

According to this configuration, the external power supply voltage is input to the inverter, and when the external power supply voltage falls below the threshold value of the inverter, the output voltage of the inverter is inverted. You. That is,
The external power supply voltage is compared with the threshold voltage of the inverter,
A drop in the external power supply voltage is detected. As described above, since the power supply voltage monitoring circuit is constituted by the inverter, and the inverter is used as a comparator to detect a drop in the external power supply voltage, the reverse current of the MOS output transistor itself and the current flowing through the parasitic diode are used. Can be prevented with a simple circuit configuration.

According to a third aspect of the present invention, in the output stage circuit according to the first aspect, the current cutoff switch comprises a MOS switch transistor having a back gate connected to a drain, and the power supply voltage monitoring circuit has an external power supply voltage and a reference voltage. And a NAND circuit that uses the voltage of the output terminal connected to the MOS output transistor as a power supply voltage, the external power supply voltage as one input voltage, and the output voltage of the comparator as the other input voltage. The output voltage of the NAND circuit is input to the gate of the MOS switch transistor.

According to this configuration, a decrease in the external power supply voltage is detected by comparing the external power supply voltage with an arbitrary reference voltage by the comparator and comparing the external power supply voltage with the threshold value of the NAND circuit. Therefore, by setting the reference voltage higher, it is possible to detect a decrease in the external power supply voltage only by slightly lowering the external power supply voltage without waiting for the external power supply voltage to drop below the threshold value of the NAND circuit. In addition, even when the external power supply voltage is considerably reduced and the operation of the comparator becomes impossible, in this case, the state where the reduction of the external power supply voltage is detected by the operation of the NAND circuit is maintained. Therefore, even when the external power supply voltage has a gradual decrease gradient, the external power supply voltage can be detected quickly, and the current cutoff switch can be opened at an early stage. And the backflow of the current passing through the parasitic diode can be prevented quickly.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram of a constant voltage circuit according to a first embodiment of the present invention. In this constant voltage circuit, as shown in FIG. 1, a current cutoff switch 36 is inserted between a source 12 of a P-channel MOS output transistor 100 and a power supply terminal 1 to which a voltage of an external power supply 2 is applied. 37 is provided to monitor the voltage of the external power supply 2 applied to the power supply terminal 1 and forcibly cut off the current cutoff switch 36 when the voltage drops below a predetermined value. 4 is the same as the constant voltage circuit.

In this constant voltage circuit, the voltage of the external power supply 2 is monitored by the power supply voltage monitoring circuit 37, and when the value falls below a predetermined value, the current cutoff switch 36 is forcibly cut off. As a result, when the voltage of the external power supply 2 falls below a predetermined value, the power supply voltage monitoring circuit 37 operates to open the path of the reverse current through the P-channel MOS output transistor 100 itself or its parasitic diode. Operations other than the above are the same as those of the constant voltage circuit of FIG.

According to the constant voltage circuit of this embodiment, the current cutoff switch 36 and the power supply voltage monitoring circuit 37 are provided, and the current cutoff switch 36 is opened when the voltage of the external power supply 2 falls below a predetermined value. Even if the voltage of the external power supply 2 falls below the voltage of the output terminal 5, it is possible to prevent the reverse current of the current due to the conduction of the P-channel MOS output transistor 100 itself and the reverse current of the current passing through the parasitic diode.
Even if the voltage of the gate of the channel MOS output transistor 100 decreases, backflow can be prevented without any problem.

In addition, a current cutoff switch 36 is inserted between the P-channel MOS output transistor 100 and the power supply terminal 1 to prevent a reverse current, and the voltage of the external power supply 2 is monitored to reduce the voltage of the external power supply 2. It is only necessary to provide a power supply voltage monitoring circuit 37 that forcibly shuts off the current cutoff switch 36 at times, so that it is possible to easily prevent the reverse current of the current due to the conduction of the P-channel MOS output transistor 100 itself and the reverse current of the current passing through the parasitic diode. Can be.

[Second Embodiment: Corresponding to Claim 2] FIG. 2 is a circuit diagram of a constant voltage circuit according to a second embodiment of the present invention. In this constant voltage circuit, as shown in FIG. 2, the current cutoff switch 36 shown in FIG. 1 is composed of a P-channel MOS switch transistor 111 having a back gate 41 connected to a drain 43, and a power supply voltage monitoring circuit 37 is a CMOS inverter. 38. The CMOS inverter 38 used as the power supply voltage monitoring circuit 37
An external power supply 2 uses the voltage of output terminal 5 connected to the drain of P-channel MOS output transistor 100 as a power supply voltage.
Is used as an input voltage, and the output voltage is input to the gate 40 of the P-channel MOS switch transistor 111. Other configurations are the same as those of the constant voltage circuit of FIG.

Here, the gate 40 of the P-channel MOS switch transistor 111 functioning as a current cutoff switch is driven by a CMOS inverter 38 functioning as a power supply voltage monitoring circuit. The CMOS inverter 38
When the voltage of the external power supply 2 is normal and the input voltage 39 is high, the gate 40 of the P-channel MOS switch transistor 111 is lowered to the ground level to make the P-channel MOS switch transistor 111 sufficiently conductive. Conversely, when the external power supply 2 is cut off, the input voltage 39 to the CMOS inverter 38 also decreases.
Is supplied from the output terminal 5, the gate 40 of the P-channel MOS switch transistor 111
Becomes equal to the voltage of the output terminal 5 and the P-channel M
The OS switch transistor 111 cannot be turned on and is turned off.

Further, the back gate 41 of the P-channel MOS switch transistor 111 is connected to the drain 43 when considered with normal voltage polarity, and has a reverse bias direction when the power supply voltage drops. P-channel MOS from terminal 5 to power supply terminal 1
No current flows back through the output transistor 100,
The charge of the capacitor 6 connected to the output terminal 5 is consumed only by the external load 7 and other leak currents.
Therefore, the voltage drop at the output terminal 5 due to the reverse current can be minimized.

The constant voltage circuit in this embodiment inputs an external power supply voltage to the inverter, and inverts the output voltage of the CMOS inverter 38 when the voltage of the external power supply 2 falls below the threshold value of the CMOS inverter 38. Thus, a decrease in the voltage of the external power supply 2 is detected. That is,
By comparing the external power supply voltage with the threshold voltage of the inverter, a drop in the voltage of the external power supply 2 is detected.

According to the constant voltage circuit of this embodiment, the power supply voltage monitoring circuit is constituted by the CMOS inverter 38,
Since the decrease in the voltage of the external power supply 2 is detected using the MOS inverter 38 as a comparator, the P-channel MOS
It is possible to prevent the backflow of the current due to the conduction of the output transistor 100 itself and the backflow of the current passing through the parasitic diode with a simple circuit configuration. Other effects are the same as those of the first embodiment.

In the CMOS inverter 38,
P channel MOS transistor or N channel MO
The same operation as described above is performed in a configuration in which one of the S transistors is replaced with a resistance element (a configuration of an N-channel inverter or a P-channel inverter). Where P
When the channel transistor is replaced with a resistance element, current consumption increases during normal operation.

When the N-channel MOS transistor is replaced with a resistance element, the voltage at the output terminal 5 is divided by the on-resistance of the P-channel MOS transistor of the inverter and the resistance element during the backflow prevention operation, and the P-channel MOS transistor is turned off. M
Since the voltage is applied to the gate 40 of the OS switch transistor 100, the voltage of the gate 40 of the P-channel MOS switch transistor 100 does not rise sufficiently during the backflow prevention operation unless the resistance of the resistance element is set to a considerably large value. Since a part of the charging current of the stray capacitance is consumed by the resistor, there is a possibility that a time delay until the current interruption operation occurs.

In consideration of the above, the CMOS inverter 38 differs from the normal structure in that the ON resistance is reduced by increasing the W / L of the P-channel MOS transistor and the W / L of the N-channel MOS transistor is reduced. By increasing the on-resistance, it is desirable to increase the threshold value (voltage at which the output of the inverter is inverted) that operates as the inverter, and to quickly charge the gate 40 when the backflow is interrupted. That is, the P-channel MO of the inverter
By making the S transistor stronger than the N-channel MOS transistor, the output is likely to be at a high level even under the condition that the P-channel MOS transistor and the N-channel MOS transistor are simultaneously turned on.
This hasten the output cutoff.

Although the input voltage 39 to the CMOS inverter 38 is directly connected to the power supply terminal 1, it is usually connected via a protection resistor or the like. Further, the connection point to the CMOS inverter 38 is not limited to the power supply terminal 1, and other than that, when the voltage of the external power supply 2 decreases, the input voltage 39 of the CMOS inverter 38 decreases sufficiently and quickly. If it is a part, it can be connected.

[Third Embodiment: Corresponding to Claim 3] FIG. 3 is a circuit diagram of a constant voltage circuit according to a third embodiment of the present invention. This constant voltage circuit can solve the problem remaining in the constant voltage circuit of the second embodiment. The second embodiment is a circuit that is effective when the power supply is momentarily interrupted and instantaneously reaches the ground voltage level. However, when the voltage of the external power supply 2 gradually decreases to some extent, it takes time for the voltage of the external power supply 2 to reach the threshold value of the CMOS inverter 38, during which time the reverse current cannot be cut off and the output terminal 5 And the voltage of the output terminal 5 cannot be suppressed.

FIG. 3 shows a third embodiment of the present invention in which the operation when the voltage of the external power supply 2 gradually decreases is improved. The constant voltage circuit according to the third embodiment replaces the CMOS inverter 38 for blocking reverse current shown in FIG. 2 with a NAND circuit 44, and compares a voltage of the external power supply 2 with an arbitrary reference voltage 46. And the voltage of the power supply terminal 1 is applied as one input to the NAND circuit 44, and the output voltage of the comparator 45 is applied as the other input.

That is, in this embodiment, the power supply voltage monitoring circuit compares the voltage of the external power supply 2 with the reference voltage 46 and the P-channel MOS output transistor 1
00, a voltage of the output terminal 5 connected to the power supply voltage, a voltage of the external power supply 2 as one input voltage, and an output voltage of the comparator 45 as the other input voltage. Output voltage to P-channel MO
The input is made to the gate of the S switch transistor 111.

As the reference voltage 46 of the comparator 45,
A value is set in advance to what extent the voltage of the external power supply 2 drops to cut off the output from the P-channel MOS output transistor 100 to the output terminal 5. For example, in a constant voltage circuit that outputs 3 V at output terminal 5, external power supply 2
If the reference voltage 46 is set so as to cut off the voltage when the voltage of the external power supply 2 drops below 3 V, the P-channel MOS output transistor 100 is cut off even when the voltage of the external power supply 2 slowly drops.

When the voltage of the external power supply 2 becomes a voltage at which the comparator 45 does not operate, the other input of the NAND circuit 44 (the input directly connected to the power supply terminal 1).
If the threshold value of the NAND circuit 44 is set so as to be effective, the reverse flow of the current from the output terminal 5 to the power supply terminal 1 through the P-channel MOS output transistor 100 is applied to the gate 40 of the P-channel MOS switch transistor 111.
Can be suppressed to the minimum value of only the charge time delay.

According to the constant voltage circuit of this embodiment, the comparator 45 compares the voltage of the external power supply 2 with an arbitrary reference voltage and compares the voltage of the external power supply 2 with the threshold value of the NAND circuit 44. Since the decrease in the voltage of the external power supply 2 is detected, the reference voltage is set to a higher value, so that the voltage of the external power supply 2 slightly decreases without waiting for the voltage of the external power supply 2 to drop below the threshold of the NAND circuit 44. Only by dropping, it is possible to detect a drop in the voltage of the external power supply 2. In addition, even when the external power supply voltage drops considerably and the operation of the comparator becomes impossible, in this case, the state in which the voltage of the external power supply 2 is detected by the operation of the NAND circuit 44 is maintained. become. Therefore, even when the voltage drop of the external power supply 2 is gentle, the external power supply 2
Of the P-channel MOS output transistor 1 which is a current cutoff switch at an early stage.
00 can be opened, and the backflow of the current due to the conduction of the P-channel MOS output transistor 100 itself and the backflow of the current passing through the parasitic diode can be promptly prevented.

The basic concept of a circuit using an N-channel MOS transistor as an output stage is the same as that of a circuit using a P-channel MOS transistor except for the polarity of voltage. It can be applied to both N-channel MOS transistor output stage circuits. Further, the application of the present invention is not limited to a constant voltage circuit, and the present invention can be applied to all MOS circuits.

[0050]

According to the output stage circuit of the present invention, the current cutoff switch and the power supply voltage monitoring circuit are provided, and the current cutoff switch is opened when the external power supply voltage falls below a predetermined value. Is lower than the voltage of the output terminal, it is possible to prevent the reverse current of the current due to the conduction of the MOS output transistor itself and the reverse current of the current passing through the parasitic diode.

Further, in order to prevent a reverse current, the MO
It is only necessary to insert a current cutoff switch between the S output transistor and the power supply terminal, and to provide a power supply voltage monitoring circuit that monitors the external power supply voltage and forcibly cuts off the current cutoff switch when the external power supply voltage drops. It is possible to easily prevent the backflow of the current due to the conduction of the transistor itself and the backflow of the current passing through the parasitic diode.

According to the output stage circuit of the present invention, the power supply voltage monitoring circuit is constituted by an inverter, and the decrease in the external power supply voltage is detected by using the inverter as a comparator. The prevention of reverse current flow due to conduction and reverse current flow through a parasitic diode can be achieved with a simple circuit configuration. According to the output stage circuit of the third aspect, the comparator compares the external power supply voltage with an arbitrary reference voltage and compares the external power supply voltage with the threshold value of the NAND circuit, thereby detecting a decrease in the external power supply voltage. Therefore, by setting the reference voltage higher, it is possible to detect a drop in the external power supply voltage only by slightly decreasing the external power supply voltage without waiting for the external power supply voltage to drop below the threshold value of the NAND circuit. In addition, even when the external power supply voltage is considerably reduced and the operation of the comparator becomes impossible, in this case, the state where the reduction of the external power supply voltage is detected by the operation of the NAND circuit is maintained. Therefore, even when the decrease gradient of the external power supply voltage is gentle, the decrease of the external power supply voltage can be detected promptly, and the current cutoff switch can be opened at an early stage.
It is possible to quickly prevent the reverse current of the current due to the conduction of the output transistor itself and the reverse current of the current passing through the parasitic diode.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a constant voltage circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a constant voltage circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a constant voltage circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a conventional constant voltage circuit.

FIG. 5 is a schematic diagram showing a configuration of a P-channel MOS transistor.

FIG. 6 is a circuit diagram for explaining a countermeasure against a parasitic diode of a P-channel MOS transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Power supply terminal 2 External power supply 3 Reference voltage terminal 4 Reference voltage source 5 Output terminal 6 External capacitor 7 External load 8 Bias current source 9 Differential amplifier 10 Gate 11 Back gate 12 Source 13 Drain 14 Gate terminal 15 Back gate terminal 16 Source Terminal 17 Drain terminal 18 Parasitic diode 19 Parasitic diode 20 Gate oxide film 21 Backflow prevention diode 22 Gate 23 Back gate 24 Source 25 Drain 26 Parasitic diode 27 Parasitic diode 28 Common gate 29 Gate 30 Back gate 31 Source 32 Drain 33 Parasitic diode 34 Parasitic Diode 35 Common gate 36 Current cutoff switch 37 Power supply voltage monitoring circuit 38 Current cutoff control inverter 39 Input voltage of current cutoff control inverter 40 Gate 41 Bus Kugeto 42 source 43 drain 44 NAND circuit 45 comparator 46 reference voltage 100 P-channel MOS output transistor 101 P-channel MOS output transistor 102 P-channel MOS output transistor

Claims (3)

[Claims] 1. An MOS output transistor, comprising:
A current cutoff switch inserted between an output transistor and a power supply terminal to which an external power supply voltage is applied; and an external power supply voltage applied to the power supply terminal is monitored, and when the value drops below a predetermined value, the current cutoff switch is forcibly activated. An output stage circuit comprising a power supply voltage monitoring circuit that shuts off the power supply. 2. The current cutoff switch comprises a MOS switch transistor having a back gate connected to a drain,
The power supply voltage monitoring circuit includes an inverter having a voltage at an output terminal connected to the MOS output transistor as a power supply voltage and an external power supply voltage as an input voltage, and the output voltage of the inverter is input to the gate of the MOS transistor. The output stage circuit according to claim 1, wherein 3. The current cutoff switch comprises a MOS switch transistor having a back gate connected to a drain,
A power supply voltage monitoring circuit for comparing an external power supply voltage with a reference voltage; a voltage at an output terminal connected to a MOS output transistor as a power supply voltage, the external power supply voltage as one input voltage, and an output voltage of the comparator. 2. The output stage circuit according to claim 1, further comprising a NAND circuit having the other input voltage as an input voltage, and wherein an output voltage of the NAND circuit is input to a gate of the MOS switch transistor.