JP2009059877A - Semiconductor device and semiconductor device system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a leakage current via an ESD protecting element, while protecting against ESD a semiconductor integrated circuit to which the output signal of another semiconductor integrated circuit operating, with a relatively high power-supply voltage and a semiconductor integrated circuit whose sleep state is controlled with an external control signal, in an environment where a plurality of semiconductor integrated circuits operate at a plurality of power-supply voltages. <P>SOLUTION: A semiconductor integrated circuit is provided with an internal circuit 404, a signal input terminal 405 for inputting a signal to the internal circuit 404; an ESD-protecting circuit having a P-channel transistor 409 and an N-channel transistor 410 for ESD protection; and a switch circuit which supplies a power-supply voltage to the back gate of the P-channel transistor 409, when the internal circuit 404 is in operation and connects the signal input terminal 405 to the back gate of the P-channel transistor 409, when the internal circuit 404 is at a halt. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a plurality of semiconductor integrated circuits operating at a plurality of different power supply voltages are mixed, and the power supply voltage is exclusively turned off or the power supply voltage is relatively low in a system composed of semiconductor integrated circuits. Relates to the input circuit.

  In recent years, products that operate on batteries such as mobile phones are required to operate for a long time for each charge, and in order to achieve this, it is effective to reduce the power consumption of the entire product. That is, a method is generally used in which a semiconductor integrated circuit that does not need to operate is stopped and its power consumption is suppressed.

  FIG. 5 shows a circuit block diagram of a conventional semiconductor integrated circuit. The semiconductor integrated circuit 501 is supplied with a power supply voltage Vcc from an external constant voltage output circuit 502, and the constant voltage output circuit 502 uses a battery 503 as a power supply voltage. The semiconductor integrated circuit 501 includes a control signal input terminal 504 as an I / O terminal, and a control signal input that puts the internal circuit 505 into a sleep state (generally, the current source is turned off and stopped) in order to suppress current consumption. A terminal 506 is provided. A control signal 507 is input to the constant voltage output circuit 502. A switch circuit 508 that is turned ON / OFF by a control signal 507 is connected to the constant voltage output circuit 502. When the switch circuit 508 is turned OFF, the constant voltage output circuit 502 enters a sleep state.

  In the semiconductor integrated circuit 501, the control signal from the control signal input terminal 504 is input to the internal circuit 505 through the inverter 509. The inverter 509 converts the level of the control signal from the control signal input terminal 504 to the power supply voltage level of the internal circuit 505 and inputs it to the internal circuit 505. The switch circuit 510 is turned ON / OFF by a control signal from the control signal input terminal 506. When the switch circuit 510 is turned off, the internal circuit 505 enters a sleep state. Further, the semiconductor integrated circuit 501 includes a P-channel transistor 511 and an N-channel transistor 512 as ESD protection elements for protecting the internal circuit 505 from ESD (Electric Static Charge) with respect to the control signal input terminal 504.

  FIG. 6 shows a path through which a surge current flows when a positive surge is input from an I / O terminal to a conventional semiconductor integrated circuit. P-channel transistor 511 is used to protect internal circuit 505 from positive surge current. In the P-channel transistor 511, a drain that is a P-type semiconductor and a back gate that is an N-type semiconductor constitute a parasitic diode 601. If a good conductor charged with a positive charge on the Vcc basis contacts the control signal input terminal 504 that is an I / O terminal, the drain and the back gate are forward biased, and a positive pulse current generated on the basis of the Vcc is generated by the contact. (Surge current) flows through the diode 601 instead of the internal circuit 505 (path 602). In the case of GND reference, the N-channel transistor 512 operates (functions) as the ggNMOS 603 and causes a surge current to flow not to the internal circuit 505 but to GND (path 604).

  FIG. 7 shows a path through which a surge current flows when a negative surge is input from an I / O terminal to a conventional semiconductor integrated circuit. N-channel transistor 512 is used to protect internal circuit 505 from negative surge currents. In the N-channel transistor 512, a drain that is an N-type semiconductor and a back gate that is a P-type semiconductor constitute a parasitic diode 701. If a good conductor charged with a negative charge with respect to the GND is in contact with the control signal input terminal 504, the drain and the back gate are forward-biased, and the negative surge current based on the GND with respect to the contact is not the internal circuit 505. , And flows through the diode 701 (path 702). In the case of GND reference, the P-channel transistor 511 operates as the ggPMOS 703 and prevents surge current from flowing through the internal circuit 505 (path 704).

  As described above, an ESD element is required to protect the internal circuit 505 from a surge, but a leakage current may flow through the ESD element. Here, a mobile phone is considered as a device in which a semiconductor integrated circuit is incorporated. In the mobile phone, a control signal to the control signal input terminals 504 and 506 and a control signal 507 to the constant voltage output circuit are output from the microcomputer that controls the operation. The control signal output from the microcomputer is an H / L signal, and its level is substantially equal to the power supply voltage or GND of the microcomputer that outputs the control signal.

  In such an operating environment, the internal circuit 505 stops operating by a control signal to the control signal input terminal 506, and the constant voltage output circuit 502 is set in the sleep state, and the power supply voltage of the semiconductor integrated circuit 501 is turned off. In such a case, there is a possibility that a leak current is generated through the ESD protection element. In this case, when a control signal having substantially the same level as the power supply voltage of the microcomputer is input to the control signal input terminal 504 of the semiconductor integrated circuit 501, the parasitic diode 601 of the P-channel transistor 511 is likely to be forward biased.

  Even when the internal circuit of the semiconductor integrated circuit 501 is in operation, the power supply voltage of the semiconductor integrated circuit 501 is suppressed to, for example, 2.8 V, and another type of microcomputer such as a microcomputer that outputs a control signal to the semiconductor integrated circuit 501 Even when the power supply voltage of the semiconductor integrated circuit is 5 V, which is higher than that, leakage current through the P-channel transistor 511 may occur. This is because when the power supply voltage of another semiconductor integrated circuit is high, the control signal input terminal 504 is the same as contacting a good conductor charged with a positive charge on the basis of Vcc. In this case, a leak current flows through the parasitic diode 601 as in the case of a positive surge current with respect to Vcc.

  FIG. 8 is a diagram for explaining a region where a leak current is generated through the ESD protection element by the control signal. The horizontal axis is time, and the vertical axis is voltage. In this example, the battery voltage is constant regardless of time, and when the control signal of the control signal input terminal 506 and the control signal 507 are turned on at a certain time T1, the output of the constant voltage output circuit 502 is externally output. Stand up while charging the attached capacity. After the constant voltage output rises, when the control signal at the control signal input terminal 504 rises at time T2 and rises until the parasitic diode 601 becomes forward biased (a voltage about 0.7V higher than the constant voltage output), as described above. The parasitic diode 601 is turned on and a leak current is generated.

  If the control signal at the control signal input terminal 506 and the control signal 507 are turned off at the subsequent time T3, the output of the constant voltage output circuit 502 is directed to GND while discharging the charge accumulated in the external capacitor. And then eventually become the same potential as GND. When the control signal at the control signal input terminal 504 rises at time T4 during the sleep state and rises until the parasitic diode 601 becomes forward biased, the diode 601 is also turned on and leak current is generated. . Thus, the current in the shaded area in the figure flows through the diode 601 and may cause problems such as increased power consumption.

As a method for solving this problem, for example, there are techniques described in Patent Document 1 and Patent Document 2. The output buffer circuit described in Patent Document 1 includes a first P-channel transistor connected to a power supply, and a second P-channel transistor whose gate and back gate are connected to an input pad. When the L level is output to the pad, the gate, source, and back gate of the second P-channel transistor are at the same potential no matter what voltage is applied to the pad. Turns off. For this reason, in this output buffer circuit, it is possible to prevent the occurrence of leakage current and to output a voltage at a high speed up to the applied voltage. The multi-power supply protection circuit described in Patent Document 2 monitors the state of the power supplied to the multi-power supply protection element, and passes the path of the multi-power supply protection element until the high-potential power supply reaches a normal voltage value. This prevents the leakage current from flowing.
JP 2000-151383 A JP 2000-243842 A

  The output buffer circuit described in Patent Document 1 prevents the occurrence of leakage current when a voltage higher than its own power supply voltage is applied to a common bus. However, when there is an external input to the power-off circuit, there is a problem that a leak current is generated through the parasitic element. In the multi-power supply protection circuit described in Patent Document 2, the path to the protection element is cut until the high-potential power supply reaches a normal voltage value, which may cause destruction of the internal circuit due to ESD. There was a problem.

  The present invention reduces leakage current through an ESD protection element while performing ESD protection even when a signal is applied from the other power supply voltage when the power supply voltage of the self power supply is OFF, and when the power supply voltage of the self power supply is lower than the other power supply voltage. An object of the present invention is to provide a semiconductor device and a semiconductor device system that can be prevented.

  FIG. 1 shows the principle of leakage current prevention ESD protection according to the present invention. The semiconductor device of the present invention includes an internal circuit 1, a signal input terminal 2 for inputting a signal to the internal circuit 1, a P-channel transistor 3 and an N-channel transistor for protecting the internal circuit 1 from electrostatic discharge. 4 is connected to the signal input terminal 2, an ESD protection circuit having a power supply terminal connected to the source of the P-channel transistor 3, and a signal input terminal 5 to which a signal for operating or stopping the internal circuit 1 is input. Depending on the potential state of signal input terminals 2 and 5, switch circuit 6 for connecting the back gate of P channel transistor 2 to either signal input terminal 2 or the power supply terminal is provided. In this semiconductor device, even when the input signal voltage from the outside is higher than its own power supply voltage or when the input signal voltage is given from another semiconductor device driven by a voltage higher than its own power supply voltage, the signal input Leakage current through the ESD protection element is prevented while performing ESD protection by determining the connection of the switch circuit 6 according to the potential state of the terminals 2 and 5.

  For example, when a control signal for turning off the switch circuit 7 and stopping the internal circuit 1 is input to the signal input terminal 5, the switch circuit 6 connects the signal input terminal 2 to the gate and back gate of the P-channel transistor 3. . For this reason, the gate and back gate of the P-channel transistor 3 are at the same potential as the signal input terminal 2, and even if a signal is input to the signal input terminal 2 when the power supply voltage of the internal circuit 1 is OFF, the P-channel transistor 3 Since the parasitic diode is not forward biased, leakage current can be prevented. When a control signal for operating the internal circuit 1 is input to the signal input terminal 5 and the power supply voltage of the internal circuit 1 is ON, the switch circuit 6 includes the power supply terminal, the gate of the P-channel transistor 3 and the back gate. Connect.

  FIG. 2 shows a current path when a positive surge based on Vcc and GND is applied to the signal input terminal 2 when the switch circuit 6 connects the signal input terminal 2 and the gate and back gate of the P-channel transistor 3. Show. In the case of a positive surge on the basis of Vcc, the signal input terminal 2 side of the P-channel transistor 3 becomes high voltage, and the P-channel transistor 3 plays a role as the ggPMOS 201 (path 202) and protects the internal circuit 1 from ESD. In addition, when the GND standard is used, the N-channel transistor 4 operates as the ggNMOS 203 (path 204), and the internal circuit 1 is protected from ESD.

  FIG. 3 shows a current path when a negative surge based on Vcc and GND is applied to the signal input terminal 2 when the switch circuit 6 connects the signal input terminal 2 and the gate and back gate of the P-channel transistor 3. . In the case of GND reference, a current flows (path 302) through a parasitic diode 301 composed of an N-type semiconductor drain of the N-channel transistor 4 and a P-type semiconductor back gate, and in the case of Vcc reference, the P-channel transistor 3 A current flows through a parasitic diode 303 composed of a P-type semiconductor drain and an N-type semiconductor back gate (path 304) to protect the internal circuit 1 from ESD.

  By adopting the above configuration, the present invention enables the self-power supply from another semiconductor integrated circuit that controls the system even when the power supply voltage of the semiconductor integrated circuit is turned off or even when the power supply voltage is turned on. Even when a signal having a voltage higher than the voltage is input, a leakage current flowing through the ESD protection element can be prevented. Therefore, even when a plurality of semiconductor integrated circuits that operate with a plurality of power supply voltages are mixed or there are semiconductor integrated circuits that are in a sleep state and turned off in a plurality of semiconductor integrated circuits, the control is special. There is no need for special consideration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The semiconductor integrated circuit in this embodiment forms one system together with other semiconductor integrated circuits having different power supply voltages, and a signal input terminal of the semiconductor integrated circuit has a power supply voltage higher than that of the semiconductor integrated circuit. An output signal of another semiconductor device driven by a high power supply voltage is input. In that case, the signal voltage input from the signal input terminal is generally higher than the power supply voltage of the semiconductor integrated circuit including the signal input terminal.

  FIG. 4 is a circuit diagram showing a circuit configuration of the semiconductor integrated circuit according to the present embodiment. The semiconductor integrated circuit 401 in this embodiment is supplied with power supply voltage Vcc and GND terminals 402 and 403 supplied from an external constant voltage circuit, an internal circuit 404 that operates according to the voltage, and an external control signal. Control signal input terminals 405 and 406, an inverter 407 for converting the level of the signal from the control signal input terminal 405 to the power supply voltage of the internal circuit 404, and the internal circuit 404 is turned ON / OFF by the signal from the control signal input terminal 406. A switch circuit 408 that operates or stops, and a P-channel transistor 409 and an N-channel transistor 410 as ESD protection elements for the control signal input terminal 405 are provided.

  The semiconductor integrated circuit 401 further includes P-channel transistors 411 and 412, and the P-channel transistors 411 and 412 serve as the gate and back gate of the P-channel transistor 409, respectively, for the power supply voltage terminal 402 and the control signal input terminal 405. Connect to either one. FIG. 1 is a diagram schematically showing a characteristic configuration of the configuration shown in FIG. 4 of the semiconductor integrated circuit according to the present embodiment. In this embodiment, P-channel transistors 411 and 412 correspond to the switch circuit 6 of FIG. When the gate and back gate of the P channel transistor 409 of the ESD protection element are connected to Vcc, the P channel transistor 411 is turned on, the P channel transistor 412 is turned off, and the gate and back gate of the P channel transistor 409 are connected to the control signal input terminal 405. , The P channel transistor 411 is turned OFF and the P channel transistor 412 is turned ON.

  In the semiconductor integrated circuit 401 shown in FIG. 4, the signal input to the control signal input terminal 406 is active low. When an “L” level signal is input to the control signal input terminal 406, the switch circuit 408 is turned on and the internal circuit 404 is in an operating state. The control signal input terminal 406 is connected to the gate of the P-channel transistor 411. When the internal circuit 404 is in an operating state, the P-channel transistor 411 is turned on. The source and back gate of the P channel transistor 411 are connected to the power supply voltage, and the drain is connected to the gate and back gate of the P channel transistor 409. By turning on the P-channel transistor 411, the gate and back gate of the P-channel transistor 409 can be set to substantially the same potential as Vcc.

  The control signal input terminal 406 is also connected to the gate of a P-channel transistor 413. The source and back gate of the P channel transistor 413 are connected to the power supply voltage, and the drain thereof is connected to the gate of the P channel transistor 412. When an “L” level signal is input to the control signal input terminal 406, the P-channel transistor 413 is turned on, and the gate potential of the P-channel transistor 412 becomes approximately Vcc. Become.

  In this way, when an “L” level signal is input to the control signal input terminal 406 and the internal circuit 404 is in an operating state, the gate and back gate of the P-channel transistor 409 as an ESD protection element have substantially the same potential as Vcc. Become. In this state, when a voltage signal higher than the power supply voltage Vcc is input to the control signal input terminal 405 and a parasitic diode composed of the P-type semiconductor drain and the N-type semiconductor back gate of the P-channel transistor 409 becomes forward biased. A leakage current through the parasitic diode is generated. In order to prevent the leakage current, the semiconductor integrated circuit 401 includes a comparator circuit 414.

  The comparator circuit 414 outputs a signal based on the signal voltage input to the control signal input terminal 405 and the reference voltage. The input on the signal voltage side of the comparator circuit 414 is connected to the middle point of the resistors 415 and 416. The signal voltage is divided by resistors 415 and 416 and input to the comparator circuit 414. An input on the reference voltage side of the comparator circuit 414 is connected to Vcc through a resistor 417 and is connected to GND through a resistor 418. A voltage obtained by dividing Vcc by the resistors 417 and 418 is input to the reference voltage side of the comparator circuit 414.

  The switch circuits 419 and 420 are turned ON / OFF by the signal from the comparator circuit 414, respectively. When the switch circuit 419 is turned on, the resistor 421 is connected in parallel with the resistor 416, and the signal voltage input to the control signal input terminal 405 is divided by the resistor 415 and the parallel resistors 416 and 421. The signal voltage is stepped down and input to the inverter 407 by the divided voltage. When the switch circuit 420 is turned on, the resistor 422 is connected in parallel with the resistor 418, and Vcc is divided by the resistor 417 and the parallel resistors 418 and 422. That is, when the resistor 421 is connected to the input on the signal voltage side of the comparator circuit 414, the resistor 422 is connected to the input on the reference voltage side correspondingly, and the voltage dividing ratio is adjusted for any input.

  The switch circuit 408 that operates or stops the internal circuit 404 is also connected to the comparator circuit 414 and the resistors 416, 418, and 422. When the internal circuit 404 is operating, the comparator circuit 414 is also operating, and the resistors 416 and 418 are connected to GND. The resistor 422 is connected to GND when the switch circuit 420 is turned on in that state.

  When a voltage higher than Vcc is input to the control signal input terminal 405 while the internal circuit 404 is operating, a voltage close to this is input to the comparator circuit 414, and the switch circuit 419 is activated by the output of the comparator circuit 414. Turn on. In this case, the voltage input to the control signal input terminal 405 is stepped down by the resistor 415 and the parallel resistors 416 and 421. As a result, the input of the inverter 407 and the drain of the P-channel transistor 409 are both about Vcc, and the parasitic diode composed of the drain and back gate of the P-channel transistor 409 is not forward biased. For this reason, even if a voltage higher than Vcc is input to the control signal input terminal 405 while the internal circuit 404 is in operation, leakage current through the parasitic diode is prevented.

  In addition, when an “H” level signal is input to the control signal input terminal 406 and the internal circuit 404 and the comparator circuit 414 are stopped, the occurrence of leakage current through the P-channel transistor 409 causes the gate of the P-channel transistor 409 and This is prevented by connecting the back gate to the control signal input terminal 405. When the “H” level signal is input to the control signal input terminal 406, the gate potentials of the P channel transistors 411 and 413 are set to the “H” level, so that the P channel transistors 411 and 413 are turned off. In this state, when an “H” level signal is input to the control signal input terminal 405, the N-channel transistor 423 is turned ON. The gate of the N-channel transistor 423 is connected to the control signal input terminal 405, and the source and back gate are connected to GND. Further, the drain of the N-channel transistor 423 is connected to the gate of the P-channel transistor 412 through the resistor 424 and to the control signal input terminal 406 through the resistors 424 and 425. When the N-channel transistor 423 is turned on, a current flows from the control signal input terminal 406 through the resistors 425 and 424, and the gate potential of the P-channel transistor 412 becomes “L” level. As a result, the P-channel transistor 412 is turned ON, and the gate and back gate of the P-channel transistor 409 are connected to the control signal input terminal 405. Since the gate and back gate of the P-channel transistor 409 have substantially the same potential as the signal input to the control signal input terminal 405, the parasitic diode composed of the drain and back gate of the P-channel transistor 409 is not forward biased. For this reason, even when an “H” level signal is input from the control signal input terminal 405 while the internal circuit 404 is stopped, the occurrence of a leakage current is prevented.

  As described above, in the semiconductor integrated circuit in this embodiment, even when a signal larger than the power supply voltage is input from the outside while the internal circuit is operating, or even when a signal is input from the outside while the internal circuit is stopped, Generation of leakage current through the protective element can be prevented. When a surge current is input from the control signal input terminal 405, the P channel transistor 409 and the N channel transistor 410, which are ESD protection elements, protect the internal circuit 404.

  When a positive potential is applied to the control signal input terminal 405 with reference to Vcc by a surge current, the N-channel transistor 423 is turned on, and thereby the P-channel transistor 412 is turned on. In this state, the P-channel transistor 409 functions as a ggPMOS. If the positive potential given on the basis of Vcc is as large as the forward bias of the diode, the flowing current is negligible, but in general, the positive potential is sufficiently larger than the forward bias of the diode and the avalanche breakdown When the voltage is exceeded, a surge current flows through the ggPMOS, thereby protecting the internal circuit 404. When a positive potential is applied to the control signal input terminal 405 by the surge current on the basis of GND, the N-channel transistor 410 functions as ggNMOS, and the surge current flows through the ggNMOS, thereby protecting the internal circuit 404.

  When a negative potential is applied to the control signal input terminal 405 with reference to Vcc by a surge current, a surge current flows through two parasitic diodes connected in series, and the internal circuit 404 is protected. One of the parasitic diodes is composed of a P-type semiconductor drain of the P-channel transistor 412 and an N-type semiconductor back gate, and the other one of the parasitic diodes is a P-type semiconductor drain of the P-channel transistor 409 and an N-type semiconductor. Type semiconductor back gate. Further, when a negative potential is applied to the control signal input terminal 405 with respect to GND due to the surge current, the surge current flows through a parasitic diode composed of the N-type semiconductor drain and the P-type semiconductor back gate of the N-channel transistor 410. The internal circuit 404 is protected.

  As described above, in the semiconductor integrated circuit in this embodiment, even when a signal higher than its own power supply voltage is input from another semiconductor integrated circuit constituting the system, the internal circuit is protected by the ESD protection element. The leakage current can be prevented from being generated through the ESD protection element.

  The embodiments described above do not limit the technical scope of the present invention, and various modifications and applications other than those already described are possible within the scope of the present invention.

  The present invention relates to a semiconductor integrated circuit that operates with a power supply voltage relatively lower than a signal for controlling the semiconductor integrated circuit in a system in which a plurality of semiconductor integrated circuits that operate with a plurality of power supply voltages coexist, or a plurality of semiconductor integrated circuits In order to reduce the power consumption of a system composed of circuits as a whole system, the present invention is useful for a semiconductor integrated circuit in which a power supply voltage is turned off when not operating as necessary.

The figure which shows the principle of the leakage current prevention ESD protection by this invention Diagram showing positive surge current path with respect to GND and Vcc Diagram showing negative surge current path based on GND and Vcc 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit in an embodiment of the present invention. The figure which shows an example of a structure of the conventional semiconductor integrated circuit The figure which shows the positive surge current path on the basis of GND and Vcc in the conventional semiconductor integrated circuit The figure which shows the negative surge current path on the basis of GND and Vcc in the conventional semiconductor integrated circuit The figure explaining the leak operation in the conventional semiconductor integrated circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Internal circuit 2 Control signal input terminal 3 ESD protection P channel transistor 4 ESD protection N channel transistor 5 Control signal input terminal 6 Switch circuit 7 Switch circuit 401 Semiconductor integrated circuit 404 Internal circuit 405 Control signal input terminal 406 Control signal input terminal 408 Switch circuit 409 ESD protection P-channel transistor 410 ESD protection N-channel transistor 411, 412 Switch circuit P-channel transistor 414 Comparator circuits 415, 416 Signal voltage side voltage dividing resistor 417, 418 Power source voltage side voltage dividing resistor 419, 420 Switch circuit 421, 422 Adjustment resistor

Claims (8)

Internal circuitry,
A first signal input terminal for inputting a signal from the outside to the internal circuit;
An ESD protection P-channel transistor having a drain / source connected between the first signal input terminal and a power supply terminal, and an ESD protection N-channel transistor having a drain connected to the first signal input terminal An ESD protection circuit comprising:
The power supply terminal is connected to the back gate of the ESD protection P-channel transistor when the internal circuit is operating, and the first signal is connected to the back gate of the ESD protection P-channel transistor when the internal circuit is stopped. A semiconductor device comprising: a first switch circuit for connecting an input terminal.   A comparator circuit that outputs a signal based on the input signal voltage input to the first signal input terminal and a reference voltage, and the ESD protection P-channel transistor and the ESD by the signal output from the comparator circuit 2. The semiconductor device according to claim 1, further comprising a circuit that steps down an input signal voltage at a connection point with the protective N-channel transistor. A second signal input terminal to which a signal for operating or stopping the internal circuit is input;
The first switch circuit is configured to detect the ESD protection P-channel transistor based on input signal voltages input to the first signal input terminal and the second signal input terminal while the internal circuit is stopped. The semiconductor device according to claim 1, wherein the first signal input terminal is connected to a back gate.   A first P-channel transistor having a source and a back gate connected to the power supply terminal and a drain connected to a gate and a back gate of the ESD protection P-channel transistor; A second P-channel transistor having a source and a back gate connected to a signal input terminal, and a drain connected to a gate and a back gate of the ESD protection P-channel transistor; the first signal input terminal and the second 4. The semiconductor device according to claim 3, further comprising a circuit for turning on and off the first P-channel transistor and the second P-channel transistor based on an input signal voltage inputted to a signal input terminal. . A first voltage dividing resistor circuit that divides an input signal voltage input to the first signal input terminal;
A second voltage dividing resistor circuit that divides a power supply voltage applied through the power supply terminal;
A comparator circuit that receives a midpoint voltage of each of the first voltage dividing resistor circuit and the second voltage dividing resistor circuit;
A second switch circuit that is turned ON / OFF by the output of the comparator circuit;
When the second switch circuit is turned on, the first voltage dividing resistor circuit and the second voltage dividing resistor circuit are connected in parallel to the ground voltage dividing resistors of the first voltage dividing resistor circuit and the second voltage dividing resistor circuit, respectively. The semiconductor device according to claim 1, further comprising: an adjustment resistor that adjusts a voltage dividing ratio of each of the circuit and the second voltage dividing resistor circuit.   The semiconductor device according to claim 1, wherein an input signal voltage input to the first signal input terminal is higher than a power supply voltage supplied via the power supply terminal.   6. The semiconductor device according to claim 1, and another semiconductor device that inputs a voltage higher than a power supply voltage supplied from the first signal input terminal to the semiconductor device via the power supply terminal; A semiconductor device system comprising:   6. The semiconductor device according to claim 1, and another semiconductor device driven by a power supply voltage higher than that of the semiconductor device, wherein a signal is input to the semiconductor device from the first signal input terminal. A semiconductor device system comprising:

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