JP2020170768A - Semiconductor device - Google Patents

Abstract

To prevent malfunctions due to parasitic elements.SOLUTION: A semiconductor device 41 comprises: an external terminal T1; a first semiconductor region (e.g., a cathode of a Zener diode D1) connected to the external terminal T1; a second semiconductor region (e.g., a drain of a transistor M2) constituting an internal circuit; a third semiconductor region (e.g., a collector of a transistor Q2) formed closer to the first semiconductor region compared with the second semiconductor region; and a current supply circuit CS configured to supply current to the external terminal T1 when a parasitic element Q3 (e.g., an npn-type transistor based on a p-type semiconductor substrate, using an n-type first semiconductor region as an emitter, and using an n-type third semiconductor region as a collector) accompanied between the first semiconductor region and the third semiconductor region turns on.SELECTED DRAWING: Figure 4

Description

The inventions disclosed herein relate to semiconductor devices.

Conventionally, during the operation of a semiconductor device, a negative voltage may be generated at an external terminal of the semiconductor device due to a current applied from the outside of the device or an inductance component such as a coil or wiring.

As an example of the prior art related to the above, Patent Document 1 can be mentioned.

JP 2015-29251

When a negative voltage is generated at the external terminal of the semiconductor device, the parasitic element inside the device may operate. This parasitic element is an element that is not incorporated in the original circuit operation. Therefore, it causes an unexpected malfunction different from the original circuit operation, which may lead to a malfunction or destruction of the set on which the semiconductor device is mounted.

It is difficult to predict where the parasitic element will be formed inside the device, and even if the chip layout and circuits are devised, it is not easy to eliminate the formation of the parasitic element itself.

The invention disclosed in the present specification is an object of the present invention to provide a semiconductor device capable of preventing malfunction due to a parasitic element in view of the above-mentioned problems found by the inventors of the present application.

For example, the semiconductor device disclosed in the present specification is more than an external terminal, a first semiconductor region connected to the external terminal, a second semiconductor region forming an internal circuit, and the second semiconductor region. When the third semiconductor region formed near the first semiconductor region and the parasitic element associated between the first semiconductor region and the third semiconductor region are turned on, a current is supplied to the external terminal. It has a configuration (first configuration) including a current supply circuit.

In the semiconductor device having the first configuration, the parasitic element is based on a P-type semiconductor substrate, has an N-type first semiconductor region as an emitter, and has an N-type third semiconductor region as a collector. It is preferable to have a configuration (second configuration) in which the npn type transistor is used.

Further, in the semiconductor device having the first or second configuration, the current supply circuit includes a first switch element that short-circuits between the external terminal and the reference potential end when the parasitic element is turned on. It is preferable to use a configuration (third configuration).

Further, in the semiconductor device having the third configuration, the first switch element is an N-channel transistor in which the drain is connected to the external terminal and the source is connected to the reference potential end (fourth). Configuration) is recommended.

Further, in the semiconductor device having the fourth configuration, the current supply circuit further includes a second switch element that short-circuits between the power supply end and the gate of the first switch element when the parasitic element is turned on. It is preferable to use the configuration (fifth configuration).

Further, in the semiconductor device having the fifth configuration, in the second switch element, the source is connected to the power supply end, the drain is connected to the gate of the first switch element, and the gate is in the third semiconductor region. The configuration (sixth configuration) may be a connected P-channel transistor.

Further, in the semiconductor device having the sixth configuration, the current supply circuit is connected between the first resistor connected between the gate and source of the first switch element and the gate and source of the second switch element. It is preferable to have a configuration (seventh configuration) further including the second resistor.

Further, the semiconductor device having any of the first to seventh configurations may be configured to further include an electrostatic protection element connected between the external terminal and the reference potential end (eighth configuration).

Further, the semiconductor device having any of the first to eighth configurations may be configured to further include an output element connected between the input end of the input voltage and the external terminal (nineth configuration).

Further, the semiconductor device having the ninth configuration further includes an output drive unit that drives the output element so that the output voltage appearing at the external terminal or the feedback voltage corresponding thereto and the predetermined reference voltage match. It is preferable to use the configuration (tenth configuration).

According to the semiconductor device disclosed in the present specification, it is possible to prevent malfunction due to a parasitic element.

The figure which shows the comparative example of the semiconductor device The figure which shows the vertical section of the semiconductor device The figure which shows the behavior when a negative voltage is generated in the comparative example. The figure which shows the 1st Embodiment of a semiconductor device The figure which shows the plane layout and the vertical cross section of a semiconductor device. The figure which shows the behavior when a negative voltage is generated in 1st Embodiment

<Semiconductor device (comparative example)>
First, before explaining a new embodiment of a semiconductor device, a comparative example to be compared with this will be briefly described.

FIG. 1 is a diagram showing a comparative example of a semiconductor device. The semiconductor device 100 of this comparative example is an LDO [low drop out] regulator IC that generates an output voltage VOUT from an input voltage VIN, and includes a P-channel MOS [metal oxide semiconductor] field effect transistor M1 and resistors R1 and R2. It has an operational amplifier AMP, a Zena diode D1, an overcurrent protection circuit OCI, an overheat protection circuit TSD, and an external terminal T1 (= output terminal). Of course, the semiconductor device 100 may have other components.

The source of the transistor M1 is connected to the input end of the input voltage VIN. The drain of the transistor M1 is connected to the external terminal T1 (= the output end of each of the output voltage VOUT and the output current IOUT). The gate of the transistor M1 is connected to the output end (= application end of the gate signal G1) of the operational amplifier AMP. In this way, the transistor M1 is connected between the input end of the input voltage VIN and the output end of the output voltage VOUT, and its on-resistance value (extended) is increased according to the gate signal G1 applied from the operational amplifier AMP. Functions as an output element whose conductivity) is continuously controlled.

The resistors R1 and R2 are connected in series between the output end (= external terminal T1) of the output voltage VOUT and the ground end (= reference potential end), and the output voltage VOUT is divided from the connection nodes between them. It functions as a resistance dividing circuit that outputs a feedback voltage Vfb (= VOUT × {R2 / (R1 + R2)}). When the output voltage VOUT is directly input to the operational amplifier AMP as the feedback voltage Vfb, the resistors R1 and R2 may be omitted.

The operational amplifier AMP has a gate signal of the transistor M1 so that the feedback voltage Vfb input to the non-inverting input end (+) and the predetermined reference voltage Vref input to the inverting input terminal (-) match (imaginary short). It functions as an output drive unit that continuously controls G1.

For example, when Vfb <Vref, the output voltage VOUT (and thus the feedback voltage Vfb) is raised by lowering the gate signal G1 and lowering the on-resistance value of the transistor M1 (= increasing the conductivity of the transistor M1). Can be done. On the contrary, when Vfb> Vref, the output voltage VOUT (and the feedback voltage Vfb) is lowered by raising the gate signal G1 and raising the on-resistance value of the transistor M1 (= lowering the conductivity of the transistor M1). be able to.

In this way, the output voltage VOUT can be adjusted to the target value (= Vref × {(R1 + R2) / R2}) by the output feedback control using the operational amplifier AMP.

The cathode of the Zener diode D1 is connected to the output end (= external terminal T1) of the output voltage VOUT. The anode of the Zener diode D1 is connected to the ground end. The Zener diode D1 functions as an electrostatic protection element for protecting the external terminal T1 from electrostatic discharge (ESD [electro-static discharge]). Therefore, it is desirable that the Zener diode D1 is provided in the vicinity of the external terminal T1.

The overcurrent protection circuit OCP controls the operational amplifier AMP so as to forcibly pull up the gate signal G1 and close the transistor M1 when the input current IIN flowing through the transistor M1 becomes larger than the overcurrent protection value IOCP. Therefore, as long as the overcurrent protection circuit OCP is operating correctly, the input current IIN can be limited to the overcurrent protection value IOCP or less.

The superheat protection circuit TSD controls the operational amplifier AMP so as to forcibly pull up the gate signal G1 and close the transistor M1 when the junction temperature Tj of the semiconductor device 100 becomes higher than the superheat protection value Ttsd. Therefore, as long as the superheat protection circuit TSD is operating correctly, the junction temperature Tj of the semiconductor device 100 can be limited to the superheat protection value Ttsd or less.

By the way, the semiconductor device 100 is accompanied by a parasitic element (for example, an npn-type bipolar transistor Q0, which is hereinafter referred to as a parasitic transistor Q0) that is not incorporated in the original circuit operation due to its device structure.

According to this figure, the parasitic transistor Q0 is based on a P-type semiconductor substrate (Psub), has an N-type semiconductor region (= cathode) of the Zena diode D1 as an emitter, and has an N-type semiconductor region (for example, an internal circuit). , The drain of the N-channel MOS field effect transistor M2 connected to the gate of the transistor M1 as the output stage of the operational amplifier AMP) is formed as a collector. Hereinafter, the description of the parasitic transistor Q0 will be continued with reference to a schematic vertical cross section of the semiconductor device 100.

FIG. 2 is a diagram showing a vertical cross section of the semiconductor device 100. N-type semiconductor wells 102 and 103 are formed on the P-type semiconductor substrate 101 of the semiconductor device 100. An N-type semiconductor contact 104 is formed in the N-type semiconductor well 102. N-type semiconductor contacts 105 and 106 are formed in the N-type semiconductor well 103. Further, a P-type semiconductor well 107 is formed in the N-type semiconductor well 103. A P-type semiconductor contact 108 is formed in the P-type semiconductor well 107.

The N-type semiconductor well 102 is an N-type semiconductor region for forming an internal circuit (NMOS, MOSFET, npn, pnp, etc.), and the drain of the transistor M2 in FIG. 1 corresponds to this. The N-type semiconductor well 102 is connected to another internal circuit (for example, the gate of the transistor M1 in FIG. 1) via the N-type semiconductor contact 104.

The N-type semiconductor well 103 is an N-type semiconductor region for forming an electrostatic protection element, and the cathode of the Zener diode D1 in FIG. 1 corresponds to this, for example. The N-type semiconductor well 103 is connected to the external terminal T1 via the N-type semiconductor contacts 105 and 106.

The P-type semiconductor well 107 is a P-type semiconductor region for forming an electrostatic protection element, and the anode of the Zener diode D1 in FIG. 1 corresponds to this, for example. The P-type semiconductor well 107 is connected to the ground end via the P-type semiconductor contact 108.

In the semiconductor device 100 having the above device structure, the parasitic transistor Q0 is based on the P-type semiconductor substrate 101, and uses the N-type semiconductor well 103 or the N-type semiconductor contacts 105 and 106 (= cathode of the Zena diode D1) as emitters. It is formed as an npn-type bipolar transistor having an N-type semiconductor well 102 or an N-type semiconductor contact 104 (= drain of the transistor M2) as a collector.

In the semiconductor device 100 accompanied by such a parasitic transistor Q0, for example, when an output current IOUT larger than the overcurrent protection value IOCP is drawn from the external terminal T1, the output current IOUT is drawn from the ground end to the external terminal T1 via the Zener diode D1. A directed forward diode current IDi (= IOUT-IOCP) flows. Therefore, a negative voltage (= −Vf (D1)) corresponding to the forward voltage drop Vf (D1) of the Zener diode D1 is generated at the external terminal T1.

When a potential difference of more than the forward voltage drop Vf (Q0) occurs between the base and emitter of the parasitic transistor Q0 due to the generation of the negative voltage, the parasitic transistor Q0 is turned on and the drain of the transistor M2 (and the gate of the transistor M1) is turned on. ), The current is drawn. As a result, contrary to the gate control of the operational amplifier AMP, the transistor M1 may be erroneously turned on, which may lead to malfunction or destruction of the set on which the semiconductor device 100 is mounted.

In addition to the electrostatic protection element (for example, Zener diode D1), the parasitic factor element connected to the external terminal T1 where a negative voltage can be generated and causing the parasitic transistor Q0 includes an N-channel type MOS field effect transistor and the like. Can be mentioned.

Hereinafter, the behavior of the external terminal T1 when a negative voltage is generated will be specifically described with reference to the drawings.

FIG. 3 is a diagram showing the behavior when a negative voltage is generated in the comparative example. In order from the top, each of the output voltage VOUT, the input current IIN, the diode current IDi, and the lost power Plus is correlated with the output current IOUT. The relationship is depicted.

The period (1) corresponds to the normal operation period of the semiconductor device 100. That is, in the period (1), no negative voltage is generated in the external terminal T1 and the parasitic transistor Q0 is not turned on. Further, when the input current IIN reaches the overcurrent protection value IOCP, the overcurrent protection circuit OCP operates so that no more current flows. Therefore, basically, the input current IIN does not flow beyond the overcurrent protection value IOCP. In the period (1), the lost power Plus determined by P1 = (VIN-VOUT) × IOUT is generated.

The period (2) corresponds to the current limiting period by the overcurrent protection circuit OCP. When an inductance component is present in the external terminal T1 or a forced load test is performed, an output current IOUT larger than the overcurrent protection value IOCP may be drawn from the external terminal T1. At this time, since the input current IIN is limited to the overcurrent protection value IOCP, the insufficient current flows as the diode current IDi. As a result, a negative voltage (= −Vf (D1)) corresponding to the forward voltage drop Vf (D1) of the Zener diode D1 is generated at the external terminal T1. However, in the period (2), Vf (D1) <Vf (Q0) is still satisfied, and the parasitic transistor Q0 does not turn on. Therefore, in the period (2), the power loss loss determined by P2 = (VIN + Vf (D1)) × IOCP + Vf (D1) × (IOUT-IOCP) is generated.

The length of the period (2) is determined by the layout, internal circuit, impedance, etc. of the semiconductor device 100. The parasitic element (for example, the parasitic transistor Q0) may cause the internal circuit to malfunction immediately after the generation of the negative voltage, or the parasitic element may not cause the malfunction.

The period (3) corresponds to a malfunction period due to the parasitic element. When a negative voltage (= −Vf (D1)) is generated, a potential difference of more than the forward voltage drop Vf (Q0) occurs between the base and emitter of the parasitic transistor Q0 and the parasitic transistor Q0 is turned on, the internal circuit malfunctions.

For example, consider the case where the drain of the transistor M2 forming the output stage of the operational amplifier AMP becomes the collector of the parasitic transistor Q0 as shown in FIG. 1 above. In this case, a collector current (for example, mA order) that is much larger than the off current (for example, μA order) that the overcurrent protection circuit OCP (or overheat protection circuit TSD) is flowing into the gate of the transistor M1 is parasitic from the gate of the transistor M1. It can be pulled out by transistor Q0.

In such a situation, the overcurrent protection circuit OCP cannot maintain the gate signal G1 at a high level, and the transistor M1 is erroneously turned on. As a result, the input current IIN (and thus the output current IOUT) increases beyond the overcurrent protection value IOCP, which may lead to the destruction of the semiconductor device 100 and the set on which the semiconductor device 100 is mounted.

In the period (3), the lost power Plus determined by P3 = (VIN + Vf (D1)) × (IOUT-IDi) + Vf (D1) × IDi is generated. That is, the higher the input voltage VIN, the larger the power loss loss, and the higher the possibility that the semiconductor device 100 and the set on which the semiconductor device 100 is mounted will be destroyed.

Hereinafter, various embodiments that can solve the above-mentioned problems will be described.

<Semiconductor device (first embodiment)>
FIG. 4 is a diagram showing a first embodiment of the semiconductor device. The semiconductor device 41 of the present embodiment is based on the above-mentioned comparative example (FIG. 1), and includes an npn-type bipolar transistor Q2, an N-channel type MOS field-effect transistor M5, and a P-channel type MOS field-effect transistor M6. It further has resistors R5 and R6.

The base and emitter of the transistor Q2 are connected to a grounded end (for example, a P-type semiconductor substrate). The collector of transistor Q2 is connected to the gate of transistor M6. The transistor Q2 connected in this way functions as a dummy element that is always turned off. The transistor Q2 is formed between the Zener diode D1 and the transistor M2 (= a position closer to the Zener diode D1 than the transistor M2), and between the cathode of the Zener diode D1 and the collector of the transistor Q2. A parasitic transistor Q3 is attached (details will be described later).

The drain of the transistor M5 is connected to the external terminal T1. The gate of the transistor M5 and the first end of the resistor R5 are connected to the drain of the transistor M6. The source of the transistor M5 and the second end of the resistor R5 are connected to the ground end. The source of the transistor M6 and the first end of the resistor R6 are connected to the source of the transistor M1 (= the input end of the input voltage VIN). The gate of the transistor M6 and the second end of the resistor R6 are connected to the collector of the transistor Q2 (and thus the collector of the parasitic transistor Q3).

The transistors M5 and M6 and the resistors R5 and R6 connected in this way function as a current supply circuit CS that supplies current to the external terminal T1 when the parasitic transistor Q3 is turned on. More specifically, the current supply circuit CS generates a transistor current IM5 that flows from the ground end toward the external terminal T1 when the parasitic transistor Q3 is turned on.

The transistor M5 corresponds to a first switch element that short-circuits between the external terminal T1 and the ground end when the parasitic transistor Q3 is turned on. Further, the transistor M6 corresponds to a second switch element that short-circuits between the power supply end (= input end of the input voltage VIN) and the gate of the first switch element when the parasitic transistor Q3 is turned on.

In the following, the description of the parasitic transistor Q3 will be continued with reference to the schematic planar layout and vertical cross section of the semiconductor device 41.

FIG. 5 is a diagram showing a planar layout (upper row) and a vertical cross section (lower row) of the semiconductor device 41. As shown in this figure, a plurality of element forming regions (in this figure, three element forming regions 410, 420, and 430 are exemplified) are formed in the P-type semiconductor substrate 400 of the semiconductor device 41.

The element forming region 410 corresponds to the forming region of the electrostatic protection element (for example, the Zener diode D1). In the element forming region 410, an N-type semiconductor well 411 is formed on the P-type semiconductor substrate 400. N-type semiconductor contacts 412 and 413 are formed in the N-type semiconductor well 411. Further, a P-type semiconductor well 414 is formed in the N-type semiconductor well 411. A P-type semiconductor contact 415 is formed in the P-type semiconductor well 414.

The N-type semiconductor well 411 corresponds to the cathode (C) of the Zener diode D1 and is connected to the external terminal T1 via the N-type semiconductor contacts 412 and 413. These N-type semiconductor wells 411 and the N-type semiconductor contacts 412 and 413 can be understood as N-type first semiconductor regions connected to the external terminal T1. On the other hand, the P-type semiconductor well 414 corresponds to the anode (A) of the Zener diode D1 and is connected to the ground end via the P-type semiconductor contact 415.

The element forming region 420 corresponds to the forming region of the internal circuit (for example, the transistor M2). In the element forming region 420, the P-type semiconductor well 421 is formed on the P-type semiconductor substrate 400. A P-type semiconductor contact 422 is formed in the P-type semiconductor well 421. Further, N-type semiconductor regions 423 and 424 are formed in the P-type semiconductor well 421.

The N-type semiconductor regions 423 and 424 correspond to the source (S) and drain (D) of the transistor M2, and a gate (G) is formed on the channel region between them with an insulating layer interposed therebetween. .. These N-type semiconductor regions 423 and 424 can be understood as N-type second semiconductor regions that form an internal circuit. On the other hand, the P-type semiconductor well 421 corresponds to the back gate (BG) of the transistor M2 and is connected to the source of the transistor M2 (= N-type semiconductor region 423) via the P-type semiconductor contact 422.

The element forming region 430 corresponds to a forming region of a dummy element (for example, transistor Q2). As shown in this figure, the element forming region 430 is arranged at a position closer to the element forming region 410 than the element forming region 420 (for example, between the element forming region 410 and the element forming region 420). .. In other words, the distance dx between the element forming region 410 and the element forming region 430 is shorter than the distance dy between the element forming region 410 and the element forming region 420.

In the element forming region 430, an N-type semiconductor well 431 is formed on the P-type semiconductor substrate 400. An N-type semiconductor contact 432 is formed in the N-type semiconductor well 431. Further, a P-type semiconductor well 433 is formed in the N-type semiconductor well 431. A P-type semiconductor contact 434 and an N-type semiconductor region 435 are formed in the P-type semiconductor well 433.

The N-type semiconductor well 431 corresponds to the collector (C) of the transistor Q2 and is connected to the current supply circuit CS (more specifically, the gate of the transistor M6) via the N-type semiconductor contact 432. These N-type semiconductor wells 431 and N-type semiconductor contacts 432 are the first semiconductor region (= N-type semiconductor wells 411 and N-type semiconductor contacts 412 and 413) and the second semiconductor region (= N-type semiconductor regions 423 and 424). It can be understood as a third semiconductor region formed between and. On the other hand, the P-type semiconductor well 433 corresponds to the base (B) of the transistor Q2 and is connected to the ground end via the P-type semiconductor contact 434. Further, the N-type semiconductor region 435 corresponds to the emitter (E) of the transistor Q2 and is connected to the ground end.

However, the dummy element formed in the element forming region 430 is not limited to the npn-type bipolar transistor Q2, but has an N-type semiconductor region (= corresponding to the third semiconductor region) that serves as a collector for the parasitic transistor Q3. If there is, any dummy element such as a pnp type bipolar transistor, an N channel type MOS field effect transistor, or a P channel type MOS field effect transistor can be used.

Further, as the dummy element, only the N-type semiconductor region (for example, only the N-type semiconductor well 431 and the N-type semiconductor contact 432) may be formed. That is, the dummy element does not have to be an element that functions by itself.

In the semiconductor device 41 having the above device structure, the parasitic transistor Q3 is based on the P-type semiconductor substrate 400, and uses the N-type semiconductor well 411 and the N-type semiconductor contacts 412 and 413 (= cathode of the Zena diode D1) as emitters. It is formed as an npn-type bipolar transistor having an N-type semiconductor well 431 or an N-type semiconductor contact 432 (= collector of transistor Q2) as a collector.

In the semiconductor device 41 accompanied by such a parasitic transistor Q3, for example, when an output current IOUT larger than the overcurrent protection value IOCP is drawn from the external terminal T1, the output current IOUT is drawn from the ground end to the external terminal T1 via the Zener diode D1. A directed forward diode current IDi (= IOUT-IOCP) flows. Therefore, a negative voltage (= −Vf (D1)) corresponding to the forward voltage drop Vf (D1) of the Zener diode D1 is generated at the external terminal T1.

When the generation of the negative voltage causes a potential difference of the forward voltage drop Vf (Q3) or more between the base and the emitter of the parasitic transistor Q3, the parasitic transistor Q3 is turned on. At this time, the parasitic transistor Q3 draws a current by using the N-type semiconductor region existing closer to the emitter as a collector when viewed from the N-type semiconductor region (= N-type semiconductor well 411 and the N-type semiconductor contacts 412 and 413). start.

According to this figure, the parasitic transistor Q3 is a collector (= N-type semiconductor well) of the transistor Q2 before the parasitic transistor Q0 starts to draw a current from the drain (= N-type semiconductor region 424) of the transistor M2. Start drawing current from 431 and N-type semiconductor contact 432). That is, the parasitic transistor Q3 starts to draw the current first from the dummy element closer to the electrostatic protection element than the internal circuit. As a result, the current supply circuit CS operates to supply the transistor current IM5 to the external terminal T1. Hereinafter, the behavior when such a negative voltage is generated will be specifically described with reference to the drawings.

FIG. 6 is a diagram showing the behavior when a negative voltage is generated in the first embodiment, and is an output current for each of the output voltage VOUT, the input current IIN, the diode current IDi, the transistor current IM5, and the lost power Plus in order from the top. The correlation with IOUT is depicted.

The period (1) corresponds to the normal operation period of the semiconductor device 41. That is, during the period (1), no negative voltage is generated at the external terminal T1, and the parasitic transistor Q0 (see FIG. 1) is not turned on. Further, in the period (1), since the parasitic transistor Q3 is not turned on, the gate of the transistor M6 is pulled up to the input voltage VIN via the resistor R6. As a result, the transistor M6 is turned off, and the gate of the transistor M5 is pulled down to the ground end via the resistor R5, so that the transistor M5 is also turned off. Therefore, the current supply circuit CS does not adversely affect the operation of generating the output voltage VOUT. In the period (1), the lost power Plus determined by P1 = (VIN-VOUT) × IOUT is generated. As described above, the normal operation period of the semiconductor device 41 is no different from that of the above-mentioned comparative example (see FIG. 3).

The period (2) corresponds to the current limiting period by the overcurrent protection circuit OCP. As described above, when an inductance component is present in the external terminal T1 or when a forced load test is performed, an output current IOUT larger than the overcurrent protection value IOCP may be drawn from the external terminal T1. At this time, since the input current IIN is limited to the overcurrent protection value IOCP, the insufficient current flows as the diode current IDi. As a result, a negative voltage (= −Vf (D1)) corresponding to the forward voltage drop Vf (D1) of the Zener diode D1 is generated at the external terminal T1. However, in the period (2), Vf (D1) <Vf (Q3) is still satisfied, and the parasitic transistor Q3 is not turned on. Therefore, in the period (2), the power loss loss determined by P2 = (VIN + Vf (D1)) × IOCP + Vf (D1) × (IOUT-IOCP) is generated.

As described above, the current limiting period by the overcurrent protection circuit OCP is basically the same as that of the above-mentioned comparative example (FIG. 3). However, the timing at which the parasitic transistor Q3 starts drawing current from the collector of transistor Q2 is earlier than the timing at which the parasitic transistor Q0 starts drawing current from the drain of transistor M2. Therefore, the length of the period (2) is shorter than that of the above-mentioned comparative example (see FIG. 3).

The period (3) corresponds to the current supply period due to the parasitic operation. As the diode current IDi increases, the output voltage VOUT further decreases negatively, and when a potential difference of the forward voltage drop Vf (Q3) or more occurs between the base and emitter of the parasitic transistor Q3, the parasitic transistor Q3 turns on. ..

When the parasitic transistor Q3 is turned on, the negative voltage (= −Vf (Q3)) of the external terminal T1 is applied to the gate of the transistor M6, so that the transistor M6 is turned on. Therefore, the power supply end (= input end of the input voltage VIN) and the gate of the transistor M5 are short-circuited to turn on the transistor M5, so that the external terminal T1 and the ground end are short-circuited.

In this way, when the transistor M5 is turned on, the external terminal T1 conducts with the ground end via the current path having the lowest impedance among the current paths connected to the external terminal T1 (= including the current path via the parasitic transistor Q0). .. Therefore, of the output current IOUT, the shortage current exceeding the overcurrent protection value IOCP is covered by the transistor current IM5, which flows from the ground end toward the external terminal T1 after the transistor M5 is turned on. ..

At this time, the negative voltage of the external terminal T1 is maintained at a negative voltage (= −Vf (Q3)> −Vf (Q0)) corresponding to the forward voltage drop Vf (Q3) of the parasitic transistor Q3. Therefore, since the parasitic transistor Q0 does not turn on, the malfunction of the internal circuit can be prevented and the transistor M1 can be surely turned off.

In the period (3), most of the output current IOUT drawn from the external terminal T1 is covered by the transistor current IM5. Therefore, unlike the comparative example (FIG. 3) above, P3 = (VIN + Vf (Q3)) × Only the loss power Plus determined by IOCP + Vf (Q3) × (IDi + IM5) is generated.

Therefore, it is possible to suppress the power loss loss to a small value, and it is possible to prevent the semiconductor device 51 and the set on which the semiconductor device 51 is mounted from being destroyed.

<Other variants>
In the above embodiment, an example of application to the LDO regulator IC has been given, but the application target is not limited to this. For example, it can be applied as a countermeasure against negative voltage at an external terminal (enable terminal, output feedback terminal, etc.) other than the output terminal.

As described above, the various technical features disclosed in the present specification can be modified in addition to the above-described embodiment without departing from the spirit of the technical creation. That is, it should be considered that the above-described embodiment is exemplary in all respects and is not restrictive, and the technical scope of the present invention is not limited to the above-described embodiment and claims for a patent. It should be understood that the meaning equivalent to the scope of and all changes belonging to the scope are included.

The invention disclosed in the present specification can be widely used in all semiconductor devices having a parasitic element.

41, 100 Semiconductor device 101 P-type semiconductor substrate 102, 103 N-type semiconductor well 104, 105, 106 N-type semiconductor contact 107 P-type semiconductor well 108 P-type semiconductor contact 400 P-type semiconductor substrate 410 Element formation area 411 N-type semiconductor well 412, 413 N-type semiconductor contact 414 P-type semiconductor well 415 P-type semiconductor contact 420 Element formation area 421 P-type well 422 P-type semiconductor contact 423, 424 N-type semiconductor area 430 Element formation area 431 N-type semiconductor well 432 N-type semiconductor Contact 433 P-type semiconductor well 434 P-type semiconductor contact 435 N-type semiconductor area AMP operational amplifier (output drive unit)
CS current supply circuit D1 Zener diode (electrostatic protection element, parasitic factor element)
M1 P-channel type MOS field effect transistor (output element)
M2 N-channel type MOS field-effect transistor M5 N-channel type MOS field-effect transistor (first switch element)
M6 P-channel type MOS field effect transistor (second switch element)
OCP overcurrent protection circuit Q0 npn type bipolar transistor (parasitic element)
Q2 npn type bipolar transistor (dummy element)
Q3 npn type bipolar transistor (parasitic element)
R1, R2, R5, R6 resistor T1 external terminal TSD overheat protection circuit

Claims (10)

With external terminals
The first semiconductor region connected to the external terminal and
The second semiconductor region that forms the internal circuit and
A third semiconductor region formed closer to the first semiconductor region than the second semiconductor region,
A current supply circuit that supplies current to the external terminal when a parasitic element attached between the first semiconductor region and the third semiconductor region is turned on.
A semiconductor device characterized by having. The claim is characterized in that the parasitic element is an npn-type transistor based on a P-type semiconductor substrate, having an N-type first semiconductor region as an emitter, and an N-type third semiconductor region as a collector. The semiconductor device according to 1. The semiconductor according to claim 1 or 2, wherein the current supply circuit includes a first switch element that short-circuits between the external terminal and the reference potential end when the parasitic element is turned on. apparatus. The semiconductor device according to claim 3, wherein the first switch element is an N-channel transistor in which a drain is connected to the external terminal and a source is connected to the reference potential end. The semiconductor device according to claim 4, wherein the current supply circuit further includes a second switch element that short-circuits between the power supply end and the gate of the first switch element when the parasitic element is turned on. .. The second switch element is a P-channel transistor in which a source is connected to the power supply end, a drain is connected to a gate of the first switch element, and the gate is connected to the third semiconductor region. The semiconductor device according to claim 5. The current supply circuit
The first resistor connected between the gate and source of the first switch element and
A second resistor connected between the gate and source of the second switch element,
The semiconductor device according to claim 6, further comprising. The semiconductor device according to any one of claims 1 to 7, further comprising an electrostatic protection element connected between the external terminal and the reference potential end. The semiconductor device according to any one of claims 1 to 8, further comprising an output element connected between an input end of an input voltage and the external terminal. The semiconductor device according to claim 9, further comprising an output drive unit that drives the output element so that the output voltage appearing at the external terminal or the feedback voltage corresponding thereto matches a predetermined reference voltage. ..

Images