JP2006157937A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP2006157937A
JP2006157937A JP2005359033A JP2005359033A JP2006157937A JP 2006157937 A JP2006157937 A JP 2006157937A JP 2005359033 A JP2005359033 A JP 2005359033A JP 2005359033 A JP2005359033 A JP 2005359033A JP 2006157937 A JP2006157937 A JP 2006157937A
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voltage
mos transistor
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semiconductor integrated
integrated circuit
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JP4326521B2 (en
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Nobuhiro Nishikawa
信広 西川
Koichi Inoue
晃一 井上
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Rohm Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of preventing breakdown in a withstand voltage of a MOS transistor even if an usage range of a power supply voltage is extended. <P>SOLUTION: The circuit device comprises a MOS transistor M2 provided with a parasitic diode Dx2 for preventing a reverse current caused by a parasitic diode Dx1 of a MOS transistor M1, a voltage setting circuit 1 for turning the MOS transistor M2 off at the time of a reverse bias being supplied, and an adverse current preventing element 2 for preventing an adverse current from flowing through the voltage setting circuit 1 at the time of the reverse bias. A direct current voltage which is within a withstand voltage of the MOS transistor M2 is supplied to a gate in response to a voltage supplied to a conductive terminal 6y of the MOS transistor M2 at the time of normal operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、ＭＯＳトランジスタを使用する半導体集積回路装置に関するもので、特に、ＭＯＳトランジスタにおける逆流電流の発生を防ぐための構成を備えた半導体集積回路装置に関する。   The present invention relates to a semiconductor integrated circuit device using a MOS transistor, and more particularly to a semiconductor integrated circuit device having a configuration for preventing the occurrence of a reverse current in a MOS transistor.

半導体集積回路装置において、図４（ａ）のようにＰ型拡散層１２とバックゲートに電源電圧Ｖｄｄが印加されたＰチャネルのＭＯＳトランジスタＭ１が設けられるものがある。このＭＯＳトランジスタＭ１は、図４（ｂ）のように、Ｐ型拡散層１１，１２と、Ｎ型拡散層１４によるバックゲートと、Ｎ型ウェル層１０の表面に絶縁膜１３を介して設けられるゲートとを備え、Ｐ型拡散層１１とＮ型ウェル層１０及びバックゲートのＮ型拡散層１４とによってＰＮ接合の寄生ダイオードＤｘが構成される。   In some semiconductor integrated circuit devices, as shown in FIG. 4A, a P-type diffusion layer 12 and a P-channel MOS transistor M1 having a power supply voltage Vdd applied to a back gate are provided. As shown in FIG. 4B, the MOS transistor M1 is provided with P-type diffusion layers 11 and 12, a back gate formed by the N-type diffusion layer 14, and the surface of the N-type well layer 10 via an insulating film 13. The P-type diffusion layer 11, the N-type well layer 10, and the back-gate N-type diffusion layer 14 constitute a PN junction parasitic diode Dx.

よって、ＭＯＳトランジスタＭ１に逆バイアスがかかったとき、Ｐ型拡散層１１から寄生ダイオードＤｘを介してＰ型拡散層１２及びバックゲートとなるＮ型拡散層１４に逆流電流が流れる。このような逆流電流の発生を防ぐために、図４（ｃ）のように、ＭＯＳトランジスタＭ１のＰ型拡散層１２及びバックゲートと電源電圧Ｖｄｄとの間にアノードに電源電圧Ｖｄｄが印加されたダイオードＤａを設けることがある。しかしながら、このように逆流防止用にダイオードＤａを設けた場合、このダイオードＤａによる電圧損失が生じるという問題がある。   Therefore, when a reverse bias is applied to the MOS transistor M1, a reverse current flows from the P-type diffusion layer 11 to the P-type diffusion layer 12 and the N-type diffusion layer 14 serving as the back gate via the parasitic diode Dx. In order to prevent the occurrence of such a reverse current, a diode in which the power supply voltage Vdd is applied to the anode between the P-type diffusion layer 12 and the back gate of the MOS transistor M1 and the power supply voltage Vdd as shown in FIG. Da may be provided. However, when the diode Da is provided to prevent backflow in this way, there is a problem that voltage loss occurs due to the diode Da.

このような逆流防止用のダイオードのように電圧損失を生じることなく、逆流電流を防ぐことができる出力段回路が、従来技術として提案されている（特許文献１参照）。この特許文献１における出力段回路は、ＰチャネルのＭＯＳトランジスタのソース及びバックゲートと電源電圧との間にスイッチを設け、電源電圧監視回路で電源電圧低下を確認するとスイッチをＯＦＦとすることで、逆流を防ぐ構成としている。
特開平１０−３４１１４１号公報 An output stage circuit capable of preventing a backflow current without causing a voltage loss like the backflow prevention diode has been proposed as a conventional technique (see Patent Document 1). The output stage circuit in this patent document 1 is provided with a switch between the source and back gate of the P-channel MOS transistor and the power supply voltage, and when the power supply voltage monitoring circuit confirms a drop in the power supply voltage, The structure prevents backflow.
JP 10-341141 A

しかしながら、特許文献１による逆流防止用に設けられた電源電圧監視回路は、インバータ又はＮＡＮＤゲートによって構成され、通常動作を行うときは、スイッチとなるＰチャネルのＭＯＳトランジスタのゲートに電源電圧監視回路より接地電圧が印加されることでＯＮとしている。このように、スイッチとなるＰチャネルのＭＯＳトランジスタのゲートに接地電圧が印加された状態で使用されるため、このスイッチとなるＰチャネルのＭＯＳトランジスタにおける耐圧破壊を招きやすい構成となっている。よって、このような耐圧破壊を防ぐためには、耐圧電圧を超えないように、電源電圧Ｖｄｄを設定する必要があり、その使用範囲が制限されてしまう。   However, the power supply voltage monitoring circuit provided for preventing backflow according to Patent Document 1 is configured by an inverter or a NAND gate. When performing normal operation, the power supply voltage monitoring circuit is connected to the gate of a P-channel MOS transistor serving as a switch. It is turned ON when a ground voltage is applied. In this way, since the ground voltage is applied to the gate of the P-channel MOS transistor serving as the switch, the breakdown voltage of the P-channel MOS transistor serving as the switch is likely to be destroyed. Therefore, in order to prevent such breakdown withstand voltage, it is necessary to set the power supply voltage Vdd so as not to exceed the withstand voltage, and its use range is limited.

このような問題を鑑みて、本発明は、電源電圧の使用範囲を拡げても、ＭＯＳトランジスタの耐圧破壊を防ぐことが可能な半導体集積回路装置を提供することを目的とする。   In view of such a problem, an object of the present invention is to provide a semiconductor integrated circuit device that can prevent a breakdown voltage of a MOS transistor even if the range of use of a power supply voltage is expanded.

上記の目的を達成するために、本発明の半導体集積回路装置は、第１バックゲート領域と、ソース領域及びドレイン領域の一方となるとともに前記第１バックゲート領域と接続される第１導電領域と、ソース領域及びドレイン領域の他方となる第２導電領域と、を有する第１ＭＯＳトランジスタを備える半導体集積回路装置において、前記第１ＭＯＳトランジスタの前記第１バックゲート領域と前記第１導電領域に接続された第２バックゲート領域と、ソース領域及びドレイン領域の一方となるとともに前記第２バックゲート領域と接続される第３導電領域と、ソース領域及びドレイン領域の他方となるとともに第１直流電圧が印加される第４導電領域と、を有する第２ＭＯＳトランジスタと、該第２ＭＯＳトランジスタのゲートに供給する第２直流電圧を設定する電圧設定回路と、前記第１直流電圧と同一の電源電圧より生成される第３直流電圧が印加されるとともに、前記電圧設定回路に接続して前記電圧設定回路における逆流を阻止する逆流防止素子と、を備え、前記電圧設定回路において、前記第１直流電圧を基準として前記第２ＭＯＳトランジスタの耐圧範囲内となる直流電圧を、前記第２直流電圧とすることを特徴とする。   In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes a first back gate region, a first conductive region which is one of a source region and a drain region and is connected to the first back gate region. In a semiconductor integrated circuit device comprising a first MOS transistor having a second conductive region that is the other of a source region and a drain region, the first back gate region and the first conductive region of the first MOS transistor are connected to the first MOS transistor The second back gate region, one of the source region and the drain region and the third conductive region connected to the second back gate region and the other of the source region and the drain region and the first DC voltage are applied A second MOS transistor having a fourth conductive region and a gate of the second MOS transistor 2 A voltage setting circuit for setting a DC voltage and a third DC voltage generated from the same power supply voltage as the first DC voltage are applied and connected to the voltage setting circuit for backflow in the voltage setting circuit. And a backflow preventing element for blocking, wherein in the voltage setting circuit, a DC voltage that falls within a withstand voltage range of the second MOS transistor with respect to the first DC voltage is defined as the second DC voltage. .

この構成によると、逆バイアス印加時には、前記逆流防止素子により前記電圧設定回路に逆流電流が流れることが阻止されて、前記電圧設定回路より前記第２ＭＯＳトランジスタの駆動範囲の電圧が出力されず、前記第２ＭＯＳトランジスタがＯＦＦとなる。又、前記第２直流電圧が前記第２ＭＯＳトランジスタの耐圧範囲内となるように調整されるため、前記第２直流電圧が前記第２ＭＯＳトランジスタに印加される電圧に応じた電圧とされて、前記第２ＭＯＳトランジスタの耐圧破壊を防ぐことができる。   According to this configuration, when a reverse bias is applied, a reverse current is prevented from flowing through the voltage setting circuit by the reverse current prevention element, and a voltage in the driving range of the second MOS transistor is not output from the voltage setting circuit. The second MOS transistor is turned off. Further, since the second DC voltage is adjusted so as to be within the breakdown voltage range of the second MOS transistor, the second DC voltage is set to a voltage corresponding to the voltage applied to the second MOS transistor, and The breakdown voltage of the 2MOS transistor can be prevented.

このような半導体集積回路装置において、前記第１ＭＯＳトランジスタ及び前記第２ＭＯＳトランジスタを同一極性のトランジスタとし、第２ＭＯＳトランジスタ内に構成される寄生ダイオードによって、第１ＭＯＳトランジスタに構成される寄生ダイオードによる逆流電流の発生を防ぐことができる。   In such a semiconductor integrated circuit device, the first MOS transistor and the second MOS transistor are transistors of the same polarity, and a reverse current caused by a parasitic diode formed in the first MOS transistor is caused by a parasitic diode formed in the second MOS transistor. Occurrence can be prevented.

又、前記逆流防止素子がダイオードであり、当該ダイオードが逆バイアス時に電流が流れないように接続される。更に、前記電圧設定回路が分圧抵抗により構成され、当該分圧抵抗の抵抗値が調整されることによって、前記分圧抵抗により発生する分圧電圧が前記第２直流電圧として前記第２ＭＯＳトランジスタのゲートに出力される。   The backflow prevention element is a diode, and the diode is connected so that no current flows during reverse bias. Further, the voltage setting circuit is constituted by a voltage dividing resistor, and the resistance value of the voltage dividing resistor is adjusted, whereby the divided voltage generated by the voltage dividing resistor is used as the second DC voltage of the second MOS transistor. Output to the gate.

このような半導体集積回路装置において、前記第１ＭＯＳトランジスタ及び前記第２ＭＯＳトランジスタを、耐圧を通常よりも広くしたＭＯＳ構造としても構わない。又、前記第１ＭＯＳトランジスタ及び前記第２ＭＯＳトランジスタを、ＰチャネルのＭＯＳトランジスタとしても構わない。   In such a semiconductor integrated circuit device, the first MOS transistor and the second MOS transistor may have a MOS structure whose breakdown voltage is wider than usual. The first MOS transistor and the second MOS transistor may be P-channel MOS transistors.

又、本発明の半導体集積回路装置は、バックゲートと第１Ｐ型拡散層と第２Ｐ型拡散層を備えるとともに、前記バックゲートと前記第１Ｐ型拡散層が接続されたＰチャネルの第１ＭＯＳトランジスタを備える半導体集積回路装置において、前記第１ＭＯＳトランジスタのバックゲートと第１Ｐ型拡散層にバックゲート及び第３Ｐ型拡散層が接続されるとともに第４Ｐ型拡散層に第１直流電圧が印加されるＰチャネルの第２ＭＯＳトランジスタと、一端が接地されるとともにその分圧電圧を前記第２ＭＯＳトランジスタのゲートに第２直流電圧として供給する分圧抵抗回路と、第３直流電圧がアノードに印加されるとともにカソードが前記分圧抵抗回路の他端に接続されるダイオードと、を備え、前記分圧抵抗回路からの前記第２直流電圧を、前記第１直流電圧を基準として前記第２ＭＯＳトランジスタの耐圧範囲内の電圧とすることを特徴とする。   The semiconductor integrated circuit device according to the present invention includes a back gate, a first P-type diffusion layer, and a second P-type diffusion layer, and includes a P-channel first MOS transistor connected to the back gate and the first P-type diffusion layer. In the semiconductor integrated circuit device, the back gate and the third P type diffusion layer are connected to the back gate and the first P type diffusion layer of the first MOS transistor, and the first DC voltage is applied to the fourth P type diffusion layer. The second MOS transistor, one end of which is grounded and a voltage dividing resistor circuit for supplying the divided voltage to the gate of the second MOS transistor as a second DC voltage, and the third DC voltage is applied to the anode and the cathode A diode connected to the other end of the voltage dividing resistor circuit, and the second DC voltage from the voltage dividing resistor circuit, The serial first DC voltage, characterized in that the voltage in the withstand voltage range of the first 2MOS transistor as a reference.

本発明によると、第２ＭＯＳトランジスタによって構成される寄生ダイオードによって逆バイアス印加時に第１ＭＯＳトランジスタによって構成される寄生ダイオードによる逆流電流を防ぐことができる。又、逆バイアス印加時に逆流電流防止素子により電圧設定回路における逆流電流を防止することができるので、第２ＭＯＳトランジスタをＯＦＦとして、半導体集積回路装置の動作に逆流電流が流れ込むことを防ぐことができる。更に、電圧設定回路で第２ＭＯＳトランジスタの耐圧範囲内の第２直流電圧を第２ＭＯＳトランジスタに与えるため、第１及び第２ＭＯＳトランジスタの耐圧破壊を防ぐことができる。又、この第２直流電圧が電源電圧により調整することが可能なため、電源電圧の高低にかかわらず、第１及び第２ＭＯＳトランジスタの耐圧破壊を防ぐことができる。   According to the present invention, the reverse current caused by the parasitic diode constituted by the first MOS transistor can be prevented when the reverse bias is applied by the parasitic diode constituted by the second MOS transistor. Further, since the reverse current in the voltage setting circuit can be prevented by the reverse current prevention element when the reverse bias is applied, the second MOS transistor can be turned off to prevent the reverse current from flowing into the operation of the semiconductor integrated circuit device. Furthermore, since the second DC voltage within the breakdown voltage range of the second MOS transistor is applied to the second MOS transistor by the voltage setting circuit, breakdown breakdown of the first and second MOS transistors can be prevented. Further, since the second DC voltage can be adjusted by the power supply voltage, it is possible to prevent breakdown of the first and second MOS transistors regardless of the level of the power supply voltage.

本発明の実施形態を、図面を参照して以下に説明する。図１は、本実施形態の半導体集積回路装置の内部構成を示す回路ブロック図である。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram showing the internal configuration of the semiconductor integrated circuit device of this embodiment.

図１の半導体集積回路装置は、ＤＭＯＳ構造のＰチャネルのＭＯＳトランジスタＭ１と、ＭＯＳトランジスタＭ１のゲートに出力端子が接続されたオペアンプＡと、ＭＯＳトランジスタＭ１の導電端子７ｘ及びバックゲートに導電端子７ｙ及びバックゲートが接続されたＭＯＳトランジスタＭ２と、ＭＯＳトランジスタＭ２のゲートに所定の電圧Ｖｘを印加する電圧設定回路１と、電圧設定回路１からの逆流電流を防ぐための逆流防止用素子２と、を備え、ＭＯＳトランジスタＭ１の導電端子６ｘに現れる電圧を出力電圧として外部の負荷に供給する。   The semiconductor integrated circuit device of FIG. 1 includes a DMOS P-channel MOS transistor M1, an operational amplifier A having an output terminal connected to the gate of the MOS transistor M1, a conductive terminal 7x of the MOS transistor M1, and a conductive terminal 7y at the back gate. And a MOS transistor M2 to which the back gate is connected, a voltage setting circuit 1 for applying a predetermined voltage Vx to the gate of the MOS transistor M2, a backflow preventing element 2 for preventing a backflow current from the voltage setting circuit 1, The voltage appearing at the conductive terminal 6x of the MOS transistor M1 is supplied as an output voltage to an external load.

又、逆流防止用素子２に電源電圧Ｖｄｄが供給されるとともに、ＭＯＳトランジスタＭ２の導電端子６ｙに電源電圧Ｖｄｄが供給され、オペアンプＡの非反転入力端子にはＭＯＳトランジスタＭ１の導電端子６ｘが接続されるとともに反転入力端子に電圧Ｖｒｅｆが印加される。又、ＭＯＳトランジスタＭ１において、導電端子６ｘからバックゲートに対して寄生ダイオードＤｘ１が構成されるとともに、ＭＯＳトランジスタＭ２において、導電端子６ｙからバックゲートに対して寄生ダイオードＤｘ２が構成される。この寄生ダイオードＤｘ１，Ｄｘ２のカソード同士が接続された状態となる。   In addition, the power supply voltage Vdd is supplied to the backflow prevention element 2, the power supply voltage Vdd is supplied to the conductive terminal 6y of the MOS transistor M2, and the conductive terminal 6x of the MOS transistor M1 is connected to the non-inverting input terminal of the operational amplifier A. In addition, the voltage Vref is applied to the inverting input terminal. In the MOS transistor M1, a parasitic diode Dx1 is formed from the conductive terminal 6x to the back gate, and in the MOS transistor M2, a parasitic diode Dx2 is formed from the conductive terminal 6y to the back gate. The cathodes of the parasitic diodes Dx1, Dx2 are connected to each other.

このような半導体集積回路装置において、図２のように、逆流防止用素子２をアノードに電源電圧Ｖｄｄが印加されたダイオードＤ１で構成するとともに、電圧設定回路１を分圧抵抗Ｒ１，Ｒ２で構成する。このとき、電圧設定回路１において、抵抗Ｒ１の一端が接地されるとともに、抵抗Ｒ２の一端がダイオードＤ１のカソードに接続され、抵抗Ｒ１，Ｒ２の接続ノードがＭＯＳトランジスタＭ２のゲートに接続される。   In such a semiconductor integrated circuit device, as shown in FIG. 2, the backflow preventing element 2 is composed of a diode D1 whose power supply voltage Vdd is applied to the anode, and the voltage setting circuit 1 is composed of voltage dividing resistors R1 and R2. To do. At this time, in the voltage setting circuit 1, one end of the resistor R1 is grounded, one end of the resistor R2 is connected to the cathode of the diode D1, and the connection node of the resistors R1 and R2 is connected to the gate of the MOS transistor M2.

又、ＭＯＳトランジスタＭ１，Ｍ２はそれぞれ、図３の模式的な断面図に示されるようなＤＭＯＳ構造のＭＯＳトランジスタである。即ち、ＭＯＳトランジスタＭ１が、Ｐ型の半導体基板４上に形成されたＮ型ウェル層５に構成されるＰ型拡散層６ａ（図１及び図２の導電端子６ｘに相当する）と、同様にＮ型ウェル層５に構成されるＰ型拡散層７ａ，７ｂ（図１及び図２の導電端子７ｘに相当する）とを備え、Ｐ型拡散層６ａ，７ａの間のＮ型ウェル層５表面を覆うように形成された絶縁膜８を介してゲートが形成される。又、Ｐ型拡散層７ａ，７ｂに挟まれた部分に形成されるＮ型拡散層９ａにバックゲートが形成され、Ｐ型拡散層７ａ，７ｂと電気的に接続される。このように構成されるとき、Ｐ型拡散層７ａ，７ｂは同一層であり、バックゲートとなるＮ型拡散層９ａを囲むように形成される。   The MOS transistors M1 and M2 are MOS transistors having a DMOS structure as shown in the schematic cross-sectional view of FIG. That is, the MOS transistor M1 is similar to the P-type diffusion layer 6a (corresponding to the conductive terminal 6x in FIGS. 1 and 2) configured in the N-type well layer 5 formed on the P-type semiconductor substrate 4. P-type diffusion layers 7a and 7b (corresponding to the conductive terminals 7x in FIGS. 1 and 2) configured in the N-type well layer 5, and the surface of the N-type well layer 5 between the P-type diffusion layers 6a and 7a A gate is formed through an insulating film 8 formed so as to cover. Further, a back gate is formed in the N-type diffusion layer 9a formed in the portion sandwiched between the P-type diffusion layers 7a and 7b, and is electrically connected to the P-type diffusion layers 7a and 7b. When configured in this way, the P-type diffusion layers 7a and 7b are the same layer and are formed so as to surround the N-type diffusion layer 9a serving as a back gate.

又、ＭＯＳトランジスタＭ２が、Ｎ型ウェル層５に構成されるＰ型拡散層６ｂ（図１及び図２の導電端子６ｙに相当する）及びＰ型拡散層７ｃ，７ｄ（図１及び図２の導電端子７ｙに相当する）とを備え、Ｐ型拡散層６ｂ，７ｃの間のＮ型ウェル層５表面を覆うように形成された絶縁膜８を介してゲートが形成される。又、Ｐ型拡散層７ｃ，７ｄに挟まれた部分に形成されるＮ型拡散層９ｂにバックゲートが形成され、Ｐ型拡散層７ｃ，７ｄと電気的に接続される。このように構成されるとき、Ｐ型拡散層７ｃ，７ｄは同一層であり、バックゲートとなるＮ型拡散層９ｂを囲むように形成される。   Further, the MOS transistor M2 includes a P-type diffusion layer 6b (corresponding to the conductive terminal 6y in FIGS. 1 and 2) and P-type diffusion layers 7c and 7d (in FIGS. 1 and 2) configured in the N-type well layer 5. Corresponding to the conductive terminal 7y), and a gate is formed through an insulating film 8 formed so as to cover the surface of the N-type well layer 5 between the P-type diffusion layers 6b and 7c. Further, a back gate is formed in the N-type diffusion layer 9b formed in the portion sandwiched between the P-type diffusion layers 7c and 7d, and is electrically connected to the P-type diffusion layers 7c and 7d. When configured in this manner, the P-type diffusion layers 7c and 7d are the same layer and are formed so as to surround the N-type diffusion layer 9b serving as a back gate.

このように構成される半導体集積回路装置が通常動作を行っているとき、ＭＯＳトランジスタＭ２のゲートに電圧設定回路１から電圧Ｖｘが印加されてＭＯＳトランジスタＭ２がＯＮとされる。このとき、電圧設定回路１では、抵抗Ｒ１，Ｒ２の値を調整することにより、その分圧電圧となる電圧Ｖｘが、電源電圧Ｖｄｄとの電圧差がＭＯＳトランジスタＭ２のゲート及び導電端子７ｙ間の閾値電圧Ｖｔｈより大きい値で、ＭＯＳトランジスタＭ２の耐圧破壊電圧ＶＢより低い値となるように調整される。即ち、分圧電圧Ｖｘは、０≦Ｖｘ＜Ｖｄｄ−Ｖｔｈ及びＶｄｄ−Ｖｘ＜ＶＢの関係を満たす値とする。   When the semiconductor integrated circuit device configured as described above is performing a normal operation, the voltage Vx is applied from the voltage setting circuit 1 to the gate of the MOS transistor M2, and the MOS transistor M2 is turned on. At this time, in the voltage setting circuit 1, by adjusting the values of the resistors R1 and R2, the voltage Vx that is the divided voltage has a voltage difference between the power supply voltage Vdd and the gate of the MOS transistor M2 and the conductive terminal 7y. It is adjusted to be a value larger than the threshold voltage Vth and lower than the breakdown voltage VB of the MOS transistor M2. That is, the divided voltage Vx is set to a value that satisfies the relationship of 0 ≦ Vx <Vdd−Vth and Vdd−Vx <VB.

このように、ＭＯＳトランジスタＭ２がＯＮすると、ＭＯＳトランジスタＭ１の導電端子７ｘ及びバックゲートには、電源電圧ＶｄｄからＭＯＳトランジスタＭ２のＯＮ抵抗により電圧降下した分の電圧が印加される。又、ＭＯＳトランジスタＭ１がオペアンプＡにより制御されて、ＭＯＳトランジスタＭ１の導電端子６ｘに現れる電圧を出力電圧として出力する。又、オペアンプＡでは、ＭＯＳトランジスタＭ１の導電端子６ｘに現れる電圧を基準電圧Ｖｒｅｆと比較することで、一定となるようにＭＯＳトランジスタＭ１のゲート電圧を制御する。   Thus, when the MOS transistor M2 is turned on, a voltage corresponding to a voltage drop from the power supply voltage Vdd by the ON resistance of the MOS transistor M2 is applied to the conductive terminal 7x and the back gate of the MOS transistor M1. Further, the MOS transistor M1 is controlled by the operational amplifier A, and a voltage appearing at the conductive terminal 6x of the MOS transistor M1 is output as an output voltage. In the operational amplifier A, the gate voltage of the MOS transistor M1 is controlled to be constant by comparing the voltage appearing at the conductive terminal 6x of the MOS transistor M1 with the reference voltage Vref.

このとき、ＭＯＳトランジスタＭ２のＯＮ抵抗は、０．１[Ω]より低い値にしておけば、ＭＯＳトランジスタＭ２に５[Ａ]のような大きな電流が流れても、その電圧降下が０．５[Ｖ]であり、図４（ａ）におけるダイオードＤａによる電圧降下０．７[Ｖ]よりも低い値とすることができる。   At this time, if the ON resistance of the MOS transistor M2 is set to a value lower than 0.1 [Ω], even if a large current such as 5 [A] flows through the MOS transistor M2, the voltage drop is reduced to 0.5. [V], which can be lower than the voltage drop 0.7 [V] due to the diode Da in FIG.

又、このような半導体集積回路装置に誤って逆バイアスが印加され、電源電圧Ｖｄｄが接地電圧より低くなったとしても、まず、逆流防止素子２であるダイオードＤ１により電流が流れないため、電圧設定回路１に接地電圧側から電流が流れ込むことが防がれる。よって、抵抗Ｒ１，Ｒ２の接続ノードには接地電圧が現れて、この接地電圧が電圧設定回路１からの出力電圧Ｖｘとして、ＭＯＳトランジスタＭ２のゲートに与えられる。   Even if a reverse bias is erroneously applied to such a semiconductor integrated circuit device and the power supply voltage Vdd becomes lower than the ground voltage, first, no current flows through the diode D1 as the backflow prevention element 2, so that the voltage setting is performed. It is possible to prevent the current from flowing into the circuit 1 from the ground voltage side. Therefore, a ground voltage appears at the connection node of the resistors R1 and R2, and this ground voltage is applied to the gate of the MOS transistor M2 as the output voltage Vx from the voltage setting circuit 1.

このとき、ＭＯＳトランジスタＭ２の導電端子６ｙにも逆バイアスのため接地電圧より低い電圧となる電源電圧Ｖｄｄが印加されることとなる。そのため、ＭＯＳトランジスタＭ１，Ｍ２はＯＦＦのままとなる。このとき、ＭＯＳトランジスタＭ１に寄生ダイオードＤｘ１が構成されているが、ＭＯＳトランジスタＭ２に構成される寄生ダイオードＤｘ２によりＭＯＳトランジスタＭ２の導電端子７ｙ及びバックゲートから導電端子６ｙへ流れ込むことが防がれている。よって、寄生ダイオードＤｘ１を流れる逆流電流が防がれる。   At this time, the power supply voltage Vdd which is lower than the ground voltage is applied to the conductive terminal 6y of the MOS transistor M2 due to the reverse bias. Therefore, the MOS transistors M1 and M2 remain OFF. At this time, the parasitic diode Dx1 is configured in the MOS transistor M1, but the parasitic diode Dx2 configured in the MOS transistor M2 prevents the MOS transistor M2 from flowing from the conductive terminal 7y and the back gate to the conductive terminal 6y. Yes. Therefore, the backflow current flowing through the parasitic diode Dx1 is prevented.

このように構成することによって、ＭＯＳトランジスタＭ２を動作させるとき、ＭＯＳトランジスタＭ２の導電端子６ｙに印加する電源電圧の電圧値に応じて、ＭＯＳトランジスタＭ２が耐圧破壊されないような電圧がゲートに印加されるように、電圧設定回路１で調整することができる。即ち、ＭＯＳトランジスタＭ２の導電端子６ｙに印加する電源電圧が高くなるときは、ＭＯＳトランジスタＭ２のゲートに与える電圧が高くなるように、又、ＭＯＳトランジスタＭ２の導電端子６ｙに印加する電源電圧が低くなるときは、ＭＯＳトランジスタＭ２のゲートに与える電圧も低くなるように、電圧設定回路１で調整される。   With this configuration, when the MOS transistor M2 is operated, a voltage is applied to the gate such that the MOS transistor M2 is not broken down in accordance with the voltage value of the power supply voltage applied to the conductive terminal 6y of the MOS transistor M2. As described above, the voltage setting circuit 1 can adjust. That is, when the power supply voltage applied to the conductive terminal 6y of the MOS transistor M2 increases, the voltage applied to the gate of the MOS transistor M2 increases, and the power supply voltage applied to the conductive terminal 6y of the MOS transistor M2 decreases. If so, the voltage setting circuit 1 adjusts the voltage to be applied to the gate of the MOS transistor M2.

尚、本実施形態では、逆流防止素子２に印加する電圧とＭＯＳトランジスタＭ２の導電端子６ｙに印加する電圧値を同一の電圧値Ｖｄｄとしたが、同じ電源電圧である必要はなく、逆流防止素子２に印加する電圧とＭＯＳトランジスタＭ２の導電端子６ｙに印加する電圧を異なる電圧値としても構わない。このとき、同一の電源電圧Ｖｄｄが供給されるとともに、電圧Ｖｄｄ１，Ｖｄｄ２に変圧して逆流防止素子２のアノード側及びＭＯＳトランジスタＭ２の導電端子６ｙそれぞれに供給するレギュレータを設けるようにしても構わない。又、逆流防止素子２として、複数のダイオード、又は、ダイオード接続されたトランジスタにより構成しても構わない。   In this embodiment, the voltage applied to the backflow prevention element 2 and the voltage value applied to the conductive terminal 6y of the MOS transistor M2 are the same voltage value Vdd. However, the same power supply voltage is not required, and the backflow prevention element The voltage applied to 2 and the voltage applied to the conductive terminal 6y of the MOS transistor M2 may have different voltage values. At this time, the same power supply voltage Vdd may be supplied, and a regulator may be provided that transforms the voltages to Vdd1 and Vdd2 and supplies them to the anode side of the backflow prevention element 2 and the conductive terminal 6y of the MOS transistor M2. . Further, the backflow prevention element 2 may be constituted by a plurality of diodes or diode-connected transistors.

は、本発明の半導体集積回路装置の構成を示すブロック回路図である。These are block circuit diagrams which show the structure of the semiconductor integrated circuit device of this invention. は、図１の詳細な回路構成例を示す回路図である。FIG. 2 is a circuit diagram showing a detailed circuit configuration example of FIG. 1. は、ＤＭＯＳ構造のＭＯＳトランジスタの構成を示す断面図である。These are sectional drawings which show the structure of the MOS transistor of a DMOS structure. は、従来の半導体集積回路装置の構成を示す図である。These are figures which show the structure of the conventional semiconductor integrated circuit device.

符号の説明Explanation of symbols

１ 電圧設定回路
２ 逆流防止素子 1 Voltage setting circuit 2 Backflow prevention element

Claims (6)

第１バックゲート領域と、ソース領域及びドレイン領域の一方となるとともに前記第１バックゲート領域と接続される第１導電領域と、ソース領域及びドレイン領域の他方となる第２導電領域と、を有する第１ＭＯＳトランジスタを備える半導体集積回路装置において、
前記第１ＭＯＳトランジスタの前記第１バックゲート領域と前記第１導電領域に接続された第２バックゲート領域と、ソース領域及びドレイン領域の一方となるとともに前記第２バックゲート領域と接続される第３導電領域と、ソース領域及びドレイン領域の他方となるとともに第１直流電圧が印加される第４導電領域と、を有する第２ＭＯＳトランジスタと、
該第２ＭＯＳトランジスタのゲートに供給する第２直流電圧を設定する電圧設定回路と、
前記第１直流電圧と同一の電源電圧より生成される第３直流電圧が印加されるとともに、前記電圧設定回路に接続して前記電圧設定回路における逆流を阻止する逆流防止素子と、
を備え、
前記電圧設定回路において、前記第１直流電圧を基準として前記第２ＭＯＳトランジスタの耐圧範囲内となる直流電圧を、前記第２直流電圧とすることを特徴とする半導体集積回路装置。 A first back gate region; a first conductive region that is one of a source region and a drain region and connected to the first back gate region; and a second conductive region that is the other of the source region and the drain region. In a semiconductor integrated circuit device comprising a first MOS transistor,
A third back gate region connected to the first back gate region of the first MOS transistor, a second back gate region connected to the first conductive region, and one of a source region and a drain region and connected to the second back gate region. A second MOS transistor having a conductive region and a fourth conductive region which is the other of the source region and the drain region and to which the first DC voltage is applied;
A voltage setting circuit for setting a second DC voltage supplied to the gate of the second MOS transistor;
A third direct current voltage generated from the same power supply voltage as the first direct current voltage is applied, and a backflow preventing element connected to the voltage setting circuit to prevent backflow in the voltage setting circuit;
With
2. The semiconductor integrated circuit device according to claim 1, wherein in the voltage setting circuit, a DC voltage that falls within a withstand voltage range of the second MOS transistor with reference to the first DC voltage is the second DC voltage. 前記第１ＭＯＳトランジスタ及び前記第２ＭＯＳトランジスタが同一極性であることを特徴とする請求項１に記載の半導体集積回路装置。   2. The semiconductor integrated circuit device according to claim 1, wherein the first MOS transistor and the second MOS transistor have the same polarity. 前記逆流防止素子がダイオードであることを特徴とする請求項１又は請求項２に記載の半導体集積回路装置。   The semiconductor integrated circuit device according to claim 1, wherein the backflow prevention element is a diode. 前記電圧設定回路が分圧抵抗により構成されることを特徴とする請求項１〜請求項３のいずれかに記載の半導体集積回路装置。   4. The semiconductor integrated circuit device according to claim 1, wherein the voltage setting circuit includes a voltage dividing resistor. 前記第１ＭＯＳトランジスタの前記第２導電領域の電圧と基準電圧を比較した値を前記第１ＭＯＳトランジスタのゲートに出力する帰還回路を備えることを特徴とする請求項１〜請求項４のいずれかに記載の半導体集積回路装置。   5. The feedback circuit according to claim 1, further comprising a feedback circuit that outputs a value obtained by comparing a voltage of the second conductive region of the first MOS transistor with a reference voltage to a gate of the first MOS transistor. Semiconductor integrated circuit device. 前記第１ＭＯＳトランジスタの前記第２導電領域に、負荷が接続されるとともに、
前記第１ＭＯＳトランジスタの前記第１バックゲート領域と第２導電領域との間に第１寄生ダイオードが構成され、前記第２ＭＯＳトランジスタの前記第２バックゲート領域と第４導電領域との間に第２寄生ダイオードが構成されることを特徴とする請求項１〜請求項５のいずれかに記載の半導体集積回路装置。 A load is connected to the second conductive region of the first MOS transistor,
A first parasitic diode is formed between the first back gate region and the second conductive region of the first MOS transistor, and a second parasitic diode is formed between the second back gate region and the fourth conductive region of the second MOS transistor. 6. The semiconductor integrated circuit device according to claim 1, further comprising a parasitic diode.
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