JPH1187628A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

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Publication number
JPH1187628A
JPH1187628A JP25018597A JP25018597A JPH1187628A JP H1187628 A JPH1187628 A JP H1187628A JP 25018597 A JP25018597 A JP 25018597A JP 25018597 A JP25018597 A JP 25018597A JP H1187628 A JPH1187628 A JP H1187628A
Authority
JP
Japan
Prior art keywords
reference voltage
circuit
temperature
constant
generating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25018597A
Other languages
Japanese (ja)
Inventor
Hiroyasu Kibi
裕恭 吉備
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP25018597A priority Critical patent/JPH1187628A/en
Publication of JPH1187628A publication Critical patent/JPH1187628A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a reference voltage generating circuit, wherein a stable reference voltage is generated without increasing the circuit scale and power consumption, etc. SOLUTION: In a semiconductor integrated circuit having a built-in reference voltage generating circuit, a constant current part 2 (junction gate type transistor) and a constant voltage part 22 (constant voltage diode) of the reference voltage generating circuit are constituted, using an SOI(silicon-on-insulator) device. Further, a volume-occupying P-type or N-type semiconductor region (11-16) which constitute the SOI device is kept to such volume as of constant temperature through the operation current of the reference voltage generating circuit.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、基準電圧発生回路
を内蔵した半導体集積回路に関するものである。
The present invention relates to a semiconductor integrated circuit having a built-in reference voltage generating circuit.

【0002】[0002]

【従来の技術】基準電圧発生回路は、図3や、図4及び
図5に示すように、+Vcc電極N1とGND電極N3
との間に電源を接続して、Vref電極N2から安定な
基準電圧を発生させることを目的としている。そのた
め、電源電圧の変動による影響を受けないようにするた
め、基本的な構造は、図3のように、定電流部21から
定電圧部22へ定電流Izを供給する回路構成になって
いる。
2. Description of the Related Art As shown in FIGS. 3, 4 and 5, a reference voltage generating circuit includes a + Vcc electrode N1 and a GND electrode N3.
And to generate a stable reference voltage from the Vref electrode N2. Therefore, in order not to be affected by the fluctuation of the power supply voltage, the basic structure has a circuit configuration for supplying the constant current Iz from the constant current unit 21 to the constant voltage unit 22 as shown in FIG. .

【0003】さらに、この回路は、基準電圧の熱的安定
性も問題になってくるため、通常、以下のような対策が
なされている。
Further, in this circuit, since the thermal stability of the reference voltage becomes a problem, the following countermeasures are usually taken.

【0004】第1の方法は、温度補償法を用いたもの
で、図4及び図5のように、温度ドリフト源(トランジ
スタQ1、Q1’、Q2’、Q3’、ダイオードDi
1、Di2、ツェナーダイオードDz、抵抗R1、R
2、R1’、R2’、R3’)の温度係数が互いに打ち
消しあってゼロとなるように回路を構成しているもので
ある。
The first method uses a temperature compensation method. As shown in FIGS. 4 and 5, a temperature drift source (transistors Q1, Q1 ', Q2', Q3 ', diode Di) is used.
1, Di2, Zener diode Dz, resistors R1, R
2, R1 ', R2', R3 ') are configured so that the temperature coefficients cancel each other and become zero.

【0005】第2の方法は、温度管理によるもので、基
準電圧発生回路の近傍に、感熱素子と発熱素子とを置
き、発熱量(電力)をコントロールする温度制御回路に
よって基板温度を一定に保つものである。
The second method is based on temperature management, in which a thermosensitive element and a heating element are placed in the vicinity of a reference voltage generating circuit, and the substrate temperature is kept constant by a temperature control circuit for controlling the amount of generated heat (power). Things.

【0006】例えば、特開昭55−74166号公報に
示されるものにおいては、図6に示すように、半導体素
子41の温度を一定に保つために、半導体素子41内に
温度検出用の感温素子42が組み込まれ、半導体素子4
1の直下に設けられた発熱抵抗膜43が導電体膜44、
44を介して、上記感温素子42よりの出力によって制
御される直流制御電源45に接続されている。感温素子
42からの信号により、直流制御電源45が発熱抵抗膜
43に供給する電流を制御して、半導体素子41の温度
を一定に保つことができるものである。
For example, in Japanese Unexamined Patent Publication No. 55-74166, as shown in FIG. 6, in order to keep the temperature of the semiconductor element 41 constant, a temperature sensing temperature sensing element is provided in the semiconductor element 41. The element 42 is incorporated and the semiconductor element 4
1, a heat-generating resistor film 43 provided immediately below
Via 44, it is connected to a DC control power supply 45 controlled by the output from the temperature sensing element 42. The DC control power supply 45 controls the current supplied to the heating resistor film 43 by a signal from the temperature sensing element 42, so that the temperature of the semiconductor element 41 can be kept constant.

【0007】また、特開平5−235127号公報に示
されるものにおいては、図7に示すように、基板上に形
成された絶縁層上にある温度制御対象の能動素子を有す
るSOIデバイス51の温度を一定に保つために、該S
OIデバイス51上に表面パッシベーション膜を介して
第1薄膜52と第2薄膜53とが積層され、接合層が形
成されている。また、上記第1薄膜52と第2薄膜53
は、起電力検出回路54と電流制御回路55へ、それぞ
れ接続されていて、起電力検出回路54が上記接合層の
ゼーベック効果により温度検出を行い、それに基づいて
電流制御回路55が供給電流を制御して、上記接合層の
ペルチェ効果による発熱若しくは吸熱により温度制御を
行っている。
In Japanese Unexamined Patent Publication No. 5-235127, as shown in FIG. 7, the temperature of an SOI device 51 having an active element to be temperature-controlled on an insulating layer formed on a substrate is disclosed. In order to keep
A first thin film 52 and a second thin film 53 are stacked on an OI device 51 via a surface passivation film, and a bonding layer is formed. Also, the first thin film 52 and the second thin film 53
Are connected to an electromotive force detection circuit 54 and a current control circuit 55, respectively. The electromotive force detection circuit 54 detects the temperature by the Seebeck effect of the bonding layer, and the current control circuit 55 controls the supply current based on the detected temperature. The temperature is controlled by heat generation or heat absorption by the Peltier effect of the bonding layer.

【0008】[0008]

【発明が解決しようとする課題】上記第1の方法による
従来技術では、基準電圧発生回路内の温度ドリフトを打
ち消すために、温度補償回路を追加する必要があり、回
路規模の増大を招いていた。
In the prior art according to the first method, it is necessary to add a temperature compensating circuit in order to cancel a temperature drift in the reference voltage generating circuit, resulting in an increase in circuit scale. .

【0009】また、上記第2の方法による従来技術で
は、回路素子の動作中の温度を一定とするために、温度
ドリフト低減対象とする回路付近の基板上に、発熱素子
や感温素子を置き、新たに、温度制御用回路と温度制御
用電力(基板加熱のための消費電力)とが必要となっ
た。更に、基準電圧発生回路内部は、常時、定電流Iz
が流れるため、動作中の変動(発生熱量)は無いが、実
際の温度ドリフト原因としては、内的な要因(基準電圧
発生回路内の変動等)より、外的な要因(他の回路内の
温度変動による影響等)もあった。
In the prior art according to the second method, in order to keep the temperature during operation of the circuit element constant, a heating element or a temperature-sensitive element is placed on a substrate near a circuit to be subjected to a temperature drift reduction. In addition, a temperature control circuit and a temperature control power (power consumption for heating the substrate) are newly required. Further, the reference voltage generating circuit always has a constant current Iz
Flow, there is no fluctuation during operation (generated heat), but the actual cause of the temperature drift is an external factor (variation in the reference voltage generation circuit, etc.) rather than an external factor (fluctuation in other circuits). Temperature fluctuations).

【0010】本発明は、上記従来の問題点を解決すべく
なされたものである。
The present invention has been made to solve the above-mentioned conventional problems.

【0011】[0011]

【課題を解決するための手段】本発明の半導体集積回路
は、基準電圧発生回路を内蔵した半導体集積回路に於い
て、上記基準電圧発生回路の温度ドリフト低減対象部分
をSOI(Silicon On Insulato
r)デバイスで構成して成ることを特徴とするものであ
る。
According to a semiconductor integrated circuit of the present invention, in a semiconductor integrated circuit having a built-in reference voltage generating circuit, a portion to be reduced in temperature drift of the reference voltage generating circuit is subjected to SOI (Silicon On Insulator).
r) It is characterized by comprising a device.

【0012】更に、本発明の半導体集積回路は、上記S
OIデバイスを構成するP型又はN型の半導体領域の占
める体積が、上記基準電圧発生回路の動作電流により一
定温度に保たれる体積に設計されていることを特徴とす
るものである。
Further, in the semiconductor integrated circuit according to the present invention,
The OI device is characterized in that the volume occupied by the P-type or N-type semiconductor region constituting the OI device is designed to be a volume maintained at a constant temperature by the operating current of the reference voltage generating circuit.

【0013】かかる、本発明の半導体集積回路によれ
ば、SOIデバイスの特性により、外部からの温度変化
の影響を受けにくく、また、内部からの一様加熱による
保温効果と一定な発生熱量(定電流による)のため、動
作中の温度を安定に保つことができるものである。
[0013] According to the semiconductor integrated circuit of the present invention, the characteristics of the SOI device make it less susceptible to external temperature changes, and also provide a heat retention effect due to uniform heating from the inside and a constant amount of heat generated (constant). Therefore, the temperature during operation can be kept stable.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して詳細に説明する。
Embodiments of the present invention will be described below in detail with reference to the drawings.

【0015】図1は、本発明の一実施形態に係る基準電
圧発生回路の断面構造図である。等価回路的には、図3
に示す回路と同一である。
FIG. 1 is a sectional structural view of a reference voltage generating circuit according to one embodiment of the present invention. As an equivalent circuit, FIG.
Is the same as the circuit shown in FIG.

【0016】定電流部21と定電圧部22とは、動作機
能が同一であれば、他の構造のものでもよいが、ここで
は、説明を容易にするため、接合ゲート型FET(定電
流部21)と定電圧ダイオード(定電圧部22)の場合
を例にとり説明する。
The constant current section 21 and the constant voltage section 22 may have other structures as long as they have the same operation function. However, in order to simplify the description, a junction gate type FET (constant current section) is used here. 21) and a constant voltage diode (constant voltage section 22).

【0017】この第1の実施形態は、温度ドリフト低減
対象が、基準電圧発生回路の定電流部21と定電圧部2
2の双方であるものである。
In the first embodiment, the temperature drift reduction targets are the constant current section 21 and the constant voltage section 2 of the reference voltage generating circuit.
The two are both.

【0018】図1において、ゲートとなるP+領域11
と、チャネルとなるN領域12と、ドレインとなるN+
領域13と、ソースとなるN+領域14とで、定電流部
21である接合ゲート型FETを形成し、カソードとな
るN+領域15と、アノードとなるP+領域16とで、定
電圧部22である定電圧ダイオードを形成している。
In FIG. 1, a P + region 11 serving as a gate is provided.
, N region 12 serving as a channel, and N + serving as a drain
A junction gate type FET which is a constant current unit 21 is formed by the region 13 and the N + region 14 serving as a source, and a N + region 15 serving as a cathode and a P + region 16 serving as an anode form a constant voltage unit. A constant voltage diode 22 is formed.

【0019】また、定電流部21のソースとなるN+
域14と、定電圧部22のカソードとなるN+領域15
とは、直接接触していて、定電流部21と定電圧部22
との間で熱が移動しやすくなっており、動作電流Izに
より、上記両部の温度が一定温度に保たれるように、上
記P型及びN型の半導体領域(11〜16)の体積は設
計されている。そして、この上には、電極若しくは図3
の等価回路のように配線する配線を構成する導電性膜1
7が形成されており、周囲が絶縁膜18で覆われてい
る。
An N + region 14 serving as a source of the constant current unit 21 and an N + region 15 serving as a cathode of the constant voltage unit 22
Are in direct contact with each other, and the constant current section 21 and the constant voltage section 22
And the volume of the P-type and N-type semiconductor regions (11 to 16) is adjusted so that the temperature of the two portions is maintained at a constant temperature by the operating current Iz. Designed. On top of this, an electrode or FIG.
Conductive film 1 constituting a wiring to be wired like an equivalent circuit of
7 are formed, and the periphery is covered with an insulating film 18.

【0020】+Vcc電極N1と、GND電極N3との
間に電源を接続して発生する回路内の熱は、周囲が絶縁
膜18で覆われ、かつ、接触している導電性膜17を介
して行われる熱の伝導は少ないために、外部との熱の出
入りがほとんど無く、P型若しくはN型の半導体領域
(11〜16)中に拡散される。更に、定電流動作によ
り、基準電圧発生回路内の発生熱量は一定であること
と、P型若しくはN型の半導体領域(11〜16)の占
める体積が、動作電流により一定温度に保たれるように
設計されていることにより、回路素子の動作中の温度は
安定する。
The heat in the circuit generated by connecting a power supply between the + Vcc electrode N1 and the GND electrode N3 is transmitted through the conductive film 17 which is covered with the insulating film 18 and is in contact therewith. Since the conducted heat conduction is small, heat hardly enters and exits from outside and is diffused into the P-type or N-type semiconductor regions (11 to 16). Further, by the constant current operation, the amount of heat generated in the reference voltage generation circuit is constant, and the volume occupied by the P-type or N-type semiconductor regions (11 to 16) is maintained at a constant temperature by the operation current. , The temperature during operation of the circuit element is stabilized.

【0021】ただし、P型若しくはN型の半導体領域
(11〜16)の占める体積は、発生熱量と拡散熱量が
ほぼ平衡し、SOIデバイスの動作温度が周囲より高い
が、許容温度は超えない程度に設計され、また、基準電
圧発生回路は、大電流が変化するような部分から離さ
れ、温度変動の少ない基板上の位置にあるものとする。
また、基準電圧を参照する回路の入力インピーダンスは
高く、この基準電圧発生回路に影響(動作電流)を与え
ないものとする。
However, the volume occupied by the P-type or N-type semiconductor regions (11 to 16) is such that the amount of generated heat and the amount of diffused heat are substantially balanced, and the operating temperature of the SOI device is higher than the ambient temperature but does not exceed the allowable temperature. The reference voltage generating circuit is separated from a portion where a large current changes, and is located at a position on the substrate where temperature fluctuation is small.
Also, the input impedance of the circuit that refers to the reference voltage is high, and it does not affect the reference voltage generation circuit (operating current).

【0022】このため、基準電圧発生回路の定電流部2
1と定電圧部22の温度ドリフトは低減し、Vref電
極N2から安定な基準電圧を発生させることができる。
Therefore, the constant current section 2 of the reference voltage generating circuit
1 and the temperature drift of the constant voltage section 22 are reduced, and a stable reference voltage can be generated from the Vref electrode N2.

【0023】次に、本発明の第2の実施形態について説
明する。
Next, a second embodiment of the present invention will be described.

【0024】図2は、本発明の第2の実施形態に係る基
準電圧発生回路の断面構造図である。等価回路的には、
図3に示す回路と同一である。
FIG. 2 is a sectional structural view of a reference voltage generating circuit according to a second embodiment of the present invention. In terms of an equivalent circuit,
This is the same as the circuit shown in FIG.

【0025】定電流部21と定電圧部22とは、動作機
能が同一であれば、他の構造のものでもよいが、ここで
は、説明を容易にするため、接合ゲート型FET(定電
流部21)と定電圧ダイオード(定電圧部22)の場合
を例にとり説明する。
The constant current section 21 and the constant voltage section 22 may have other structures as long as they have the same operation function. However, in order to simplify the description, a junction gate type FET (constant current section) is used here. 21) and a constant voltage diode (constant voltage section 22).

【0026】この第2の実施形態は、基準電圧発生回路
の定電圧部22のみを温度ドリフト低減対象としている
ものである。
In the second embodiment, only the constant voltage section 22 of the reference voltage generating circuit is targeted for temperature drift reduction.

【0027】図2において、ゲートとなるP+領域1
1’と、チャネルとなるN領域12’と、ドレインとな
るN+領域13’と、ソースとなるN+領域14’とで、
定電流部21である接合ゲート型FETを形成し、カソ
ードとなるN+領域15’と、アノードとなるP+領域1
6’とで、定電圧部22である定電圧ダイオードを形成
している。
In FIG. 2, P + region 1 serving as a gate
1 ′, an N region 12 ′ serving as a channel, an N + region 13 ′ serving as a drain, and an N + region 14 ′ serving as a source.
A junction gate type FET which is a constant current portion 21 is formed, and an N + region 15 ′ serving as a cathode and a P + region 1 serving as an anode are formed.
6 ′ form a constant voltage diode which is the constant voltage section 22.

【0028】また、チャネルとなるN領域12’と、カ
ソードとなるN+領域15’とは、絶縁膜18’によっ
て分離され、接触している導電性膜17’を介して行わ
れる熱の伝導は少ないので、定電流部21と定電圧部2
2との間で熱の移動は無く、また、温度ドリフト低減対
象である定電圧部22のN+領域15’とP+領域16’
の占める体積は、動作電流Izにより一定の温度に保た
れるように設計されている。そして、この上には、電極
若しくは図3の等価回路となるように配線する配線を形
成する導電性膜17’が形成され、周囲を絶縁膜18’
で覆っているために、外部との熱の出入りがほとんど無
い。
Further, the N region 12 'serving as a channel and the N + region 15' serving as a cathode are separated by an insulating film 18 ', and heat conduction performed through a conductive film 17' in contact therewith. Is small, the constant current unit 21 and the constant voltage unit 2
2 does not transfer heat, and the N + region 15 ′ and the P + region 16 ′ of the constant voltage unit 22 to be reduced in temperature drift.
Is designed to be kept at a constant temperature by the operating current Iz. Then, a conductive film 17 'for forming an electrode or a wiring for wiring so as to form the equivalent circuit of FIG. 3 is formed thereon, and the periphery thereof is an insulating film 18'.
Because it is covered with heat, there is almost no ingress and egress of heat with the outside.

【0029】+Vcc電極N1とGND電極N3との間
に電源を接続すると、上記第1の実施形態と同様な理由
により、基準電圧発生回路の定電圧部22の温度ドリフ
トが低減されるので、Vref電極N2から安定な基準
電圧が得られるものである。
When a power supply is connected between the + Vcc electrode N1 and the GND electrode N3, the temperature drift of the constant voltage section 22 of the reference voltage generating circuit is reduced for the same reason as in the first embodiment, so that Vref A stable reference voltage can be obtained from the electrode N2.

【0030】なお、図2に示す定電流部21は、専用の
定電流源であるが、専用の定電流源が無く、他の回路の
定電流源を共用する構成としてもよいものである。
Although the constant current section 21 shown in FIG. 2 is a dedicated constant current source, it may have no dedicated constant current source and may share a constant current source of another circuit.

【0031】[0031]

【発明の効果】以上詳細に説明したように、本発明の半
導体集積回路は、基準電圧発生回路を内蔵した半導体集
積回路に於いて、上記基準電圧発生回路の温度ドリフト
低減対象部分をSOI(Silicon On Ins
ulator)デバイスで構成して成ることを特徴とす
るものであり、更に、本発明の半導体集積回路は、上記
SOIデバイスを構成するP型又はN型の半導体領域の
占める体積が、上記基準電圧発生回路の動作電流により
一定温度に保たれる体積に設計されていることを特徴と
するものであり、かかる本発明の半導体集積回路によれ
ば、容易に、動作中の温度が安定な基準電圧発生回路を
構成することができ、回路規模の縮小化、小型化及び低
消費電力化を達成することができるものである。
As described above in detail, in the semiconductor integrated circuit of the present invention, in a semiconductor integrated circuit having a built-in reference voltage generating circuit, a portion of the reference voltage generating circuit to be subjected to temperature drift reduction is SOI (Silicon). On Ins
Further, in the semiconductor integrated circuit according to the present invention, the volume occupied by the P-type or N-type semiconductor region constituting the SOI device is the same as that of the reference voltage generation. The semiconductor integrated circuit of the present invention is characterized in that it is designed to have a volume that is maintained at a constant temperature by the operating current of the circuit. A circuit can be formed, and a reduction in circuit size, size, and power consumption can be achieved.

【0032】なお、従来の温度補償法を用いた基準電圧
発生回路に本発明を適用すれば、更に安定した出力が得
られる基準電圧発生回路を構成することができるもので
ある。
When the present invention is applied to a reference voltage generating circuit using a conventional temperature compensation method, a reference voltage generating circuit that can obtain a more stable output can be constructed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係る基準電圧発生回路の
断面構造図である。
FIG. 1 is a sectional structural view of a reference voltage generating circuit according to an embodiment of the present invention.

【図2】本発明の他の実施形態に係る基準電圧発生回路
の断面構造図である。
FIG. 2 is a sectional structural view of a reference voltage generating circuit according to another embodiment of the present invention.

【図3】一般的な基準電圧発生回路の回路構成図であ
る。
FIG. 3 is a circuit configuration diagram of a general reference voltage generation circuit.

【図4】温度補償回路を用いた基準電圧発生回路の回路
構成図である。
FIG. 4 is a circuit configuration diagram of a reference voltage generation circuit using a temperature compensation circuit.

【図5】温度補償回路を用いた他の基準電圧発生回路の
回路構成図である。
FIG. 5 is a circuit configuration diagram of another reference voltage generation circuit using a temperature compensation circuit.

【図6】従来の温度管理方法の説明に供する図である。FIG. 6 is a diagram provided for explanation of a conventional temperature management method.

【図7】従来の他の温度管理方法の説明に供する図であ
る。
FIG. 7 is a diagram provided for explanation of another conventional temperature management method.

【符号の説明】[Explanation of symbols]

11、11’ P+領域(ゲート) 12、12’ N領域(チャネル) 13、13’ N+領域(ドレイン) 14、14’ N+領域(ソース) 15、15’ N+領域(カソード) 16、16’ P+領域(アノード) 17、17’ 導電性膜 18、18’ 絶縁膜 21 定電流部 22 定電圧部11, 11 'P + region (gate) 12, 12' N region (channel) 13, 13 'N + region (drain) 14, 14' N + region (source) 15, 15 'N + region (cathode) 16 , 16 'P + region (anode) 17, 17' conductive film 18, 18 'insulating film 21 constant current part 22 constant voltage part

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基準電圧発生回路を内蔵した半導体集積
回路に於いて、上記基準電圧発生回路の温度ドリフト低
減対象部分をSOI(Silicon OnInsul
ator)デバイスで構成して成ることを特徴とする半
導体集積回路。
In a semiconductor integrated circuit having a built-in reference voltage generation circuit, a portion to be reduced in temperature drift of the reference voltage generation circuit is formed by SOI (Silicon On Insul).
(a) A semiconductor integrated circuit comprising a device.
【請求項2】 上記SOIデバイスを構成するP型又は
N型の半導体領域の占める体積が、上記基準電圧発生回
路の動作電流により一定温度に保たれる体積に設計され
ていることを特徴とする、請求項1に記載の半導体集積
回路。
2. The semiconductor device according to claim 1, wherein a volume occupied by a P-type or N-type semiconductor region constituting said SOI device is designed to be a volume maintained at a constant temperature by an operation current of said reference voltage generation circuit. The semiconductor integrated circuit according to claim 1.
JP25018597A 1997-09-16 1997-09-16 Semiconductor integrated circuit Pending JPH1187628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25018597A JPH1187628A (en) 1997-09-16 1997-09-16 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25018597A JPH1187628A (en) 1997-09-16 1997-09-16 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH1187628A true JPH1187628A (en) 1999-03-30

Family

ID=17204087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25018597A Pending JPH1187628A (en) 1997-09-16 1997-09-16 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH1187628A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6967378B2 (en) 2003-02-27 2005-11-22 Rohm Co., Ltd. Semiconductor integrated circuit device configured to prevent the generation of a reverse current in a MOS transistor
JP2006157937A (en) * 2005-12-13 2006-06-15 Rohm Co Ltd Semiconductor integrated circuit device
JP2013030091A (en) * 2011-07-29 2013-02-07 Mitsubishi Electric Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6967378B2 (en) 2003-02-27 2005-11-22 Rohm Co., Ltd. Semiconductor integrated circuit device configured to prevent the generation of a reverse current in a MOS transistor
JP2006157937A (en) * 2005-12-13 2006-06-15 Rohm Co Ltd Semiconductor integrated circuit device
JP2013030091A (en) * 2011-07-29 2013-02-07 Mitsubishi Electric Corp Semiconductor device

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