CN110058140B - Go up electric voltage detection circuitry, electron device and thing networking device - Google Patents
Go up electric voltage detection circuitry, electron device and thing networking device Download PDFInfo
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- CN110058140B CN110058140B CN201810048419.2A CN201810048419A CN110058140B CN 110058140 B CN110058140 B CN 110058140B CN 201810048419 A CN201810048419 A CN 201810048419A CN 110058140 B CN110058140 B CN 110058140B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
A go up electric voltage detection circuitry, electron device and thing networking equipment, go up electric voltage detection circuitry includes: the detection unit is suitable for detecting the electrifying voltage, and the output end of the detection unit generates a breakover voltage in response to the electrifying voltage being greater than the starting voltage; the impedance value between the first end and the second end of the non-resistance load unit is controlled by a first control voltage, and the non-resistance load unit is connected in series with an electric path from the power-on voltage to the reference ground through the detection unit; the feedback control unit is suitable for generating a first control voltage according to the breakover voltage; wherein, in response to the power-on voltage being less than or equal to the turn-over voltage, the first control voltage controls the impedance value to be a first impedance so that the turn-on voltage is a first logic level; in response to the power-up voltage being greater than the flipping voltage, the first control voltage controls the impedance value to be a second impedance that is greater than the first impedance so that the turn-on voltage is at a second logic level. By adopting the scheme, the power consumption of the power-on voltage detection circuit can be reduced, and the reliability of the circuit is improved.
Description
Technical Field
The invention relates to the field of electronic circuit design, in particular to an electrifying voltage detection circuit, an electronic device and Internet of things equipment.
Background
In an Integrated Circuit (IC), it is generally required to detect a power-on voltage, and the IC is particularly suitable for a situation where the IC operates in a multi-power mode.
In the prior art, a voltage comparator can be adopted to detect the power-on voltage so as to determine which power supply voltage range the power-on voltage is in; for example, a reference voltage generated by a bandgap reference source may be connected to one input terminal of a voltage comparator, the power-on voltage may be connected to the other input terminal, and the output logic of the voltage comparator may determine the power-on voltage range.
However, the prior art solution needs to additionally introduce a reference voltage, which may introduce additional circuit reliability problems, and also needs to additionally pay more circuit area and power consumption. Meanwhile, low power consumption design becomes the mainstream of electronic chip and electronic product design. Therefore, when detecting the power-on voltage, it is necessary to improve the stability of the detection circuit and meet the requirement of low power consumption of the detection circuit.
Disclosure of Invention
The invention solves the technical problem of how to improve the stability of the detection circuit and meet the low power consumption requirement of the detection circuit when detecting the electrifying voltage.
In order to solve the above technical problem, an embodiment of the present invention provides a power-on voltage detection circuit, where the power-on voltage detection circuit includes: the detection unit is suitable for detecting the power-on voltage received by the power port, and in response to the fact that the power-on voltage is larger than the starting voltage, the output end of the detection unit generates a conducting voltage; the non-resistance load unit is coupled with the output end of the detection unit, the control end of the non-resistance load unit is connected with a first control voltage, the impedance value between the first end and the second end of the non-resistance load unit is controlled by the first control voltage, and the non-resistance load unit is connected in series with an electric path from the power-on voltage to the reference ground through the detection unit; the feedback control unit is suitable for generating the first control voltage according to the breakover voltage; wherein, in response to the power-on voltage being less than or equal to a turn-over voltage, the first control voltage controls a resistance value between a first terminal and a second terminal of the non-resistive load unit to be a first resistance so that the turn-on voltage is a first logic level, and the turn-over voltage is greater than the turn-on voltage; in response to the power-up voltage being greater than the flipping voltage, the first control voltage controls a resistance value between the first terminal and the second terminal of the non-resistive load unit to be a second resistance so that the turn-on voltage is a second logic level different from the first logic level, the second resistance being greater than the first resistance.
Optionally, the detection unit comprises one or more diodes connected in series.
Optionally, the non-resistive load unit includes: a first transistor, a control terminal of which is connected to the first control voltage, an input terminal of which is coupled to an output terminal of the detection unit, and an output terminal of which is coupled to the reference ground directly or indirectly, wherein the first control voltage controls the first transistor to be turned on in response to the power-on voltage being less than or equal to the flip voltage, and the first control voltage controls the first transistor to be turned off in response to the power-on voltage being greater than the flip voltage.
Optionally, the first transistor is an NMOS transistor.
Optionally, the feedback control unit comprises: the input end of the output logic subunit is connected with the breakover voltage and is suitable for carrying out logic operation on the breakover voltage so as to generate a second control voltage; and a switch unit, a control end of which is connected to the second control voltage, an input end of which is connected to a related voltage, and an output end of which outputs the first control voltage, wherein the related voltage is related to the power-on voltage, and in response to the power-on voltage being less than or equal to the turnover voltage, the switch unit is turned on so that the first control voltage is equal to the related voltage, and in response to the power-on voltage being greater than the turnover voltage, the switch unit is turned off.
Optionally, the output logic subunit includes: and the input end of the first inverter is connected with the breakover voltage, and the output end of the first inverter outputs the second control voltage.
Optionally, the output logic subunit includes: and the input end of the hysteresis comparator is connected with the conducting voltage, the output end of the hysteresis comparator outputs the second control voltage, and the conducting voltage is greater than the upper limit threshold voltage of the hysteresis comparator in response to the fact that the power-on voltage is greater than the overturning voltage.
Optionally, the switching unit comprises: a second transistor, a control end of which is connected to the second control voltage, and an input end of which is connected to the associated voltage; a third transistor, a control terminal of which is connected to a third control voltage, an input terminal of which is coupled to the output terminal of the second transistor, and an output terminal of which is coupled to the reference ground directly or indirectly; the input end of the second inverter is connected with the second control voltage, and the output end of the second inverter outputs the third control voltage; wherein, in response to the power-up voltage being less than or equal to the flipping voltage, the second transistor is turned on, and the third transistor is turned off, so that the switch unit is turned on; in response to the power-up voltage being greater than the flipping voltage, the second transistor is turned off, the third transistor is turned on, and the switching unit is turned off.
Optionally, the power-on voltage detection circuit further includes: a first voltage dividing resistor, the first end of which is connected to the power-on voltage; a first terminal of the second voltage-dividing resistor is coupled to the second terminal of the first voltage-dividing resistor and the input terminal of the second transistor, and the second terminal of the second voltage-dividing resistor is coupled to the output terminal of the third transistor.
Optionally, the power-on voltage is a power supply voltage of an IO interface circuit, and the output logic subunit and the second inverter are in different power domains from the IO interface circuit.
In order to solve the above technical problem, an embodiment of the present invention further provides an electronic device, where the electronic device includes the above power-on voltage detection circuit.
In order to solve the technical problem, an embodiment of the present invention further provides an internet of things device, where the internet of things device includes the electronic device.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the power-on voltage detection circuit of the embodiment of the invention may include: the detection unit is suitable for detecting the power-on voltage received by the power port, and in response to the fact that the power-on voltage is larger than the starting voltage, the output end of the detection unit generates a conducting voltage; the non-resistance load unit is coupled with the output end of the detection unit, the control end of the non-resistance load unit is connected with a first control voltage, the impedance value between the first end and the second end of the non-resistance load unit is controlled by the first control voltage, and the non-resistance load unit is connected in series with an electric path from the power-on voltage to the reference ground through the detection unit; the feedback control unit is suitable for generating the first control voltage according to the breakover voltage; further, the power-on voltage detection circuit may respectively adjust, when the power-on voltage is less than or equal to the flipping voltage and when the power-on voltage is greater than the flipping voltage, an impedance value between the first end and the second end of the non-resistive load unit to a first impedance and a second impedance through the first control voltage, and correspondingly, the turn-on voltage is different logic levels to indicate a magnitude relationship between the power-on voltage and the flipping voltage, so as to determine the power supply mode in which the power port is located. On one hand, compared with the prior art, the scheme of the embodiment of the invention does not need to introduce additional reference voltage, and has better circuit stability, and on the other hand, because the non-resistance load unit is adopted as the load, the static power consumption consumed by the scheme of the embodiment of the invention is lower, and the power consumption of the detection circuit can be better reduced.
Further, the feedback control unit may include: the input end of the output logic subunit is connected with the breakover voltage and is suitable for carrying out logic operation on the breakover voltage so as to generate a second control voltage; a switching unit, a control terminal of which is connected to the second control voltage, an input terminal of which is connected to an associated voltage, and an output terminal of which outputs the first control voltage, wherein the associated voltage is associated with the power-on voltage, and in response to the power-on voltage being less than or equal to the turn-over voltage, the switching unit is turned on so that the first control voltage is equal to the associated voltage, and in response to the power-on voltage being greater than the turn-over voltage, the switching unit is turned off; further, the output logic subunit may include: and the input end of the hysteresis comparator is connected with the conducting voltage, the output end of the hysteresis comparator outputs the second control voltage, and the conducting voltage is greater than the upper limit threshold voltage of the hysteresis comparator in response to the fact that the power-on voltage is greater than the overturning voltage. When the power-on voltage has burrs and is enabled to float around the overturning voltage but not lower than the lower limit threshold voltage of the hysteresis comparator, the stability of the second control voltage can be ensured according to the hysteresis characteristic of the hysteresis comparator, so that the circuit reliability of the power-on voltage detection circuit is improved.
Further, the power-on voltage detection circuit may further include a first voltage-dividing resistor and a second voltage-dividing resistor. Since the associated voltage is obtained by dividing the power-up voltage through the first voltage dividing resistor and the second voltage dividing resistor, that is, the first control voltage applied to the control terminal of the first transistor is lower than the power-up voltage, the device stress of the first transistor can be reduced to prevent the control voltage from being too high to affect the device performance.
Drawings
Fig. 1 is a schematic structural block diagram of a power-on voltage detection circuit according to an embodiment of the present invention.
Fig. 2 is a schematic block diagram of another power-on voltage detection circuit according to an embodiment of the present invention.
Fig. 3 is a circuit diagram of a power-on voltage detection circuit according to an embodiment of the invention.
Fig. 4 is a simulation diagram of the power-on voltage detection circuit shown in fig. 3.
Detailed Description
As described in the background section, Integrated Circuits (ICs) typically require a power-up voltage to be detected to determine which power mode the IC is in. In the prior art, a voltage comparator can be used for the above detection, however, this solution requires an additional reference voltage, may introduce additional circuit reliability problems, and also requires additional circuit area and power consumption. Meanwhile, low power consumption design becomes the mainstream of electronic chip and electronic product design. Therefore, when detecting the power-on voltage, it is necessary to improve the stability of the detection circuit and meet the requirement of low power consumption of the detection circuit.
In view of the above technical problems, an embodiment of the present invention provides a power-on voltage detection circuit with low power consumption and high circuit reliability, which includes a detection unit, a non-resistive load unit, and a feedback control unit, where the detection unit detects a power-on voltage, the detection unit generates a conduction voltage when the power-on voltage is greater than a turn-on voltage, and the feedback control unit generates a first control voltage according to the conduction voltage to control an impedance value between a first end and a second end of the non-resistive load unit; further, when the power-on voltage is less than or equal to or less than a turn-over voltage (greater than a turn-on voltage), the first control voltage controls the impedance value to be different, so that the logic levels of the turn-on voltages are different to indicate the magnitude relationship between the power-on voltage and the turn-over voltage.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic structural block diagram of a power-on voltage detection circuit according to an embodiment of the present invention.
The power-on voltage detection circuit 100 shown in fig. 1 may include a detection unit 10, a non-resistive load unit 20, and a feedback control unit 30.
Wherein, the detecting unit 10 is adapted to detect a power-on voltage VddIO received by a power port (not shown), and in response to the power-on voltage VddIO being greater than a turn-on voltage (not shown), an output terminal of the detecting unit 10 generates a turn-on voltage Vbo. The magnitude of the turn-on voltage is related to the circuit structure of the detection unit 10, and when the power-on voltage VddIO is less than or equal to the turn-on voltage, the output end of the detection unit 10 does not generate the conduction voltage Vbo.
As a non-limiting example, in a specific implementation, the detection unit 10 may include one or more diodes connected in series (see fig. 3, fig. 3 illustrates a plurality of diodes D1, D2, … … and Dm connected in series, m is a positive integer). Accordingly, the turn-on voltage is equal to the turn-on voltage of the one diode or the equivalent turn-on voltage of a plurality of diodes connected in series (i.e., the sum of the turn-on voltages of the diodes). Preferably, the detection unit 10 may include a plurality of diodes connected in series, so as to adjust the turn-on voltage by the number of the diodes.
The non-resistance load unit 20 is coupled to the output end of the detection unit 10, the control end of the non-resistance load unit is connected to a first control voltage V1, the impedance value between the first end and the second end of the non-resistance load unit 20 is controlled by the first control voltage V1, and the non-resistance load unit 20 is connected in series to the electrical path from the power-on voltage VddIO to the reference ground Vss through the detection unit 10. The non-resistive load unit 20 is a load unit other than a resistor, and the impedance value between the first terminal and the second terminal is controlled, for example, it may be a transistor or other electronic components, or a combination of electronic components. It should be noted that, in this embodiment, a specific manner of connecting the detection unit 10 and the non-resistive load unit 20 in series in the path from the power-on voltage VddIO to the reference ground Vss is not particularly limited, for example, the two may be connected in the manner shown in fig. 1, or the two may be interchanged.
The feedback control unit 30 is adapted to generate the first control voltage V1 in dependence on the breakover voltage Vbo for controlling the impedance value between the first and second terminals of the non-resistive load unit 20 in dependence on the breakover voltage Vbo. Specifically, in response to the power-on voltage VddIO being equal to or less than a flipping voltage (not shown), the first control voltage V1 controls the impedance value between the first terminal and the second terminal of the non-resistive load unit 20 to be a first impedance, so that the turn-on voltage Vbo is a first logic level (e.g., a logic low level), and the flipping voltage is greater than the turn-on voltage; in response to the power-on voltage VddIO being greater than the flipping voltage, the first control voltage V1 controls the impedance value between the first terminal and the second terminal of the non-resistive load cell 20 to be a second impedance such that the turn-on voltage Vbo is a second logic level (e.g., a logic high level) different from the first logic level, the second impedance being greater than the first impedance.
Further, in the embodiment of the present invention, when the power-on voltage VddIO is less than or equal to the turning voltage and the power-on voltage VddIO is greater than the turning voltage, the power-on voltage VddIO detection circuit may respectively adjust the impedance value between the first end and the second end of the non-resistive load unit 20 to be the first impedance and the second impedance through the first control voltage V1, and correspondingly, the conduction voltage Vbo is a different logic level to indicate the magnitude relationship between the power-on voltage VddIO and the turning voltage, so as to determine the power supply mode of the power port. On one hand, compared with the prior art, the scheme of the embodiment of the invention does not need to introduce additional reference voltage, and has better circuit stability, and on the other hand, because the non-resistance load unit 20 is adopted as the load, the scheme of the embodiment of the invention consumes lower static power consumption, and can better reduce the power consumption of the detection circuit.
In a specific implementation, the power-on voltage detection circuit 100 according to the embodiment of the present invention may be carried on a circuit board, and may also be used in an IC, that is, as an electronic device carried on a chip. Generally, an IC may generally include at least two circuit domains, i.e., a main circuit and an Input/Output (IO) interface circuit. The main circuit may include other functional circuits besides the IO interface circuit; the main circuit may be an Intellectual Property (IP) core. The main circuit and the IO interface circuit are generally in different power domains.
It should be noted that, in the embodiment of the present invention, the sizes of the first impedance and the second impedance are not particularly limited, as long as the second impedance is larger than the first impedance. In a specific implementation, the first impedance may be a small and appropriate value, and preferably, the first impedance is larger than an equivalent impedance of the detection unit 10; the second impedance may be infinite, that is, the first and second terminals of the non-resistive load unit 20 are completely turned off.
Referring to fig. 1 and 2 together, in a preferred implementation, the non-resistive load unit 20 may include a first transistor (shown as an NMOS transistor in fig. 2) MNL, a control terminal (i.e., a gate of the NMOS transistor) of the first transistor MNL is connected to the first control voltage V1, an input terminal (i.e., a drain of the NMOS transistor) of the first transistor MNL is coupled to the output terminal of the detection unit 10, and an output terminal (i.e., a source of the NMOS transistor) of the first transistor MNL is directly or indirectly coupled to the ground Vss, where indirectly coupled means that indirect coupling may be performed via other electronic components. In response to the power-on voltage VddIO being less than or equal to the switching voltage, the first control voltage V1 controls the first transistor MNL to be turned on, that is, corresponding to the impedance value being 0 Ω; in response to said power-up voltage VddIO being greater than said flipping voltage, said first control voltage V1 controls said first transistor MNL to turn off, i.e. corresponding to said impedance value being infinity.
Further, it is understood by those skilled in the art that the first Transistor MNL may be a unipolar Transistor (also called a field effect Transistor, such as an NMOS Transistor or a PMOS Transistor) or a Bipolar Transistor, which is all called a Bipolar Junction Transistor (BJT). When the transistor is a unipolar transistor, the control end of the transistor is a grid electrode, and the input end and the output end of the transistor can be a source electrode and a drain electrode respectively or are interchanged; when the transistor is a bipolar transistor, the control terminal is a base, and the input terminal and the output terminal can be an emitter and a collector, respectively, or interchanged. For simplicity, the first transistor MNL is described as an NMOS transistor. It is also understood by those skilled in the art that when the first transistor MNL is a PMOS transistor or a BJT, the specific circuit connection manner of the non-resistive load unit 20 and the detection unit 10 can be adaptively adjusted, and will not be described herein.
Further, referring to fig. 2, the power-on voltage detection circuit 200 shown in fig. 2 is substantially identical to the circuit structure and operation principle of the power-on voltage detection circuit 100 shown in fig. 1, and the main difference is that in the power-on voltage detection circuit 200, the feedback control unit 30 may include an output logic subunit 301 and a switch unit 302.
Specifically, the input terminal of the output logic subunit 301 is connected to the turn-on voltage Vbo, and the output logic subunit 301 is adapted to perform a logic operation on the turn-on voltage Vbo to generate the second control voltage V2. In a specific implementation, for example, the output logic subunit 301 may be a logic gate device or a combinational logic circuit to implement a logic operation function on the turn-on voltage Vbo.
The control end of the switch unit 302 is connected to the second control voltage V2, the input end of the switch unit 302 is connected to a related voltage VddIO ', the output end of the switch unit 302 outputs the first control voltage V1, and the related voltage VddIO' is related to the power-on voltage VddIO, for example, the related voltage VddIO 'may be equal to the power-on voltage VddIO, or the related voltage VddIO' may be in a linear relationship, such as a proportional relationship, with the power-on voltage VddIO, so that the power-on voltage detection circuit 200 according to the embodiment of the present invention may be applicable to power-on voltage detection for a conventional power supply voltage of 2 times or more, so as to improve detection reliability. Further, in response to the power-on voltage VddIO being less than or equal to the flipping voltage, the switch unit 302 is turned on, so that the first control voltage V1 is equal to the associated voltage VddIO', and in response to the power-on voltage VddIO being greater than the flipping voltage, the switch unit 302 is turned off.
As a non-limiting example, in a specific implementation, the output logic subunit 301 may include a first inverter (not shown), an input end of the first inverter is connected to the conducting voltage Vbo, and an output end of the first inverter outputs the second control voltage V2, so that the second control voltage V2 and the conducting voltage Vbo have opposite logic levels.
For more information on the power-up voltage detection circuit 200 shown in fig. 2, reference is made to the related description of the power-up voltage detection circuit 100 shown in fig. 1, and details thereof are not repeated herein.
Fig. 3 is a circuit diagram of a power-on voltage detection circuit according to an embodiment of the invention.
Referring to fig. 3, the power-on voltage detection circuit 300 shown in fig. 3 is substantially identical to the circuit structure and operation principle of the power-on voltage detection circuit 200 shown in fig. 2, and the main difference is that in the power-on voltage detection circuit 300, preferably, the output logic subunit (see fig. 2) may include a hysteresis comparator U1.
The input end of the hysteresis comparator U1 is connected to the conducting voltage Vbo, and the output end thereof outputs the second control voltage V2; in response to the power-up voltage VddIO being greater than the flipping voltage, the turn-on voltage Vbo is greater than an upper threshold voltage of the hysteretic comparator U1. As understood by those skilled in the art, a hysteretic comparator, also known as a schmitt trigger, has a hysteretic characteristic with an upper threshold voltage and a lower threshold voltage; in general, when the level input to the hysteretic comparator U1 is greater than its upper threshold voltage or less than its lower threshold voltage, its output logic flips, while when the level input thereto is between its lower and upper threshold voltages, its output logic does not change.
In this embodiment, when the power-on voltage VddIO is greater than the flipping voltage, the turn-on voltage Vbo is greater than the upper threshold voltage of the hysteretic comparator U1, so that the output logic of the hysteretic comparator U1 is flipped to obtain the second control voltage V2; in addition, when the power-on voltage VddIO is glitched and floated around the flip voltage but not lower than the lower threshold voltage of the hysteresis comparator U1, the stability of the second control voltage V2 can be ensured according to the hysteresis characteristic of the hysteresis comparator U1, so as to improve the circuit reliability of the power-on voltage detection circuit 300.
It should be noted that, in the embodiment of the present invention, the lower threshold voltage of the hysteresis comparator U1 is not particularly limited.
Further, in the present embodiment, the switch unit 302 (see fig. 2) may be any suitable switch or switching device, for example, it may be a semiconductor switch such as a MOS transistor or a BJT, and may also be a conventional switch element or an integrated switch packaged in a chip, which is not limited in this embodiment.
As a non-limiting example, the switching unit 302 (see fig. 2) may include a second transistor MNT, a third transistor MND, and a second inverter U2. The present embodiment does not specifically limit the specific types of the second transistor MNT and the third transistor MND, and for simplicity, both of them are illustrated as NMOS transistors.
The control end (i.e. the gate of the NMOS transistor) of the second transistor MNT is connected to the second control voltage V2, and the input end (i.e. the drain of the NMOS transistor) of the second transistor MNT is connected to the associated voltage VddIO'; a control terminal (i.e., a gate of the NMOS transistor) of the third transistor MND is connected to a third control voltage V3, an input terminal (i.e., a drain of the NMOS transistor) thereof is coupled to an output terminal (i.e., a source of the NMOS transistor) of the second transistor MNT, and an output terminal (i.e., a source of the NMOS transistor) of the third transistor MND is directly or indirectly coupled to the reference ground Vss; the input terminal of the second inverter U2 is connected to the second control voltage V2, and the output terminal thereof outputs the third control voltage V3.
Further, in response to the power-on voltage VddIO being equal to or less than the flip voltage, the second transistor MNT is turned on, and the third transistor MND is turned off, so that the switching unit (see fig. 2) is turned on; in response to the power-on voltage VddIO being greater than the flip voltage, the second transistor MNT is turned off, the third transistor MND is turned on, and the switching unit 302 (see fig. 2) is turned off.
Further preferably, the power-on voltage detection circuit 300 may further include a first voltage-dividing resistor R1 and a second voltage-dividing resistor R2. The first end of the first voltage dividing resistor R1 is connected to the power-on voltage VddIO; a first terminal of the second voltage-dividing resistor R2 is coupled to the second terminal of the first voltage-dividing resistor R1 and the input terminal of the second transistor MNT, and inputs the associated voltage VddIO', and a second terminal of the second voltage-dividing resistor R2 is coupled to the output terminal of the third transistor MND; optionally, the output of the third transistor MND is terminated by the reference ground Vss.
Since the associated voltage VddIO' is obtained by dividing the power-up voltage VddIO by the first voltage dividing resistor R1 and the second voltage dividing resistor R2, that is, the first control voltage V1 acting on the control terminal of the first transistor MNL is lower than the power-up voltage VddIO, the device stress of the first transistor MNL can be reduced to prevent the control voltage from being too high to affect the device performance.
In a specific implementation, the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 may be implemented by MOS transistors to save circuit power consumption; specifically, the MOS transistors may be connected in a diode connection manner, so that the MOS transistors are resistive, which is beneficial to saving power consumption; or the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 may be resistors, and preferably, the values of the two resistors are larger, so as to save the power consumption of the circuit.
Optionally, the power-on voltage detection circuit 300 may further include a third inverter U3 adapted to obtain an inverted voltage Detect thereof according to the third control voltage V3, and an external circuit (not shown) determines the power supply mode of the power port by identifying a logic level of the inverted voltage Detect of the third control voltage V3.
For more information on the power-up voltage detection circuit 300 shown in fig. 3, reference is made to the related description of the power-up voltage detection circuit 200 shown in fig. 2, which is not repeated herein.
Fig. 4 is a simulation diagram of the power-on voltage VddIO detection circuit shown in fig. 3.
With reference to fig. 3 and 4, the operation of the power-up voltage detection circuit 300 is as follows. Wherein "0" represents a logic low level, and "1" represents a logic high level, and it is assumed that the power port has two power supply modes, i.e., the power-on voltage VddIO is 3V and 5V, respectively.
The equivalent turn-on voltages of the diodes D1 to Dm connected in series are about 3V, when the power-on voltage VddIO rises from 0V to 3V, each diode is not turned on, no current flows through the diode, and the turn-on voltage Vbo is not generated, that is, the turn-on voltage Vbo is 0, the second control voltage V2 is 1, the third control voltage V3 is 0, the second transistor MNT is turned on, the third transistor MND is turned off, the first control voltage V1 is 1, and the first transistor MNL is turned on, but no current exists thereon; in the process that the power-on voltage VddIO rises from 3V to 5V, each diode is turned on, so that a current flows through the diode, the turn-on voltage Vbo starts to rise, the current IMNL of the first transistor MNL also starts to rise, when the power-on voltage VddIO is greater than 4.1V (i.e., the turning voltage), the turn-on voltage Vbo is identified as 1, the second control voltage V2 is 0, the third control voltage V3 is 1, the second transistor MNT is turned off, the third transistor MND is turned on, the first control voltage V1 is 0, so that the first transistor MNL is turned off, the current IMNL of the first transistor MNL is reduced to 0A, and the turn-on voltage Vbo increases, which is a difference between the power-on voltage VddIO and the turning-on voltage; as the power-up voltage VddIO continues to increase from 4.1V, the turn-on voltage Vbo continues to increase, the logic levels of the second control voltage V2 and the third control voltage V3, and the current IMNL of the first transistor MNL remain unchanged.
In an application scenario of the embodiment of the present invention, the power-up voltage VddIO is a power supply voltage of an IO interface circuit (not shown in the figure), the output logic subunit 301 (not labeled in the figure, see the hysteresis comparator U1) and the second inverter U2 are located in different power domains from the IO interface circuit, for example, the output logic subunit 301 and the second inverter U2 may be located in a main circuit (not shown in the figure) and powered by using the power supply voltage Vddcore of the main circuit, and the power supply voltage Vddcore of the main circuit is generally smaller than the power-up voltage VddIO.
The embodiment of the invention also discloses an electronic device which can be packaged in a chip form. In particular, the electronic device may include the power-on voltage detection circuit shown in any one of fig. 1 to 3, so that the electronic device has lower power consumption and better circuit stability.
The embodiment of the invention also discloses an Internet of Things (Internet of Things) device, and the IOT device can comprise the electronic device, so that the IOT device has lower power consumption and better circuit stability. For example, the IOT device may be a smart home device or a wearable device, etc.
It should be noted that "logic high level" and "logic low level" in this document are relative logic levels. Here, the "logic high level" refers to a level range that can be recognized as a digital signal "1", and the "logic low level" refers to a level range that can be recognized as a digital signal "0", and the specific level range thereof is not particularly limited.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A power-on voltage detection circuit, comprising:
the detection unit is suitable for detecting the power-on voltage received by the power port, and in response to the fact that the power-on voltage is larger than the starting voltage, the output end of the detection unit generates a conducting voltage;
the non-resistance load unit is coupled with the output end of the detection unit, the control end of the non-resistance load unit is connected with a first control voltage, the impedance value between the first end and the second end of the non-resistance load unit is controlled by the first control voltage, and the non-resistance load unit is connected in series with an electric path from the power-on voltage to the reference ground through the detection unit;
the feedback control unit is suitable for generating the first control voltage according to the breakover voltage;
wherein, in response to the power-on voltage being less than or equal to a turn-over voltage, the first control voltage controls a resistance value between a first terminal and a second terminal of the non-resistive load unit to be a first resistance so that the turn-on voltage is a first logic level, and the turn-over voltage is greater than the turn-on voltage; in response to the power-up voltage being greater than the flipping voltage, the first control voltage controls a resistance value between the first terminal and the second terminal of the non-resistive load unit to be a second resistance so that the turn-on voltage is a second logic level different from the first logic level, the second resistance being greater than the first resistance.
2. The power-on voltage detection circuit according to claim 1, wherein the detection unit comprises one or more diodes connected in series.
3. The power-on voltage detection circuit according to claim 1, wherein the non-resistive load unit includes:
a first transistor, a control terminal of which is connected to the first control voltage, an input terminal of which is coupled to an output terminal of the detection unit, and an output terminal of which is coupled to the reference ground directly or indirectly, wherein the first control voltage controls the first transistor to be turned on in response to the power-on voltage being less than or equal to the flip voltage, and the first control voltage controls the first transistor to be turned off in response to the power-on voltage being greater than the flip voltage.
4. The power-on voltage detection circuit according to claim 3, wherein the first transistor is an NMOS transistor.
5. The power-on voltage detection circuit according to claim 1, wherein the feedback control unit includes:
the input end of the output logic subunit is connected with the breakover voltage and is suitable for carrying out logic operation on the breakover voltage so as to generate a second control voltage;
and a switch unit, a control end of which is connected to the second control voltage, an input end of which is connected to a related voltage, and an output end of which outputs the first control voltage, wherein the related voltage is related to the power-on voltage, and in response to the power-on voltage being less than or equal to the turnover voltage, the switch unit is turned on so that the first control voltage is equal to the related voltage, and in response to the power-on voltage being greater than the turnover voltage, the switch unit is turned off.
6. The power-on voltage detection circuit of claim 5, wherein the output logic subunit comprises: and the input end of the first inverter is connected with the breakover voltage, and the output end of the first inverter outputs the second control voltage.
7. The power-on voltage detection circuit of claim 5, wherein the output logic subunit comprises: and the input end of the hysteresis comparator is connected with the conducting voltage, the output end of the hysteresis comparator outputs the second control voltage, and the conducting voltage is greater than the upper limit threshold voltage of the hysteresis comparator in response to the fact that the power-on voltage is greater than the overturning voltage.
8. The power-on voltage detection circuit according to claim 5, wherein the switching unit includes:
a second transistor, a control end of which is connected to the second control voltage, and an input end of which is connected to the associated voltage;
a third transistor, a control terminal of which is connected to a third control voltage, an input terminal of which is coupled to the output terminal of the second transistor, and an output terminal of which is coupled to the reference ground directly or indirectly;
the input end of the second inverter is connected with the second control voltage, and the output end of the second inverter outputs the third control voltage;
wherein, in response to the power-up voltage being less than or equal to the flipping voltage, the second transistor is turned on, and the third transistor is turned off, so that the switch unit is turned on; in response to the power-up voltage being greater than the flipping voltage, the second transistor is turned off, the third transistor is turned on, and the switching unit is turned off.
9. The power-on voltage detection circuit according to claim 8, further comprising:
a first voltage dividing resistor, the first end of which is connected to the power-on voltage;
a first terminal of the second voltage-dividing resistor is coupled to the second terminal of the first voltage-dividing resistor and the input terminal of the second transistor, and the second terminal of the second voltage-dividing resistor is coupled to the output terminal of the third transistor.
10. The power-on voltage detection circuit according to claim 8, wherein the power-on voltage is a supply voltage of an IO interface circuit, and the output logic subunit and the second inverter are in different power domains from the IO interface circuit.
11. An electronic device characterized by comprising the power-on voltage detection circuit according to any one of claims 1 to 10.
12. An internet of things device comprising the electronic device of claim 11.
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