CN110794942B

CN110794942B - Reset chip circuit

Info

Publication number: CN110794942B
Application number: CN201810877678.6A
Authority: CN
Inventors: 崔先宇; 谢程益; 于翔; 其他发明人请求不公开姓名
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2018-08-03
Filing date: 2018-08-03
Publication date: 2021-07-09
Anticipated expiration: 2038-08-03
Also published as: CN110794942A

Abstract

A reset chip circuit can shorten the leakage time from millisecond level to microsecond level, thereby reducing the power consumption of the reset chip circuit, comprising a watchdog detection end, the watchdog detection end is connected with the input end of a Schmitt trigger through a second resistor, the output end of the Schmitt trigger outputs a second signal, the input end of the Schmitt trigger is connected with a grounding end through a first capacitor, the watchdog detection end is connected with a first port of a transmission gate module through a first resistor, the first port of the transmission gate module is connected with the grounding end through a first switch tube, a third signal end of the transmission gate module is connected with a third signal end of an enabling module, a fourth signal end of the transmission gate module is connected with a fourth signal end of the enabling module, the enabling module is provided with a first signal end and a second signal end, the first signal end of the enabling module is connected with the output end of a first phase inverter, the output end of the first phase inverter is connected with the controlled end of the enabling module through a control module, the output end of the first inverter is connected with the second port of the transmission gate module.

Description

Reset chip circuit

Technical Field

The invention relates to a reset chip technology with a watchdog function, in particular to a reset chip circuit, which can shorten the leakage time from millisecond level to microsecond level and simultaneously reduce the average value of leakage current by setting the circuit logic control of a switch transmission gate, thereby reducing the power consumption of the reset chip circuit and having almost no influence on the cost.

Background

At present, a reset chip generally has a watchdog function for detecting whether a CPU works normally, a watchdog detection terminal (WDI) generally detects three states, a constant high or constant low, suspended tri-state and a normal working state, where the normal state is a signal for generating a jump by the CPU. If the signal at the watchdog input is held constant high or low for 1.6s, the output will generate a reset signal. At present, there are two main designs of watchdog WDI end: 1. when the suspension state is detected, a signal is generated to close the watchdog, but part of circuits of the watchdog always leak electricity; when the WDI detects a normal signal, the detection circuit also leaks current, in both cases by at least tens of microamps. 2. Some methods reset the count of 1.6s by using internal pulse, the first 1.4s of the signal is low level, the last 0.2s of the signal is high level, and the watchdog is reset by changing two edges. The inventor finds that the reset chips are all small chips, cost and power consumption are important parameters, and the method can be used but wastes excessive current and increases power consumption. If the operating current of the whole circuit is only a few microamperes, the leakage reaches dozens of microamperes and the time is long, which is not sensible. The inventor believes that if the transmission gate module is arranged in the reset chip circuit with the watchdog function and appropriate logic is added, the leakage time can be shortened from millisecond level to microsecond level, the average value of leakage current is reduced, the power consumption is reduced, and the cost is hardly influenced. In view of the above, the present inventors have completed the present invention.

Disclosure of Invention

Aiming at the defects or shortcomings in the prior art, the invention provides the reset chip circuit, through setting the circuit logic control of the switch transmission gate, the leakage time can be shortened from millisecond level to microsecond level, and meanwhile, the average value of leakage current is also reduced, so that the power consumption of the reset chip circuit is reduced, and the cost is hardly influenced.

The technical scheme of the invention is as follows:

a reset chip circuit is characterized by comprising a watchdog detection end, wherein the watchdog detection end is connected with an input end of a Schmitt trigger through a second resistor, an output end of the Schmitt trigger outputs a second signal, an input end of the Schmitt trigger is connected with a grounding end through a first capacitor, the watchdog detection end is connected with a first port of a transmission gate module through a first resistor, a first port of the transmission gate module is connected with the grounding end through a first switch tube, a third signal end of the transmission gate module is connected with a third signal end of an enabling module, a fourth signal end of the transmission gate module is connected with a fourth signal end of the enabling module, the enabling module is provided with a first signal end and a second signal end, the first signal end of the enabling module is connected with an output end of a first phase inverter, an output end of the first phase inverter is connected with a controlled end of the enabling module through a control module, and the output end of the first phase inverter is connected with the second port of the transmission gate module.

The Schmitt trigger, the enabling module and the first phase inverter are respectively connected with a power supply end.

The first resistor is a current limiting resistor of 40K ohms.

The first capacitor is a filter capacitor, the first capacitor and the second resistor form a filter circuit, and the filter circuit filters noise at the detection end of the watchdog.

The control module prevents the electric leakage of the watchdog detection end in normal work by turning off the resistor inside the enabling module.

The first switch tube is an NMOS tube, a first port of the transmission gate module is connected with a drain electrode of the NMOS tube, a source electrode of the NMOS tube is connected with a grounding end, and a grid electrode of the NMOS tube is an electrifying indication signal input end.

The invention has the following technical effects: the reset chip circuit of the invention utilizes the transmission gate and proper logic to reduce the leakage current of the circuit to the minimum. The system mainly comprises an enabling module EN, a control module cut, a transmission gate module TG and a Schmitt trigger. EN also represents the enabling signal of the transmission gate, EN detects the signals of a first signal A and a second signal B, wherein the signal A is a pulse which is internally used for clearing 1.6s, the signal B is the output signal of the watchdog schmitt trigger, when A, B cocurrent EN generates an enabling signal to open the transmission gate, when A, B cocurrent EN generates an enabling signal to close the transmission gate, the cut module is used for turning off a resistor inside the EN module, and the problem of EN electric leakage when the watchdog detection end WDI normally works is prevented. In the circuit structure, the left side of WDI is called a buff module, the right side of WDI is called a schmitt trigger detection module of WDI, por _ L is a power-on indicating signal, a first resistor R1 has a current limiting function and is 40K, and a second resistor R2 and a first capacitor C1 have a filtering function to prevent noise of WDI. The most likely cases of leakage currents are: the signal A is L (low), the front inverter, i.e. the first inverter INV1, is N-transistor ON, and WDI is H (high), which will generate current on the current limiting resistor R1, if the transmission gate is in ON state, the leakage current flowing out path is WDI-R1-NMOS transistor GND of the transmission gate-A-INV 1. The invention aims to reduce the electric leakage under various conditions to the minimum.

Drawings

Fig. 1 is a schematic diagram of a structural principle of a reset chip circuit for implementing the present invention.

Fig. 2 is a schematic diagram of the internal pulse (pulse) driving logic when the external capacitor (not shown in fig. 1) is connected to the watchdog detection terminal WDI in fig. 1 and is 200 pf.

Fig. 3 is a schematic diagram of internal logic of the watchdog detector WDI in fig. 1 when detecting a normal signal.

The reference numbers are listed below: VDD-power supply terminal; INV1 — first inverter; EN-Enable module or enable signal; CUT-control module (e.g., to turn off a resistor inside EN module, preventing WDI from normal-operation EN leakage problems); a TG-transmission gate module; MN1 — first switching tube; r1 — first resistance; r2 — second resistance; WDI-watchdog detection end or WDI point or WDI signal; c1 — first capacitance; ST-Schmitt Trigger (Schmitt Trigger); GND-ground; a-a first signal or a signal a or a position point or a point; b-second signal or B signal or signal B or B site point or B point; y-third signal or Y point or Y signal; YB-fourth signal or YB point or YB signal; i-current or current signal or I signal; por _ L-Power on indication signal. The combination of R2 and C1 acts as a filter; r1 limiting current (e.g., R1 is 40K ohms); leakage current outflow path: WDI-R1-TG-A-INV1 NMOS tube-GND.

Detailed Description

The invention is described below with reference to the accompanying drawings (fig. 1-3).

Fig. 1 is a schematic diagram of a structural principle of a reset chip circuit for implementing the present invention. Fig. 2 is a schematic diagram of the internal pulse (pulse) driving logic when the external capacitor (not shown in fig. 1) is connected to the watchdog detection terminal WDI in fig. 1 and is 200 pf. Fig. 3 is a schematic diagram of internal logic of the watchdog detector WDI in fig. 1 when detecting a normal signal. As shown in fig. 1 to 3, a reset chip circuit includes a watchdog detection terminal WDI, the watchdog detection terminal WDI is connected to an input terminal of a schmitt trigger ST through a second resistor R2, an output terminal of the schmitt trigger ST outputs a second signal B, the input terminal of the schmitt trigger ST is connected to a ground terminal GND through a first capacitor C1, the watchdog detection terminal WDI is connected to a first port of a transmission gate module TG through a first resistor R1, the first port of the transmission gate module TG is connected to the ground terminal GND through a first switch MN1, a third signal terminal of an enable module EN is connected to a third signal terminal (a third signal is a Y signal) of the enable module EN, a fourth signal terminal of the transmission gate module TG is connected to a fourth signal terminal (a fourth signal is a YB signal) of an enable module EN, the enable module EN has a first signal terminal (a first signal is an a signal) and a second signal terminal (a second signal is a signal terminal B signal) of the enable module EN, the first signal end of the enable module EN is connected with the output end of a first inverter INV1, the output end of the first inverter INV1 is connected with the controlled end of the enable module EN through a control module CUT, and the output end of the first inverter INV1 is connected with the second port of the transmission gate module TG. The schmitt trigger ST, the enabling module EN and the first inverter INV1 are respectively connected to a power supply terminal VDD. The first resistor R1 is a current limiting resistor of 40K ohms. The first capacitor is a filter capacitor, the first capacitor C1 and the second resistor R2 form a filter circuit, and the filter circuit filters noise of the watchdog detection end WDI. The control module CUT prevents the current leakage when the watchdog detection terminal WDI works normally by turning off the internal resistor of the enable module EN. The first switch tube MN1 is an NMOS tube, the first port of the transmission gate module TG is connected with the drain electrode of the NMOS tube, the source electrode of the NMOS tube is connected with the ground terminal GND, and the grid electrode of the NMOS tube is the input end of an electrifying indication signal por _ L.

Fig. 2 shows a first case of controlling the leakage current, WDI terminal floating, WDI potential is driven by internal pulse, but since WDI has a 200pf capacitor external to ground, which forms 8us delay with current limit R1, internal pulse is required to drive WDI for a time longer than 8us, that is, the pass gate on time is required to exceed 8us, the present invention sets a delay inside the EN module, EN generates the enable signal for pass gate off after detecting A, B opposite direction and 10us, EN generates the pass gate on enable signal with almost no delay when detecting A, B same direction. When power-on is not established, por _ L is H, the output potential, WDI and B of the transmission gate are all pulled to L, after power-on is established, por _ L is L, the switch tube MN1 does not work, the output potential, WDI and B of the transmission gate are also L, internal pulse starts to be L in return, so the transmission gate is always on, when the external capacitance of WDI is reasonable, a drives B before the transmission gate is off, so the transmission gate is always on, when the falling edge of internal pulse comes, a is L, WDI needs 8us to become L, so electric leakage occurs within microseconds, and a waveform diagram is shown in fig. 2. When the WDI external capacitor is too large, the transmission gate is turned off without driving the point B. Therefore, when WDI is suspended, the circuit only generates leakage current at the edge of the internal pulse, the maximum time is 8us, and then the transmission gate is turned off.

Fig. 3 shows a second case of controlling the leakage current, for example, fig. 3, the WDI terminal detects a normal signal, because WDI is an external signal, the level of the transition may be different from the level of the chip, and the logic circuit is in an intermediate state to generate the leakage current, in order to prevent this, the invention firstly performs current limiting on the schmitt trigger of WDI, and the maximum value can only reach 3 microamps, and secondly takes the output of the schmitt trigger as the B point of the buff in the buff module, so that the logic in the buff is prevented from being in the intermediate state, and no leakage current is generated. At this time, the signal a is L, the resistor causing delay in EN is short, EN generates a delay of only tens of ns for the enable signal, when WDI is L, although the transmission gate is on, the current limiting resistor R1 does not generate a voltage drop, and no leakage current is generated, and when WDI is H, although the current limiting resistor R1 generates a voltage drop, the transmission gate TG can be turned off with a delay of tens of ns, so the leakage current is mainly the current generated at this time (as in fig. 3, the current I is only a pulse appearing in the beginning time period). The third signal Y and the fourth signal YB in fig. 3 are inverted signals.

And in the third situation of controlling the leakage current, the WDI end detects an error signal and is constant high or low, according to the circuit, no voltage drop exists when the WDI is constant low, no leakage current exists, and when the WDI is constant high, the leakage current can be formed only when the A is L and the transmission gate TG is conducted, but the transmission gate TG is conducted after the A is changed into the H, the A is H, the WDI is also H, and no leakage current can be generated. In summary, the present invention is directed to minimizing leakage in various situations.

It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.

Claims

1. A reset chip circuit is characterized by comprising a watchdog detection end, wherein the watchdog detection end is connected with an input end of a Schmitt trigger through a second resistor, an output end of the Schmitt trigger outputs a second signal, an input end of the Schmitt trigger is connected with a grounding end through a first capacitor, the watchdog detection end is connected with a first port of a transmission gate module through a first resistor, a first port of the transmission gate module is connected with the grounding end through a first switch tube, a third signal end of the transmission gate module is connected with a third signal end of an enabling module, a fourth signal end of the transmission gate module is connected with a fourth signal end of the enabling module, the enabling module is provided with a first signal end and a second signal end, the first signal end of the enabling module is connected with an output end of a first phase inverter, an output end of the first phase inverter is connected with a controlled end of the enabling module through a control module, the output end of the first inverter is connected with the second port of the transmission gate module;

the outer part of the watchdog detection end is provided with a capacitor of 200pf to the ground, and a delay of 8us is formed by the capacitor and a first resistor, namely a current-limiting resistor, so that the conduction time of a transmission gate is certainly longer than 8us in order to drive the watchdog detection end.

2. The reset chip circuit of claim 1, wherein the schmitt trigger, the enabling module and the first inverter are each connected to a power supply terminal.

3. The reset chip circuit of claim 1, wherein the first resistor is a 40K ohm current limiting resistor.

4. The reset chip circuit according to claim 1, wherein the first capacitor is a filter capacitor, and the first capacitor and the second resistor form a filter circuit, and the filter circuit filters noise at the detection end of the watchdog.

5. The reset chip circuit of claim 1, wherein the control module prevents the current leakage when the watchdog test terminal is operating normally by turning off a resistor inside the enable module.

6. The reset chip circuit of claim 1, wherein the first switch transistor is an NMOS transistor, the first port of the transmission gate module is connected to the drain of the NMOS transistor, the source of the NMOS transistor is connected to a ground terminal, and the gate of the NMOS transistor is an input terminal of an power-on indication signal.