CN210350786U - Multiple RC clamp ESD protection circuit allowing fast power-up - Google Patents
Multiple RC clamp ESD protection circuit allowing fast power-up Download PDFInfo
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- CN210350786U CN210350786U CN201921478966.0U CN201921478966U CN210350786U CN 210350786 U CN210350786 U CN 210350786U CN 201921478966 U CN201921478966 U CN 201921478966U CN 210350786 U CN210350786 U CN 210350786U
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Abstract
The utility model provides a multiple RC that allows to go up electricity fast presss from both sides ESD protection circuit, including one-level RC clamp unit, the transistor of bleeding, the transistor control access and the second grade RC clamp unit of bleeding, one-level RC clamps the unit: the control circuit is used for keeping the drain transistor on through the drain transistor control path when an ESD event occurs; when the power is quickly powered on, the bleeder transistor is kept closed through the bleeder transistor control path; a secondary RC clamping unit: the turn-on time of the bleeder transistor is delayed while the bleeder transistor is turned on. The problem of in current electrostatic discharge ESD protection circuit, there is the unsuccessful or technical problem who burns out the system of power-on when needs are electrified fast, the utility model provides a RC that allows to go up power fast clamps ESD protection circuit, when the ESD incident takes place, the time that the transistor MN0 that releases switches on is about 1030nS, can satisfy the requirement of ESD design.
Description
Technical Field
The utility model belongs to the integrated circuit field, concretely relates to allow RC clamp ESD protection circuit of electricity fast.
Background
A conventional RC clamp (RC clamp device) in an ESD protection circuit for electrostatic discharge of a chip is shown in fig. 1 as follows. The size of the NMOS tube MN0 is large, and the channel width is 1000-2000 um. The RC0 module is composed of a resistor R0 and a capacitor C0, and since ESD discharge time lasts 1nS to 1uS, the RC constant of the RC0 module is usually set to 1uS, i.e., R0 × C0 is 1uS, R0 is 500K Ω, and C0 is 2 pF. The inverter INV1 is composed of PMOS transistor MP1 and NMOS transistor MN 1. The inverter INV2 is composed of PMOS transistor MP2 and NMOS transistor MN 2. The inverter INV3 is composed of PMOS transistor MP3 and NMOS transistor MN 3.
When the chip normally works, the node rc is pulled up to the level VCC through R0, that is, the voltage V (rc) from the node rc becomes VCC, and after passing through the inverter INV1, V (INV1out) becomes 0; after passing through the inverter INV2, V (INV2out) becomes VCC; after passing through the inverter INV3, V (trig) becomes 0, so the gate-source voltage of the NMOS transistor MN0 is 0V, and the NMOS transistor MN0 is in the off state.
When a forward ESD event occurs from power VCC to ground GND, GND is grounded (0V) and the VCC voltage increases rapidly. Because the capacitance of the capacitor C0 is relatively large and the resistance of the capacitor R0 is relatively large, the voltage at the node rc rises slowly with VCC. When the voltage V (rc) at the node rc is smaller than VCC/2, the inverter INV1 outputs a high level, i.e., V (INV1out) is VCC, V (INV2out) is 0, and V (trig) is VCC, so as to turn on the NMOS transistor MN0, and the ESD charges are discharged from the power supply VCC to GND through the NMOS transistor MN 0. As VCC charges C0 through R0, V (rc) rises continuously, and when V (rc) is greater than VCC/2 after a certain period of time (about 1 uS), the output of inverter INV1 is low, i.e., V (INV1out) is 0, V (INV2out) is VCC, and V (trig) is 0, and NMOS transistor MN0 is turned off.
The conventional RC clamp ESD protection circuit has a fatal defect when the chip is powered on rapidly: when the time for the VCC to rise from 0V to the working voltage is very short, for example, at 100nS to 1000nS, due to the influence of R0 and C0, the rising speed of the voltage V (rc) at the node rc is much slower than that of the VCC, which may cause a significant forward pulse to occur in the output V (INV1out) signal of the inverter INV1, and finally cause a significant forward pulse to occur in V (trig), and then cause the NMOS transistor MN0 to turn on, so that a large current may occur from the power source VCC to the ground GND, thereby causing unsuccessful power-up or system burnout, as shown in fig. 2.
SUMMERY OF THE UTILITY MODEL
In order to solve current electrostatic discharge ESD protection circuit, there is the unsuccessful or technical problem who burns out the system of going up electricity when needs are gone up the electricity fast, the utility model provides a multiple RC that allows to go up electricity fast presss from both sides ESD protection circuit.
The technical solution of the utility model is as follows:
a multiple RC clamp ESD protection circuit allowing fast power-up comprises a primary RC clamp unit, a drain transistor and a drain transistor control path, and is characterized in that: the circuit also comprises a two-stage RC clamping unit,
a first-stage RC clamping unit: the control circuit is used for keeping the drain transistor on through the drain transistor control path when an ESD event occurs; when the power is quickly powered on, the bleeder transistor is kept closed through the bleeder transistor control path;
a secondary RC clamping unit: the turn-on time of the bleeder transistor is delayed while the bleeder transistor is turned on.
Furthermore, the first-stage RC clamping unit comprises a resistor R0 and a capacitor C0 which are connected in series, one end of the first-stage RC clamping unit is connected with a power supply VCC, the other end of the first-stage RC clamping unit is connected with a ground wire GND, and an RC node of the first-stage RC clamping unit is connected to a control path of the bleeder transistor.
Further, the two-stage RC clamping unit comprises a resistor R1 and a capacitor C1 which are connected in parallel, one end of the resistor R1 and one end of the capacitor C1 are both connected to the power source VCC, and the other end of the resistor R1 and the other end of the capacitor C1 are connected to the bleeder transistor control path.
Further, the bleeder transistor control path comprises an inverter INV1, a transistor and an inverter INV3, the inverter INV1 is connected between the power VCC and the ground GND, the input end of the inverter INV1 is connected with the RC node of the first-stage RC clamping unit, the output end of the inverter is connected with the G stage of the transistor, the input end of the transistor is connected with the ground GND, the output end of the transistor is connected with the input end of the inverter INV3 after being connected with the resistor R1 and the capacitor C1, and the output end of the inverter INV3 controls the bleeder transistor.
Further, the transistor is an NMOS transistor MN2, an S-stage of the NMOS transistor MN2 is connected to the input of the resistor R1, the capacitor C1 and the inverter INV3, and a D-stage of the NMOS transistor MN2 is connected to the ground GND.
Further, the inverter INV1 includes an NMOS transistor MN1 and a PMOS transistor MP1, the G-stage of the transistors MN1 and MP1 are both connected to the RC node of the first stage RC clamp unit, the D-stage of the input terminal of the transistor MN1 is connected to the ground, the S-stage of the input terminal of the transistor MP1 is connected to the power VCC, and the S-stage of the output terminal of the transistor MN1 and the D-stage of the output terminal of the transistor MP1 are both connected to the G-stage of the transistor MN 2.
Further, the inverter INV3 includes an NMOS transistor MN3 and a PMOS transistor MP3, the G-stage of the transistors MN3 and MP3 are both connected to the output terminals of the second-stage RC clamp unit and the transistor MN2, the D-stage of the input terminal of the transistor MN3 is connected to the ground, the S-stage of the input terminal of the transistor MP3 is connected to the power VCC, and the S-stage of the output terminal of the transistor MN3 and the D-stage of the output terminal of the transistor MP3 are both connected to the bleeder transistor.
Further, the bleeder transistor is an NMOS transistor MN0, the G-stage of the transistor MN0 is controlled to be turned on by the bleeder transistor, the D-stage ground GND of the transistor MN0 is connected to the D-stage ground GND, and the S-stage of the transistor MN0 is connected to the power VCC.
Further, the RC constant of the first-stage RC clamping unit is 30 nS.
Further, the RC constant of the secondary RC clamping unit is 1 uS.
The utility model discloses the beneficial effect who has:
the utility model provides a RC that allows to go up electricity fast presss from both sides ESD protection circuit, when the ESD incident takes place, the time that transistor MN0 that releases switched on is about 1030nS, can satisfy the requirement of ESD design.
Drawings
FIG. 1 is a schematic diagram of a conventional RC clamp;
FIG. 2 is a schematic diagram of signals of a conventional RC clamp circuit during fast power-up;
FIG. 3 is a schematic diagram of an RC clamp ESD protection circuit that allows for fast power-up;
fig. 4 is a schematic diagram of a fast power-up process of an RC clamp ESD protection circuit that allows fast power-up.
Detailed Description
As shown in fig. 3, a multiple RC clamp ESD protection circuit allowing fast power up includes a primary RC clamp unit, a secondary RC clamp unit, a bleed transistor, and a bleed transistor control path. A first-stage RC clamping unit: the control circuit is used for keeping the drain transistor on through the drain transistor control path when an ESD event occurs; when the power is quickly powered on, the bleeder transistor is kept closed through the bleeder transistor control path; a secondary RC clamping unit: after the bleeder transistor is turned on, the on state of the bleeder transistor is maintained for 1 us.
Adjusting the RC constant of the first-stage RC clamping unit to meet the condition:
1) during an ESD event, the bleeder transistor MN0 may be turned on;
2) on rapid power-up, the bleed off transistor MN0 remains off.
By adding the two-stage RC clamping unit, the conduction time of the bleeder transistor MN0 is compensated, and the conduction time duration of 1us required by ESD design is met.
Furthermore, the first-stage RC clamping unit comprises a resistor R0 and a capacitor C0 which are connected in series, one end of the first-stage RC clamping unit is connected with a power supply VCC, the other end of the first-stage RC clamping unit is connected with a ground wire GND, and an RC node of the first-stage RC clamping unit is connected to a control path of the bleeder transistor.
Further, the two-stage RC clamping unit comprises a resistor R1 and a capacitor C1 which are connected in parallel, one end of the resistor R1 and one end of the capacitor C1 are both connected with the power supply VCC, and the other end of the resistor R1 and the other end of the capacitor C1 are connected with the bleeder transistor control path.
Further, the bleeder transistor control path comprises an inverter INV1, a transistor MN2 and an inverter INV3, the inverter INV1 is connected between a power supply VCC and a ground GND, the input end of the inverter INV1 is connected with the RC node of the first-stage RC clamping unit, the output end of the inverter is connected with the G stage of the transistor, the input end of the transistor is connected with the ground GND, the output end of the transistor is connected with the input end of the inverter INV3 after being connected with a resistor R1 and a capacitor C1, and the output end of the inverter INV3 controls the bleeder transistor. The transistor is an NMOS transistor MN2, the S-stage of the NMOS transistor MN2 is connected with the input of a resistor R1, a capacitor C1 and an inverter INV3, and the D-stage of the NMOS transistor MN2 is connected with the ground GND. The inverter INV1 comprises an NMOS transistor MN1 and a PMOS transistor MP1, wherein the G-stage of the transistor MN1 and the G-stage of the transistor MP1 are both connected with the RC node of the first-stage RC clamp unit, the D-stage of the input end of the transistor MN1 is connected with the ground, the S-stage of the input end of the transistor MP1 is connected with the power VCC, and the S-stage of the output end of the transistor MN1 and the D-stage of the output end of the transistor MP1 are both connected with the G-stage of the transistor MN 2.
The inverter INV2 comprises an NMOS transistor MN3 and a PMOS transistor MP3, wherein the G-stage of the transistor MN3 and the G-stage of the transistor MP3 are both connected to the output terminals of the second-stage RC clamp unit and the transistor MN2, the D-stage of the input terminal of the transistor MN3 is connected to the ground, the S-stage of the input terminal of the transistor MP3 is connected to the power source VCC, and the S-stage of the output terminal of the transistor MN3 and the D-stage of the output terminal of the transistor MP3 are both connected to the bleeder transistor.
The bleeder transistor is an NMOS transistor MN0, the G-level of the transistor MN0 is connected with the bleeder transistor for controlling on, the D-level ground wire GND of the transistor MN0, and the S-level of the transistor MN0 is connected with the power supply VCC.
The RC constant of the first-stage RC clamping unit is generally 30nS, and the RC constant of the second-stage RC clamping unit is generally 1 uS.
The utility model provides a RC clamps ESD protection circuit, the RC constant with one-level RC clamps unit falls to 30nS from 1uS, R0C 0 promptly equals 30 nS. R0 decreased from 500K Ω to 30K Ω, and C0 decreased from 2pF to 1 pF.
The element RC constant R1 × C1 of the two-stage RC clamping unit is set to 1uS, typically R1 equals 500K Ω, and C1 equals 2 pF.
As shown in table 1, the voltage levels of the nodes are listed in different operating states.
TABLE 1 tabulates the status of each node for different operating conditions
When the chip normally works, a serial node rc of the resistor R0 and the capacitor C0 is pulled high to a level VCC through R0, that is, v (rc) is VCC; after passing through the inverter INV1, V (INV1out) becomes VSS, the transistor MN2 is turned off, V (INV2out) is pulled up to VCC through R1, and after passing through the inverter INV3, V (trig) becomes 0, so the gate-source voltage Vgs of MN0 becomes 0V, and MN0 is in an off state.
When a power supply ESD event occurs, VSS is grounded (0V), and the VCC voltage increases rapidly. Because the capacitance of the capacitor C0 is relatively large and the resistance of the capacitor R0 is relatively large, the voltage at the node rc rises slowly with VCC. When the voltage V (rc) at the node a is lower than VCC/2, INV1 outputs a high level, i.e., V (INV1out) is VCC, MN2 is on, V (INV2out) is 0V because R1 has a large resistance, and V (trig) is VCC and MN0 is on after passing through INV 3. Since RC0 has an RC constant of 30nS, when about 30nS passes, the voltage at node RC becomes low, i.e., V (RC) becomes VCC, and after INV1, V (INV1out) becomes 0, and MN2 is turned off. After MN2 turns off, the voltage at node INV2out is gradually pulled up from 0V by R1 and C1, the rising time thereof is determined by the time constant R1 × C1, after about 1us, the voltage at INV2out rises from 0V to the reversal voltage of INV3, after INV3, V (trig) becomes 0V, and MN0 turns off. From the above, when an ESD event occurs, MN0 is turned on for about 30nS +1000nS — 1030nS, which satisfies the ESD design requirements.
When fast power-up (100nS < tr <1000nS), since RC constant of RC0 is 30nS, which is much smaller than minimum power-up time 100nS, voltage V (RC) of node RC during power-up rises immediately after VCC, i.e., V (RC) is approximately VCC, V (INV1out) is 0 after INV1, MN2 is in off state, node INV2out is connected to VCC through R1 and C1, i.e., V (INV2out) is VCC, V (trig) is 0V after INV3, MN0 is in off state, so current from VCC to GND is not caused, and the process is as shown in fig. 4.
It is to be understood that the above embodiments are merely exemplary embodiments that have been employed to illustrate the principles of the present invention, and that the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A multiple RC clamp ESD protection circuit allowing fast power-up, comprising a primary RC clamp unit, a bleed transistor and a bleed transistor control path, characterized in that: the circuit also comprises a two-stage RC clamping unit,
a first-stage RC clamping unit: the control circuit is used for keeping the drain transistor on through the drain transistor control path when an ESD event occurs; when the power is quickly powered on, the bleeder transistor is kept closed through the bleeder transistor control path;
a secondary RC clamping unit: the turn-on time of the bleeder transistor is delayed while the bleeder transistor is turned on.
2. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 1, wherein:
the primary RC clamping unit comprises a resistor R0 and a capacitor C0 which are connected in series, one end of the primary RC clamping unit is connected with a power supply VCC, the other end of the primary RC clamping unit is connected with a ground wire GND, and an RC node of the primary RC clamping unit is connected to a control path of the bleeder transistor.
3. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 1, wherein:
the two-stage RC clamping unit comprises a resistor R1 and a capacitor C1 which are connected in parallel, one end of the resistor R1 and one end of the capacitor C1 are both connected with a power supply VCC, and the other end of the resistor R1 and the other end of the capacitor C1 are connected with a control path of a bleeder transistor.
4. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 1, wherein:
the bleeder transistor control path comprises an inverter INV1, a transistor and an inverter INV3, wherein the inverter INV1 is connected between a power supply VCC and a ground line GND, the input end of the inverter INV1 is connected with an RC node of a first-stage RC clamping unit, the output end of the inverter is connected with a G stage of the transistor, the input end of the transistor is connected with the ground line GND, the output end of the transistor is connected with the input end of the inverter INV3 after being connected with a resistor R1 and a capacitor C1, and the output end of the inverter INV3 controls the bleeder transistor.
5. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 4, wherein: the transistor is an NMOS transistor MN2, the S-stage of the NMOS transistor MN2 is connected with the input of a resistor R1, a capacitor C1 and an inverter INV3, and the D-stage of the NMOS transistor MN2 is connected with the ground GND.
6. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 5, wherein: the inverter INV1 comprises an NMOS transistor MN1 and a PMOS transistor MP1, wherein the G-stage of the transistor MN1 and the G-stage of the transistor MP1 are both connected with the RC node of the first-stage RC clamp unit, the D-stage of the input end of the transistor MN1 is connected with the ground, the S-stage of the input end of the transistor MP1 is connected with the power VCC, and the S-stage of the output end of the transistor MN1 and the D-stage of the output end of the transistor MP1 are both connected with the G-stage of the transistor MN 2.
7. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 6, wherein: the inverter INV3 comprises an NMOS transistor MN3 and a PMOS transistor MP3, wherein the G-stage of the transistor MN3 and the G-stage of the transistor MP3 are both connected to the output terminals of the second-stage RC clamp unit and the transistor MN2, the D-stage of the input terminal of the transistor MN3 is connected to the ground, the S-stage of the input terminal of the transistor MP3 is connected to the power source VCC, and the S-stage of the output terminal of the transistor MN3 and the D-stage of the output terminal of the transistor MP3 are both connected to the bleeder transistor.
8. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 7, wherein: the bleeder transistor is an NMOS transistor MN0, the G-level of the transistor MN0 is connected with the bleeder transistor for controlling on, the D-level ground wire GND of the transistor MN0, and the S-level of the transistor MN0 is connected with the power supply VCC.
9. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 8, wherein: the RC constant of the first-stage RC clamping unit is 30 nS.
10. The multiple RC clamp ESD protection circuit that allows for fast power up of claim 9, wherein: the RC constant of the secondary RC clamping unit is 1 uS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921478966.0U CN210350786U (en) | 2019-09-06 | 2019-09-06 | Multiple RC clamp ESD protection circuit allowing fast power-up |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921478966.0U CN210350786U (en) | 2019-09-06 | 2019-09-06 | Multiple RC clamp ESD protection circuit allowing fast power-up |
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| CN210350786U true CN210350786U (en) | 2020-04-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109245078A (en) * | 2018-10-22 | 2019-01-18 | 深圳讯达微电子科技有限公司 | A kind of power clamp circuit for ESD protection |
| CN110445114A (en) * | 2019-09-06 | 2019-11-12 | 深圳讯达微电子科技有限公司 | A kind of multiple RC clamp ESD protective circuit allowing fast powering-up |
-
2019
- 2019-09-06 CN CN201921478966.0U patent/CN210350786U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109245078A (en) * | 2018-10-22 | 2019-01-18 | 深圳讯达微电子科技有限公司 | A kind of power clamp circuit for ESD protection |
| CN110445114A (en) * | 2019-09-06 | 2019-11-12 | 深圳讯达微电子科技有限公司 | A kind of multiple RC clamp ESD protective circuit allowing fast powering-up |
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