CN111276944A - Power tube overcurrent protection circuit - Google Patents
Power tube overcurrent protection circuit Download PDFInfo
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- CN111276944A CN111276944A CN202010229573.7A CN202010229573A CN111276944A CN 111276944 A CN111276944 A CN 111276944A CN 202010229573 A CN202010229573 A CN 202010229573A CN 111276944 A CN111276944 A CN 111276944A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
- H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/06—Details with automatic reconnection
- H02H3/066—Reconnection being a consequence of eliminating the fault which caused disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
- H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
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- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a power tube overcurrent protection circuit, which comprises an overcurrent detection circuit, a timing control circuit and an enabling control circuit, wherein the overcurrent detection circuit is used for detecting whether a controlled power tube is in overcurrent or not; the timing control circuit and the enabling control circuit jointly control the controlled power tube. The invention can turn off the controlled power tube to protect the controlled power tube when the controlled power tube for controlling whether the load works is over-current.
Description
Technical Field
The invention relates to the field of electronic circuits, in particular to a power tube overcurrent protection circuit.
Background
In the field of electronic circuits, a power tube is often used as a switching device to control a rear-end load circuit, and whether the rear-end load circuit works or not is controlled by switching on and off of the power tube; in the using process, if the load has the conditions of short circuit and the like, so that the current of the power tube is overlarge, the power tube is easy to damage, and the whole circuit cannot work.
Disclosure of Invention
The invention aims to provide a power tube overcurrent protection circuit which can shut off a controlled power tube to protect the controlled power tube when the controlled power tube has overcurrent.
In order to achieve the above purpose, the solution of the invention is:
a power tube overcurrent protection circuit is applied to a power tube control circuit, and the power tube control circuit comprises a load and a controlled power tube for controlling whether the load works or not; the power tube of the power tube overcurrent protection circuit comprises:
the overcurrent detection circuit is connected with the controlled power tube; the overcurrent detection circuit is used for detecting whether the controlled power tube is in overcurrent or not; if the controlled power tube is over-current, the output end of the over-current detection circuit outputs an over-current signal; if the controlled power tube has no overcurrent, the output end of the overcurrent detection circuit outputs a normal signal;
the timing control circuit is connected with the output end of the over-current detection circuit; when the timing control circuit is powered on, the output end of the timing control circuit outputs a starting signal; after the timing control circuit is powered on, controlling a signal at the output end of the timing control circuit according to a signal output by the output end of the over-current detection circuit; if the output end of the over-current detection circuit outputs an over-current signal, the output end of the timing control circuit continuously outputs a turn-off signal within the set time and outputs a turn-on signal again after the set time is reached; if the output end of the over-current detection circuit outputs a normal signal, the output end of the timing control circuit keeps outputting a starting signal;
the enabling control circuit is connected with the output end of the timing control circuit and the grid electrode of the controlled power tube respectively; the enabling control circuit is used for controlling the on-off of the controlled power tube and is controlled by a signal output by the output end of the timing control circuit and an enabling signal; the enabling control circuit turns off the controlled power tube as long as the enabling control circuit receives a turn-off signal output by the timing control circuit; and when the enabling control circuit receives the effective enabling signal and the starting signal output by the timing control circuit at the same time, the enabling control circuit starts the controlled power tube.
The timing control circuit is connected with the over-current detection circuit through the signal conversion circuit; the overcurrent signal is a low level signal, and the normal signal is a high level signal; the input end of the signal conversion circuit is connected with the output end of the over-current detection circuit; the signal conversion circuit is used for carrying out level conversion on a signal output by the output end of the over-current detection circuit, converting a high-level normal signal into a low-level holding signal and outputting the low-level holding signal to the input end of the timing control circuit, and converting a low-level over-current signal into a high-level trigger signal and outputting the high-level trigger signal to the input end of the timing control circuit; the input end of the timing control circuit is connected with the output end of the signal conversion circuit; after the timing control circuit is powered on, if the input end of the timing control circuit receives a holding signal, the output end of the timing control circuit keeps outputting a starting signal; and if the signal received by the input end of the timing control circuit is changed from the holding signal to the trigger signal, the output end of the timing control circuit continuously outputs a turn-off signal within the set time and outputs a turn-on signal again after the set time is reached.
The controlled power tube is a PMOS tube, the source electrode of the controlled power tube is connected with a first direct current power supply, and the drain electrode of the controlled power tube is connected with the load; the over-current detection circuit comprises a second switching tube, a second current source and a comparator; the second switching tube is a PMOS tube, and the transconductance of the second switching tube is smaller than that of the controlled power tube; the source electrode of the second switching tube is connected with the first direct-current power supply, the grid electrode of the second switching tube is connected with the grid electrode of the controlled power tube and the output end of the enabling control circuit, and the drain electrode of the second switching tube is connected with the negative input end of the comparator and is grounded through a second current source; the positive input end of the comparator is connected with the drain electrode of the controlled power tube, the output end of the comparator is used as the output end of the over-current detection circuit, the power supply end of the comparator is connected with the first direct-current power supply, and the grounding end of the comparator is connected with the virtual ground circuit.
The virtual ground circuit comprises a fourth switch tube, a fourth resistor, a third current source and a fourth current source, wherein the fourth switch tube is a PMOS tube; one end of the fourth resistor is connected with the first direct-current power supply, the other end of the fourth resistor is connected with the input end of the third current source and the grid electrode of the fourth switch tube, the source electrode of the fourth switch tube is connected with the grounding end of the comparator, the drain electrode of the fourth switch tube is connected with the input end of the fourth current source, and the output end of the third current source and the output end of the fourth current source are grounded.
The signal conversion circuit comprises a third switching tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmidt trigger, wherein the third switching tube is a PMOS tube; the source electrode of the third switching tube is connected with a first direct-current power supply, the grid electrode of the third switching tube serves as the input end of the signal conversion circuit, the drain electrode of the third switching tube is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected with the input end of the Schmitt trigger and is grounded through the first capacitor, and the output end of the Schmitt trigger serves as the output end of the signal conversion circuit.
The enabling control circuit comprises an AND gate, a first current source, a current-limiting resistor and a first switching tube, and the first switching tube is an NMOS tube; the first input end of the AND gate is used for accessing an enabling signal, the second input end of the AND gate is used for connecting the output end of the timing control circuit, and the output end of the AND gate is connected with the grid electrode of the first switching tube; one end of the current-limiting resistor is connected with a first direct-current power supply, the other end of the current-limiting resistor is connected with a drain electrode of a first switch tube, and a source electrode of the first switch tube is grounded through a first current source; and the common end of the current limiting resistor and the first switching tube is used as the output end of the enabling control circuit and is connected with the grid electrode of the controlled power tube.
The controlled power tube is an NMOS tube, the input end of the load is connected with a first direct current power supply, the drain electrode of the controlled power tube is connected with the output end of the load, and the source electrode of the controlled power tube is grounded; the over-current detection circuit comprises a second switching tube, a second current source and a comparator; the second switching tube is an NMOS tube, and the transconductance of the second switching tube is smaller than that of the controlled power tube; the input end of the second current source is connected with the first direct-current power supply, the output end of the second current source is connected with the drain electrode of the second switching tube and the positive input end of the comparator, the grid electrode of the second switching tube is connected with the grid electrode of the controlled power tube and the output end of the enabling control circuit, and the source electrode of the second switching tube is grounded; the negative input end of the comparator is connected with the drain electrode of the controlled power tube, the power supply end of the comparator is connected with a second direct-current power supply, and the grounding end of the comparator is grounded.
The signal conversion circuit comprises a third switching tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmidt trigger, wherein the third switching tube is a PMOS tube; the source electrode of the third switching tube is connected with the second direct-current power supply, the grid electrode of the third switching tube serves as the input end of the signal conversion circuit, the drain electrode of the third switching tube is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected with the input end of the Schmitt trigger and is grounded through the first capacitor, and the output end of the Schmitt trigger serves as the output end of the signal conversion circuit.
The enabling control circuit comprises an AND gate; the first input end of the AND gate is used for accessing an enabling signal, the second input end of the AND gate is used for connecting the output end of the timing control circuit, and the output end of the AND gate serving as the output end of the enabling control circuit is connected with the grid of the controlled power tube.
The timing control circuit comprises a D trigger and a counter; the input end of the D trigger is connected with the second direct-current power supply, the clock end of the D trigger is connected with the enable end of the counter and serves as the input end of the timing control circuit, the output end of the counter is connected with the reset end of the D trigger, and the negative output end of the D trigger serves as the output end of the timing control circuit.
After the scheme is adopted, when the controlled power tube is subjected to overcurrent, the timing control circuit can output a turn-off signal to the enable control circuit, so that the enable control circuit turns off the controlled power tube, overcurrent protection is realized, and the controlled power tube is prevented from being damaged due to overlarge current. In addition, after the controlled power tube is over-current, the timing control circuit continuously outputs a turn-off signal to the enable control circuit within a set time, and then outputs a turn-on signal to the enable control circuit again, so that the enable control circuit can control the controlled power tube to be turned on again, and the controlled power tube is automatically restarted; after the controlled power tube is started again, if the controlled power tube is not in overcurrent, the controlled power tube works normally to enable the circuit to recover a normal working state, and if the controlled power tube is still in overcurrent, the timing control circuit and the enabling control circuit can turn off the controlled power tube again to protect the controlled power tube.
Drawings
FIG. 1 is a schematic circuit diagram of a first embodiment of the present invention;
FIG. 2 is a schematic circuit diagram according to a second embodiment of the present invention;
description of reference numerals:
an overcurrent detection circuit 1, a second switch tube Q2, a second current source I2, a comparator U2,
a virtual ground circuit 11, a fourth switch tube Q4, a fourth resistor R4, a third current source I3, a fourth current source I4,
a timing control circuit 2, a D flip-flop U4, a counter U5,
an enable control circuit 3, an AND gate U1, a first current source I1, a current limiting resistor RT, a first switch tube Q1,
a signal conversion circuit 4, a third switch tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a Schmitt trigger U3,
power tube control circuit 5, load 51, controlled power tube M1,
a first dc power supply VDD, a second dc power supply VCC, an enable signal EN.
Detailed Description
As shown in fig. 1 and fig. 2, the present invention discloses a power tube overcurrent protection circuit, which is applied in a power tube control circuit 5, wherein the power tube control circuit 5 includes a load 51 and a controlled power tube M1 for controlling whether the load 51 operates or not.
Referring to fig. 1 and 2, a power tube of an overcurrent protection circuit of a power tube of the present invention includes an overcurrent detection circuit 1, a timing control circuit 2, and an enable control circuit 3.
With reference to fig. 1 and fig. 2, the overcurrent detecting circuit 1 is connected to the controlled power transistor M1, and the overcurrent detecting circuit 1 is configured to detect whether the controlled power transistor M1 is overcurrent; if the controlled power tube is over-current, the output end of the over-current detection circuit 1 outputs an over-current signal; if the controlled power transistor M1 has no overcurrent, the output terminal of the overcurrent detecting circuit 1 outputs a normal signal.
As shown in fig. 1 and fig. 2, the timing control circuit 2 is connected to an output terminal of the over-current detection circuit 1, and when the timing control circuit 2 is powered on, the output terminal of the timing control circuit 2 outputs a start signal; after the timing control circuit 2 is powered on, the output end signal of the timing control circuit 2 is controlled according to the signal output by the output end of the over-current detection circuit 1; if the output end of the over-current detection circuit 1 outputs an over-current signal, the output end of the timing control circuit 2 continuously outputs a turn-off signal within a set time and outputs a turn-on signal again after the set time is reached; if the output end of the over-current detection circuit 1 outputs a normal signal, the output end of the timing control circuit 2 keeps outputting the start signal. Referring to fig. 1 and 2, the over-current signal is a low level signal, and the normal signal is a high level signal; the timing control circuit 2 can be connected with the over-current detection circuit 1 through a signal conversion circuit 4; the input end of the signal conversion circuit 4 is connected with the output end of the over-current detection circuit 1; the signal conversion circuit 4 is used for performing level conversion on a signal output by the output end of the over-current detection circuit 1, the signal conversion circuit 4 converts a high-level normal signal into a low-level holding signal and outputs the low-level holding signal to the input end of the timing control circuit 2, and the signal conversion circuit 4 converts a low-level over-current signal into a high-level trigger signal and outputs the high-level trigger signal to the input end of the timing control circuit 2; the input end of the timing control circuit 2 is connected with the output end of the signal conversion circuit 4; after the timing control circuit 2 is powered on, if the input end of the timing control circuit 2 receives a holding signal, the output end of the timing control circuit 2 keeps outputting a starting signal; if the signal received by the input terminal of the timing control circuit 2 changes from the hold signal to the trigger signal, the output terminal of the timing control circuit 2 continuously outputs a turn-off signal within the set time and outputs a turn-on signal again after the set time is reached.
As shown in fig. 1 and fig. 2, the enable control circuit 3 is connected to the output terminal of the timing control circuit 2 and the gate of the controlled power transistor respectively; the enabling control circuit 3 is used for controlling the on-off of the controlled power tube M1, and the enabling control circuit 3 is controlled by a signal output by the output end of the timing control circuit 2 and an enabling signal EN; wherein, as long as the enabling control circuit 3 receives the turn-off signal output by the timing control circuit 2, the enabling control circuit 3 turns off the controlled power tube M1; when the enable control circuit 3 receives the active enable signal EN and the enable signal output by the timing control circuit 2 at the same time, the enable control circuit 3 turns on the controlled power transistor M1.
With reference to fig. 1 and 2, the working principle of the present invention is as follows:
when the invention starts to work, the timing control circuit 2 outputs a starting signal to the enabling control signal, and meanwhile, the enabling control circuit 3 receives an effective enabling signal EN, so that the enabling control circuit 3 controls the controlled power tube M1 to be started;
after the controlled power tube M1 is turned on, if the current of the controlled power tube M1 is normal, the over-current detection circuit 1 outputs a normal signal to the signal conversion circuit 4, the circuit conversion circuit converts the received normal signal into a holding signal and outputs the holding signal to the timing control circuit 2, the input end of the timing control circuit 2 receives the holding signal and keeps outputting a turn-on signal to the enable control circuit 3, so that the controlled power tube M1 is ensured to be turned on;
after the controlled power tube M1 is turned on, if the controlled power tube M1 is over-current, the over-current detection circuit 1 outputs an over-current signal to the signal conversion circuit 4, the circuit conversion circuit converts the received over-current signal into a trigger signal and outputs the trigger signal to the timing control circuit 2, the signal received by the input end of the timing control circuit 2 is changed from the hold signal to the trigger signal, the timing control circuit 2 outputs a turn-off signal to the enable control circuit 3 within a set time, so that the enable control circuit 3 turns off the controlled power tube M1, thereby realizing over-current protection and avoiding the damage of the controlled power tube M1 due to over-large current; after the timing control circuit 2 outputs a turn-off signal to the enable control circuit 3 within a set time, the timing control circuit 2 outputs a turn-on signal to the enable control circuit 3 again, so that the enable control circuit 3 can control the controlled power tube M1 to be turned on again, and the controlled power tube M1 is restarted; after the controlled power tube M1 is turned on again, if the controlled power tube M1 has no overcurrent, the controlled power tube M1 operates normally to make the circuit return to a normal operating state, and if the controlled power tube M1 still has overcurrent, the timing control circuit 2 and the enabling control circuit 3 turn off the controlled power tube M1 again to protect the controlled power tube M1.
In order to further explain the technical solution of the present invention, the present invention is explained in detail by two embodiments below.
The first embodiment is as follows:
as shown in fig. 1, in the first embodiment of the invention, the controlled power transistor M1 of the power transistor control circuit 5 is a PMOS transistor, the source of the controlled power transistor M1 is connected to a first dc power source VDD, and the drain of the controlled power transistor M1 is connected to the load 51.
As shown in fig. 1, in the first embodiment of the present invention, the over-current detection circuit 1 includes a second switching transistor Q2, a second current source I2 and a comparator U2, the second switching transistor Q2 is a PMOS transistor, and a transconductance of the second switching transistor Q2 is smaller than a transconductance of the controlled power transistor M1; the source of the second switching tube Q2 is connected to the first dc power supply VDD, the gate of the second switching tube Q2 is connected to the gate of the controlled power tube M1 and the output end of the enable control circuit 3, and the drain of the second switching tube Q2 is connected to the negative input end of the comparator U2 and is grounded through the second current source I2; the positive input end of the comparator U2 is connected with the output end of the controlled power tube M1, and the output end of the comparator U2 is used as the output end of the over-current detection circuit 1 and is connected with the signal conversion circuit 4; thus, when the enable control circuit 3 controls the controlled power transistor M1 to be turned on, the second switch transistor Q2 is also turned on synchronously; when the enable control circuit 3 controls the controlled power tube M1 to turn off, the second switch tube Q2 can also be turned off synchronously, thereby reducing the energy consumption. In addition, since the sources of the second switching tube Q2 and the controlled power tube M1 are both connected to the first direct current power source VDD, the gates of the second switching tube Q2 and the controlled power tube M1 are both connected to the output end of the enable control circuit 3, and the second switching tube Q2 and the controlled power tube M1 are field effect tubes of the same type, when the controlled power tube M1 and the second switching tube Q2 are turned on, if the drain voltages of the controlled power tube M1 and the second switching tube Q2 are equal, that is, the positive input voltage of the comparator U2 is equal to the negative input voltage of the comparator U2, at this time, the current of the controlled power tube M1 is N times the current of the second switching tube Q2, and N is equal to the transconductance voltage of the controlled power tube M1 divided by the transconductance voltage of the second switching tube Q2; if the drain voltage of the controlled power tube M1 is less than the drain voltage of the second switching tube Q2, that is, the voltage of the positive input end of the comparator U2 is less than the voltage of the negative input end of the comparator U2, the current of the controlled power tube M1 is N times greater than the current of the second switching tube Q2, and the comparator U2 outputs a low-level overcurrent signal; if the drain voltage of the controlled power transistor M1 is greater than the drain voltage of the second switching transistor Q2, that is, the voltage of the positive input terminal of the comparator U2 is greater than the voltage of the negative input terminal of the comparator U2, the current of the controlled power transistor M1 is less than N times of the current of the second switching transistor Q2, and the comparator U2 outputs a high-level normal signal; thus, the N times of the current of the second switching tube Q2 is set to be the overcurrent threshold of the controlled power tube M1, when the controlled power tube M1 does not have overcurrent, the current of the controlled power tube M1 is smaller than the overcurrent threshold, the voltage of the positive input end of the comparator U2 is larger than the voltage of the negative input end of the comparator U2, and at this time, the comparator U2 outputs a high-level normal signal; if the current of the controlled power tube M1 is greater than the overcurrent threshold when the controlled power tube M1 is overcurrent, the voltage at the positive input end of the comparator U2 is less than the voltage at the negative input end of the comparator U2, and at this time, the comparator U2 outputs an overcurrent signal with a low level.
As shown in fig. 1, in the first embodiment of the present invention, a power terminal of a comparator U2 of the over-current detection circuit 1 is connected to a first dc power supply VDD, and a ground terminal of a comparator U2 is connected to a circuit of a dashed-line ground; the virtual ground circuit 11 comprises a fourth switching tube Q4, a fourth resistor R4, a third current source I3 and a fourth current source I4, wherein the fourth switching tube Q4 is a PMOS tube; one end of a fourth resistor R4 is connected with a first direct-current power supply VDD, the other end of the fourth resistor R4 is connected with the input end of a third current source I3 and the grid electrode of a fourth switching tube Q4, the source electrode of the fourth switching tube Q4 is connected with the grounding end of a comparator U2, the drain electrode of the fourth switching tube Q4 is connected with the input end of the fourth current source I4, and the output end of the third current source I3 and the output end of the fourth current source I4 are grounded; thus, the ground terminal voltage Vgnd = VDD-I3 × R4+ Vgs of the comparator U2, where VDD is the voltage of the first dc power VDD, I3 is the current of the third current source I3, R4 is the resistance of the fourth resistor R4, and Vgs is the source-gate voltage when the fourth switching tube Q4 is turned on, so that the voltage difference Vu2= I3 × R4-Vgs between the power terminal and the ground terminal of the comparator U2 can be obtained, and thus by setting the current of the third current source I3 and the resistance of the fourth resistor R4, the comparator U2 can operate in a low voltage region (the low voltage region is a voltage lower than 5V) lower than the voltage of the first dc power VDD, so that the comparator U2 can adopt a low voltage device, and the voltage of the first dc power VDD can be a high voltage higher than 60V.
As shown in fig. 1, in the first embodiment of the present invention, the signal conversion circuit 4 includes a third switch tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a schmitt trigger U3, where the third switch tube Q3 is a PMOS tube; the source of the third switching tube Q3 is connected to the first dc power source VDD, the gate of the third switching tube Q3 is used as the input terminal of the signal conversion circuit 4 and is connected to the output terminal of the over-current detection circuit 1, the drain of the third switching tube Q3 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the third resistor R3 and is grounded through the second resistor R2, the other end of the third resistor R3 is connected to the input terminal of the schmitt trigger U3 and is grounded through the first capacitor C1, and the output terminal of the schmitt trigger U3 is used as the output terminal of the signal conversion circuit 4. Thus, when a normal signal with a high level is input into the signal conversion circuit 4, the third switching tube Q3 is turned off to make the voltage at the input end of the schmitt trigger U3 be a low level, so that the output end of the schmitt trigger U3 outputs a holding signal with a low level; when a low-level overcurrent signal is input into the signal conversion circuit 4, the third switching tube Q3 is turned on to make the voltage at the input end of the schmitt trigger U3 be at a high level, so that the output end of the schmitt trigger U3 outputs a high-level trigger signal; the Schmitt trigger U3 can work in a low-voltage area lower than the voltage of a first direct-current power supply VDD by performing voltage division operation through the first resistor R1 and the second resistor R2, and further the timing control circuit 2 at the rear end can work in a low-voltage area lower than the voltage of the first direct-current power supply VDD, so that the Schmitt trigger U3 and the timing control circuit 2 can adopt low-voltage devices; in addition, the voltages of the output holding signal and the trigger signal can be stabilized by the schmitt trigger U3.
As shown in fig. 1, in the first embodiment of the present invention, the timing control circuit 2 includes a D flip-flop U4 and a counter U5; the initial state of the positive output end of the D trigger U4 is low level; the input end of the D flip-flop U4 is connected to a second dc power VCC, the voltage of the second dc power VCC may be lower than the voltage of the first dc power VDD, the clock end of the D flip-flop U4 is connected to the enable end of the counter U5 and serves as the input end of the timing control circuit 2, the output end of the counter U5 is connected to the reset end of the D flip-flop U4, and the negative output end of the D flip-flop U4 serves as the output end of the timing control circuit 2 and is connected to the enable control circuit 3; thus, when the timing control circuit 2 is powered on, the negative output end of the D flip-flop U4 outputs a high-level start signal; when the signal received by the input terminal of the timing control circuit 2 changes from the hold signal to the trigger signal, that is, when the signal received by the input terminal of the timing control circuit 2 generates a rising edge, the D flip-flop U4 is triggered, so that the negative output terminal of the D flip-flop U4 outputs a low-level off signal, at the same time, the counter U5 starts counting, after the set time has elapsed, the counter U5 outputs a signal to the reset terminal of the D flip-flop U4 to reset the D flip-flop U4, and the negative output terminal of the D flip-flop U4 outputs a high-level on signal again.
As shown in fig. 1, in the first embodiment of the present invention, the enable control circuit 3 includes an and gate U1, a first current source I1, a current-limiting resistor RT, and a first switch tube Q1, where the first switch tube Q1 is an NMOS tube; a first input end of the and gate U1 is used for accessing an enable signal EN, a second input end of the and gate U1 is used for connecting an output end of the timing control circuit 2 and accessing an output signal of the timing control circuit 2, and an output end of the and gate U1 is connected with a gate of the first switching tube Q1; one end of a current-limiting resistor RT is connected with a first direct-current power supply VDD, the other end of the current-limiting resistor RT is connected with the drain electrode of a first switch tube Q1, and the source electrode of a first switch tube Q1 is grounded through a first current source I1; the common end of the current limiting resistor RT and the first switch tube Q1 is used as the output end of the enabling control circuit 3 and is connected with the grid electrode of the controlled power tube M1; when the first input end and the second input end of the and gate U1 are respectively connected to the enable signal EN of high level and the start signal of high level, the and gate U1 outputs high level to the first switch tube Q1 to turn on the first switch tube Q1, and further controls the controlled power tube M1 and the second switch tube Q2 to be turned on; when the second input terminal of the and gate U1 receives a low-level turn-off signal, the and gate U1 outputs a low level to the first switching transistor Q1 to turn off the first switching transistor Q1, thereby controlling the controlled power transistor M1 and the second switching transistor Q2 to turn off.
Example two:
referring to fig. 2, in the second embodiment of the present invention, the controlled power transistor M1 of the power transistor control circuit 5 is an NMOS transistor, the input terminal of the load 51 is connected to a first dc power VDD, the output terminal of the load 51 is connected to the drain of the controlled power transistor M1, and the source of the controlled power transistor M1 is grounded.
As shown in fig. 2, in the second embodiment of the present invention, the over-current detection circuit 1 includes a second switching tube Q2, a second current source I2 and a comparator U2, the second switching tube Q2 is an NMOS tube, and a transconductance of the second switching tube Q2 is smaller than a transconductance of the controlled power tube M1; the input end of the second current source I2 is connected to the first direct current power supply VDD, the output end of the second current source I2 is connected to the drain of the second switching tube Q2 and the positive input end of the comparator U2, the gate of the second switching tube Q2 is connected to the gate of the controlled power tube M1 and the output end of the enable control circuit 3, and the source of the second switching tube Q2 is grounded; the negative input end of the comparator U2 is connected with the drain electrode of the controlled power tube M1, the power supply end of the comparator U2 is connected with a second direct-current power supply VCC, and the grounding end of the comparator U2 is grounded; thus, when the enable control circuit 3 controls the controlled power transistor M1 to be turned on, the second switch transistor Q2 is also turned on synchronously; when the enable control circuit 3 controls the controlled power tube M1 to turn off, the second switch tube Q2 can also be turned off synchronously, thereby reducing the energy consumption. In addition, as the sources of the second switching tube Q2 and the controlled power tube M1 are both grounded, the input ends of the load 51 and the second current source I2 are both connected to the first direct current power source VDD, the gates of the second switching tube Q2 and the controlled power tube M1 are both connected to the output end of the enable control circuit 3, and the second switching tube Q2 and the controlled power tube M1 are field effect tubes of the same type, so when the controlled power tube M1 and the second switching tube Q2 are turned on, if the drain voltages of the controlled power tube M1 and the second switching tube Q2 are equal, the positive input end voltage of the comparator U2 is equal to the negative input end voltage of the comparator U2, and at this time, the current of the controlled power tube M1 is N times the current of the second switching tube Q2, and N is equal to the transconductance of the controlled power tube M1 divided by the terminal voltage of the second switching tube Q2; if the drain voltage of the controlled power tube M1 is greater than the drain voltage of the second switching tube Q2, that is, the voltage of the positive input end of the comparator U2 is less than the voltage of the negative input end of the comparator U2, the current of the controlled power tube M1 is greater than N times of the current of the second switching tube Q2, and the comparator U2 outputs a low-level overcurrent signal; if the drain voltage of the controlled power transistor M1 is lower than the drain voltage of the second switching transistor Q2, that is, the voltage of the positive input terminal of the comparator U2 is higher than the voltage of the negative input terminal of the comparator U2, the current of the controlled power transistor M1 is lower than N times of the current of the second switching transistor Q2, and the comparator U2 outputs a high-level normal signal; thus, the N times of the current of the second switching tube Q2 is set to be the overcurrent threshold of the controlled power tube M1, when the controlled power tube M1 does not have overcurrent, the current of the controlled power tube M1 is smaller than the overcurrent threshold, the voltage of the positive input end of the comparator U2 is larger than the voltage of the negative input end of the comparator U2, and at this time, the comparator U2 outputs a high-level normal signal; if the current of the controlled power tube M1 is greater than the overcurrent threshold when the controlled power tube M1 is overcurrent, the voltage at the positive input end of the comparator U2 is less than the voltage at the negative input end of the comparator U2, and at this time, the comparator U2 outputs an overcurrent signal with a low level.
As shown in fig. 2, in the second embodiment of the present invention, the signal conversion circuit 4 includes a third switch tube Q3, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a schmitt trigger U3, and the third switch tube Q3 is a PMOS tube; the source of the third switching tube Q3 is connected to the second dc power VCC, the gate of the third switching tube Q3 is used as the input terminal of the signal conversion circuit 4 and connected to the output terminal of the overcurrent detection circuit 1, the drain of the third switching tube Q3 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the third resistor R3 and grounded through the second resistor R2, the other end of the third resistor R3 is connected to the input terminal of the schmitt trigger U3 and grounded through the first capacitor C1, and the output terminal of the schmitt trigger U3 is used as the output terminal of the signal conversion circuit 4. Thus, when a normal signal with a high level is input into the signal conversion circuit 4, the third switching tube Q3 is turned off to make the voltage at the input end of the schmitt trigger U3 be a low level, so that the output end of the schmitt trigger U3 outputs a holding signal with a low level; when a low-level overcurrent signal is input into the signal conversion circuit 4, the third switching tube Q3 is turned on to make the voltage at the input end of the schmitt trigger U3 be at a high level, so that the output end of the schmitt trigger U3 outputs a high-level trigger signal; wherein, the voltage division operation can be carried out through the first resistor R1 and the second resistor R2 to carry out voltage reduction; in addition, the voltages of the output holding signal and the trigger signal can be stabilized by the schmitt trigger U3.
As shown in fig. 2, in the second embodiment of the present invention, the timing control circuit 2 includes a D flip-flop U4 and a counter U5; the initial state of the positive output end of the D trigger U4 is low level; the input end of the D flip-flop U4 is connected to a second dc power VCC, the voltage of the second dc power VCC may be lower than the voltage of the first dc power VDD, the clock end of the D flip-flop U4 is connected to the enable end of the counter U5 and serves as the input end of the timing control circuit 2, the output end of the counter U5 is connected to the reset end of the D flip-flop U4, and the negative output end of the D flip-flop U4 serves as the output end of the timing control circuit 2 and is connected to the enable control circuit 3; thus, when the timing control circuit 2 is powered on, the negative output end of the D flip-flop U4 outputs a high-level start signal; when the signal received by the input terminal of the timing control circuit 2 changes from the hold signal to the trigger signal, that is, when the signal received by the input terminal of the timing control circuit 2 generates a rising edge, the D flip-flop U4 is triggered, so that the negative output terminal of the D flip-flop U4 outputs a low-level off signal, at the same time, the counter U5 starts counting, after the set time has elapsed, the counter U5 outputs a signal to the reset terminal of the D flip-flop U4 to reset the D flip-flop U4, and the negative output terminal of the D flip-flop outputs a high-level on signal again.
As shown in fig. 2, in the second embodiment of the present invention, the enable control circuit 3 includes an and gate U1; a first input end of the and gate U1 is used for accessing the enable signal EN, a second input end of the and gate U1 is used for connecting the output end of the timing control circuit 2 and accessing the output signal of the timing control circuit 2, and an output end of the and gate U1 is connected as the output end of the enable control circuit 3; the enable signal EN is active at a high level, and when the first input end and the second input end of the and gate U1 are respectively connected to the enable signal EN at the high level and the high-level turn-on signal, the and gate U1 outputs the high level to the gates of the controlled power transistor M1 and the second switch transistor Q2, so as to control the controlled power transistor M1 and the second switch transistor Q2 to be turned on; when the second input terminal of the and gate U1 receives a low-level turn-off signal, the and gate U1 outputs a low level to the gates of the controlled power transistor M1 and the second switching transistor Q2, so as to turn off the controlled power transistor M1 and the second switching transistor Q2.
The above embodiments and drawings are not intended to limit the form and style of the present invention, and any suitable changes or modifications thereof by those skilled in the art should be considered as not departing from the scope of the present invention.
Claims (10)
1. A power tube overcurrent protection circuit is applied to a power tube control circuit, the power tube control circuit comprises a load and a controlled power tube for controlling whether the load works or not, and the power tube overcurrent protection circuit is characterized in that:
the power tube of the power tube overcurrent protection circuit comprises:
the overcurrent detection circuit is connected with the controlled power tube; the overcurrent detection circuit is used for detecting whether the controlled power tube is in overcurrent or not; if the controlled power tube is over-current, the output end of the over-current detection circuit outputs an over-current signal; if the controlled power tube has no overcurrent, the output end of the overcurrent detection circuit outputs a normal signal;
the timing control circuit is connected with the output end of the over-current detection circuit; when the timing control circuit is powered on, the output end of the timing control circuit outputs a starting signal; after the timing control circuit is powered on, controlling a signal at the output end of the timing control circuit according to a signal output by the output end of the over-current detection circuit; if the output end of the over-current detection circuit outputs an over-current signal, the output end of the timing control circuit continuously outputs a turn-off signal within the set time and outputs a turn-on signal again after the set time is reached; if the output end of the over-current detection circuit outputs a normal signal, the output end of the timing control circuit keeps outputting a starting signal;
the enabling control circuit is connected with the output end of the timing control circuit and the grid electrode of the controlled power tube respectively; the enabling control circuit is used for controlling the on-off of the controlled power tube and is controlled by a signal output by the output end of the timing control circuit and an enabling signal; the enabling control circuit turns off the controlled power tube as long as the enabling control circuit receives a turn-off signal output by the timing control circuit; and when the enabling control circuit receives the effective enabling signal and the starting signal output by the timing control circuit at the same time, the enabling control circuit starts the controlled power tube.
2. The power tube overcurrent protection circuit of claim 1, wherein: the timing control circuit is connected with the over-current detection circuit through the signal conversion circuit;
the overcurrent signal is a low level signal, and the normal signal is a high level signal;
the input end of the signal conversion circuit is connected with the output end of the over-current detection circuit; the signal conversion circuit is used for carrying out level conversion on a signal output by the output end of the over-current detection circuit, converting a high-level normal signal into a low-level holding signal and outputting the low-level holding signal to the input end of the timing control circuit, and converting a low-level over-current signal into a high-level trigger signal and outputting the high-level trigger signal to the input end of the timing control circuit;
the input end of the timing control circuit is connected with the output end of the signal conversion circuit; after the timing control circuit is powered on, if the input end of the timing control circuit receives a holding signal, the output end of the timing control circuit keeps outputting a starting signal; and if the signal received by the input end of the timing control circuit is changed from the holding signal to the trigger signal, the output end of the timing control circuit continuously outputs a turn-off signal within the set time and outputs a turn-on signal again after the set time is reached.
3. The power tube overcurrent protection circuit of claim 2, wherein: the controlled power tube is a PMOS tube, the source electrode of the controlled power tube is connected with a first direct current power supply, and the drain electrode of the controlled power tube is connected with the load;
the over-current detection circuit comprises a second switching tube, a second current source and a comparator; the second switching tube is a PMOS tube, and the transconductance of the second switching tube is smaller than that of the controlled power tube; the source electrode of the second switching tube is connected with the first direct-current power supply, the grid electrode of the second switching tube is connected with the grid electrode of the controlled power tube and the output end of the enabling control circuit, and the drain electrode of the second switching tube is connected with the negative input end of the comparator and is grounded through a second current source; the positive input end of the comparator is connected with the drain electrode of the controlled power tube, the output end of the comparator is used as the output end of the over-current detection circuit, the power supply end of the comparator is connected with the first direct-current power supply, and the grounding end of the comparator is connected with the virtual ground circuit.
4. The power tube overcurrent protection circuit of claim 3, wherein: the virtual ground circuit comprises a fourth switch tube, a fourth resistor, a third current source and a fourth current source, wherein the fourth switch tube is a PMOS tube; one end of the fourth resistor is connected with the first direct-current power supply, the other end of the fourth resistor is connected with the input end of the third current source and the grid electrode of the fourth switch tube, the source electrode of the fourth switch tube is connected with the grounding end of the comparator, the drain electrode of the fourth switch tube is connected with the input end of the fourth current source, and the output end of the third current source and the output end of the fourth current source are grounded.
5. The power tube overcurrent protection circuit of claim 3, wherein: the signal conversion circuit comprises a third switching tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmidt trigger, wherein the third switching tube is a PMOS tube;
the source electrode of the third switching tube is connected with a first direct-current power supply, the grid electrode of the third switching tube serves as the input end of the signal conversion circuit, the drain electrode of the third switching tube is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected with the input end of the Schmitt trigger and is grounded through the first capacitor, and the output end of the Schmitt trigger serves as the output end of the signal conversion circuit.
6. The power tube overcurrent protection circuit of claim 3, wherein: the enabling control circuit comprises an AND gate, a first current source, a current-limiting resistor and a first switching tube, and the first switching tube is an NMOS tube; the first input end of the AND gate is used for accessing an enabling signal, the second input end of the AND gate is used for connecting the output end of the timing control circuit, and the output end of the AND gate is connected with the grid electrode of the first switching tube; one end of the current-limiting resistor is connected with a first direct-current power supply, the other end of the current-limiting resistor is connected with a drain electrode of a first switch tube, and a source electrode of the first switch tube is grounded through a first current source; and the common end of the current limiting resistor and the first switching tube is used as the output end of the enabling control circuit and is connected with the grid electrode of the controlled power tube.
7. The power tube overcurrent protection circuit of claim 2, wherein: the controlled power tube is an NMOS tube, the input end of the load is connected with a first direct current power supply, the drain electrode of the controlled power tube is connected with the output end of the load, and the source electrode of the controlled power tube is grounded;
the over-current detection circuit comprises a second switching tube, a second current source and a comparator; the second switching tube is an NMOS tube, and the transconductance of the second switching tube is smaller than that of the controlled power tube; the input end of the second current source is connected with the first direct-current power supply, the output end of the second current source is connected with the drain electrode of the second switching tube and the positive input end of the comparator, the grid electrode of the second switching tube is connected with the grid electrode of the controlled power tube and the output end of the enabling control circuit, and the source electrode of the second switching tube is grounded; the negative input end of the comparator is connected with the drain electrode of the controlled power tube, the power supply end of the comparator is connected with a second direct-current power supply, and the grounding end of the comparator is grounded.
8. The power tube overcurrent protection circuit of claim 7, wherein: the signal conversion circuit comprises a third switching tube, a first resistor, a second resistor, a third resistor, a first capacitor and a Schmidt trigger, wherein the third switching tube is a PMOS tube;
the source electrode of the third switching tube is connected with the second direct-current power supply, the grid electrode of the third switching tube serves as the input end of the signal conversion circuit, the drain electrode of the third switching tube is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the third resistor and is grounded through the second resistor, the other end of the third resistor is connected with the input end of the Schmitt trigger and is grounded through the first capacitor, and the output end of the Schmitt trigger serves as the output end of the signal conversion circuit.
9. The power tube overcurrent protection circuit of claim 7, wherein: the enabling control circuit comprises an AND gate; the first input end of the AND gate is used for accessing an enabling signal, the second input end of the AND gate is used for connecting the output end of the timing control circuit, and the output end of the AND gate serving as the output end of the enabling control circuit is connected with the grid of the controlled power tube.
10. The power tube overcurrent protection circuit of any one of claims 2 to 9, wherein: the timing control circuit comprises a D trigger and a counter; the initial state of the positive output end of the D trigger is low level;
the input end of the D trigger is connected with the second direct-current power supply, the clock end of the D trigger is connected with the enable end of the counter and serves as the input end of the timing control circuit, the output end of the counter is connected with the reset end of the D trigger, and the negative output end of the D trigger serves as the output end of the timing control circuit.
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| CN202010229573.7A CN111276944A (en) | 2020-03-27 | 2020-03-27 | Power tube overcurrent protection circuit |
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| CN202010229573.7A CN111276944A (en) | 2020-03-27 | 2020-03-27 | Power tube overcurrent protection circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111901923A (en) * | 2020-08-03 | 2020-11-06 | 四川遂宁市利普芯微电子有限公司 | Overcurrent protection circuit of common-cathode LED display line driving chip |
| CN112491012A (en) * | 2021-02-03 | 2021-03-12 | 四川蕊源集成电路科技有限公司 | Current-limiting double-protection circuit and current-limiting double-protection method of circuit |
| WO2022007523A1 (en) * | 2020-07-09 | 2022-01-13 | 深圳市创芯微微电子有限公司 | Battery protection circuit |
| CN116027097A (en) * | 2022-12-16 | 2023-04-28 | 无锡中微爱芯电子有限公司 | Overcurrent detection circuit for gate drive |
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2020
- 2020-03-27 CN CN202010229573.7A patent/CN111276944A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022007523A1 (en) * | 2020-07-09 | 2022-01-13 | 深圳市创芯微微电子有限公司 | Battery protection circuit |
| CN111901923A (en) * | 2020-08-03 | 2020-11-06 | 四川遂宁市利普芯微电子有限公司 | Overcurrent protection circuit of common-cathode LED display line driving chip |
| CN111901923B (en) * | 2020-08-03 | 2023-10-03 | 四川遂宁市利普芯微电子有限公司 | Overcurrent protection circuit of common-cathode LED display line driving chip |
| CN112491012A (en) * | 2021-02-03 | 2021-03-12 | 四川蕊源集成电路科技有限公司 | Current-limiting double-protection circuit and current-limiting double-protection method of circuit |
| CN112491012B (en) * | 2021-02-03 | 2021-04-16 | 四川蕊源集成电路科技有限公司 | Current-limiting double-protection circuit and current-limiting double-protection method of circuit |
| CN116027097A (en) * | 2022-12-16 | 2023-04-28 | 无锡中微爱芯电子有限公司 | Overcurrent detection circuit for gate drive |
| CN116027097B (en) * | 2022-12-16 | 2024-04-05 | 无锡中微爱芯电子有限公司 | Overcurrent detection circuit for gate drive |
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