CN114994500A

CN114994500A - Overcurrent detection circuit and overcurrent detection method of high-voltage driving chip

Info

Publication number: CN114994500A
Application number: CN202210552600.3A
Authority: CN
Inventors: 陆扬扬; 张允武; 禹阔; 黄海敏; 孟海迪; 陈启亮; 张大双
Original assignee: State Silicon Integrated Circuit Technology Wuxi Co ltd
Current assignee: State Silicon Integrated Circuit Technology Wuxi Co ltd
Priority date: 2022-05-19
Filing date: 2022-05-19
Publication date: 2022-09-02

Abstract

The application discloses an over-current detection circuit and an over-current detection method of a high-voltage driving chip, and belongs to the technical field of integrated circuits. In the circuit, when the falling edge detection circuit detects the falling edge of the floating ground of the high-voltage area and the output of the low-voltage output port is a high-level signal, the logic control circuit is used for outputting the high-level signal to the high-precision voltage detection circuit; when the output of the low-voltage output port is a low-level signal, the logic control circuit is used for outputting the low-level signal to the high-precision voltage detection circuit; the high-precision voltage detection circuit is used for starting over-current detection when receiving a high level signal and closing the over-current detection when receiving a low level signal; the comparator is used for generating an overcurrent detection result according to the detection voltage and the reference voltage. When the overcurrent detection precision can be improved, the problem that the narrow pulse width is missed to be judged easily due to too late detection time is avoided, and the timeliness of overcurrent detection is improved.

Description

Overcurrent detection circuit and overcurrent detection method of high-voltage driving chip

Technical Field

The embodiment of the application relates to the technical field of integrated circuits, in particular to an overcurrent detection circuit and an overcurrent detection method of a high-voltage driving chip.

Background

The power driving circuit is widely applied to the fields of new energy automobiles, motor driving, electronic ballasts, switching power supplies and the like, and can be used for driving two Metal-Oxide-Semiconductor Field-Effect transistors (MOS) or Insulated Gate Bipolar Transistors (IGBTs) connected in a totem-pole manner to be alternately conducted. Since N-type power devices have lower on-resistance and smaller parasitic capacitance than P-type power devices, two N-type power devices are generally used in high voltage applications above 60V to 600V, as shown in fig. 1, M _H Is the above-mentioned high-side switching device, M _L Is the low side switching device described above. High-voltage driver chip is typically used to efficiently drive high-side switching device M _H The high-voltage driving chip comprises a high-voltage area gate driving circuit and a low-voltage area gate driving circuit, LIN is an input signal of the low-voltage area gate driving circuit, HIN is an input signal of the high-voltage area gate driving circuit, and control signals of LIN and HIN are derived from an external microcontroller. LO is the output signal of the low-voltage gate driver circuit, connected to M _L HO is an output signal of the high voltage area gate driving circuit, connected to M _H A gate electrode of (1). The voltage domain from a low-voltage power supply VCC to a low-voltage area ground GND supplies power to a low-voltage area gate drive circuit, the floating voltage domain from a high-voltage side power supply VB to a high-voltage area floating ground VS supplies power to the high-voltage area gate drive circuit, and VS is connected to M _H Source electrode and M _L Of the substrate. Using high-voltage diodes D _B And a bootstrap capacitor C _B Supply power to VB, when M _L When turned on, VCC passes through D _B Is C _B Charging and supplying power for high-voltage area gate drive circuit(ii) a When M is _H When turned on, C _B And the task of supplying power to the high-voltage area gate driving circuit is carried out, and the steps are repeated. An inductor L with one end connected to VS and the other end connected to the output voltage Vout, a capacitor C and a resistor R ₀ And one end of the parallel connection is connected to Vout, and the other end is connected to GND. In the application of high-voltage driving chip, a series resistor R is generally used _SENSE Is connected in series at M _L With the error amplifier as a comparator to compare V with ground _SENSE And the reference voltage Vref, and transmits the obtained over-current signal to the microcontroller, and the microcontroller turns off the transmission signals of the high-voltage side and the low-voltage side after receiving the over-current signal.

In order to solve the problem of overcurrent protection of the high-voltage driving chip, a bidirectional current detection circuit in on-chip integration is proposed in US7548029B2, as shown in fig. 2. The bidirectional current detection circuit comprises a high-voltage power MOSFET M1, medium-voltage and low-voltage MOSFETs M2-M9, Zener diodes D1 and D2, and a resistor R _S1 And a current source I _REF1 And I _REF2 The source electrodes of the PMOS transistor M6 and the PMOS transistor M7 are connected with a low-voltage power supply VCC, and the grid electrode of M6 is connected with the drain electrode of M6, the grid electrode of M7 and I _REF2 M7 with the drain of the NMOS transistor M8, the gate of M8 and the gate of the NMOS transistor M9, and a current source I _REF2 Is connected to the sources of M8 and M9 and the anode of D1 and is connected to GND, and the drain of M9 is connected to the source of M1 and the cathode of D1 and outputs V as an overcurrent detection voltage _SENSE The gate of M1 is connected with a control signal to ensure M _L And the LED is started after being started for a period of time, and overcurrent detection is carried out. The drain of M1 is connected to the source of NMOS transistor M5 and the anode of D2, the gate of M5 is connected to the gate of NMOS transistor M4, the drain of M4 and the drain of PMOS transistor M3, the gate of PMOS transistor M2 is connected to the drain of NMOS transistor M3, the gate of M3 and I _REF1 M5 with the cathode of D2, the sources of M3 and M2 connected to VB, the source of M4 with R _S1 Are connected at one end to R _S1 And the other end of which is connected to the outflow port of IREF1 and is connected to VS. The above-mentioned bidirectional current is examinedThe circuit can effectively integrate the over-current protection circuit into the high-voltage driving chip, but has two problems: (1) the EN end is used as a start port of the overcurrent detection, and must be started after the LO is started and delayed for a period of time, and a large delay time may cause a narrow LO pulse width to fail overcurrent determination, as shown in fig. 3, an excessively short delay time may cause an overcurrent misdetermination due to a high voltage region voltage not being reduced, and finally cause the high voltage driver chip to fail to operate; (2) v _SENSE Is the drain voltage of M1 minus the conduction voltage drop of M1, even with R _S1 The drain voltage of M1 is raised, so that accurate detection is still difficult to achieve, and especially under the very severe environment conditions such as automobile electronics and the like, V _SENSE The detection voltage change is large, the overcurrent is possibly generated but is not detected, the high-voltage driving chip is further damaged, and the overcurrent protection operation is also triggered without overcurrent, so that the false triggering is caused, and the normal work of the high-voltage driving chip is influenced.

Disclosure of Invention

The embodiment of the application provides an overcurrent detection circuit and an overcurrent detection method of a high-voltage driving chip, which are used for solving the problems of detection precision, early detection time, easy misjudgment and short pulse width misjudgment caused by too late detection time. The technical scheme is as follows:

in one aspect, an over-current detection circuit of a high-voltage driving chip is provided, the over-current detection circuit includes: the circuit comprises a falling edge detection circuit, a logic control circuit, a high-precision voltage detection circuit and a comparator;

a first input port in the falling edge detection circuit is connected with a high-voltage side power supply or a high-voltage area in a floating mode, a second input port is connected with a low-voltage power supply, and an output port is connected with a first input port of the logic control circuit;

a second input port in the logic control circuit is connected with a low-voltage output port of the low-voltage area gate driving circuit, a third input port is connected with an output port of the power-on reset circuit, a fourth input port and a power supply port are respectively connected with the low-voltage power supply, a grounding port is connected with a low-voltage area ground, and the output port is connected with a first input port of the high-precision voltage detection circuit;

a second input port in the high-precision voltage detection circuit is connected with the high-voltage area in a floating mode, a power supply port is connected with the low-voltage power supply, a ground port is connected with the low-voltage area in a ground mode, and an output port is connected with a non-inverting input port of the comparator;

an inverting input port in the comparator is connected with a reference voltage, and an output port is connected with the low-voltage area gate driving circuit;

when the falling edge detection circuit detects the falling edge of the high-voltage area floating ground and the output of the low-voltage output port is a high-level signal, the logic control circuit is used for outputting the high-level signal to the high-precision voltage detection circuit; when the output of the low-voltage output port is a low-level signal, the logic control circuit is used for outputting the low-level signal to the high-precision voltage detection circuit;

the high-precision voltage detection circuit is used for starting over-current detection when receiving a high level signal and closing the over-current detection when receiving a low level signal;

the comparator is used for generating an overcurrent detection result according to the detection voltage and the reference voltage.

In one possible implementation, the falling edge detection circuit includes: the capacitive device, the first current source and the diode;

one port of the capacitive device is used as a first input port of the falling edge detection circuit, the other port of the capacitive device is connected with the outflow port of the first current source and the anode of the diode and then used as an output port of the falling edge detection circuit, and the inflow port of the first current source is connected with the cathode of the diode and then used as a second input port of the falling edge detection circuit.

In a possible implementation manner, the capacitive device is any one or a combination of a capacitor, a source-drain parasitic capacitor of an NMOS transistor with a short-circuited gate and a source-drain parasitic capacitor of a PMOS transistor with a short-circuited gate and a source.

In one possible implementation, the logic control circuit includes: the circuit comprises a first AND gate, a second AND gate, a D trigger and a falling edge pulse generating circuit;

two input ports of the first AND gate are respectively used as a second input port and a third input port of the logic control circuit; the output port of the first AND gate is respectively connected with the input port of the falling edge pulse generating circuit and one input port of the second AND gate; the output port of the falling edge pulse generating circuit is connected with the reset port of the D trigger; an input port of the D flip-flop is used as a fourth input port of the logic control circuit; a clock input port of the D flip-flop is used as a first input port of the logic control circuit; the output port of the D flip-flop is connected with the other input port of the second AND gate; the power supply ports of the first AND gate, the second AND gate, the D trigger and the falling edge pulse generating circuit are used as the power supply ports of the logic control circuit; the first AND gate, the second AND gate, the D flip-flop and a ground port of the falling edge pulse generating circuit are used as ground ports of the logic control circuit; and the output port of the second AND gate is used as the output port of the logic control circuit.

In one possible implementation, the falling edge pulse generating circuit includes: second to fifth inverters and a nand gate;

an input port of a second inverter INV2 is used as an input port of the falling edge pulse generating circuit, and an output port of the second inverter is respectively connected with an input port of a third inverter and one input port of the nand gate; an output port of the third inverter is connected with an input port of a fourth inverter, and an output port of the fourth inverter is connected with an input port of a fifth inverter; an output port of the fifth inverter is connected with the other input port of the NAND gate; the output port of the NAND gate is used as the output port of the falling edge pulse generating circuit; and power supply ports of the second to fifth inverters and the NAND gate are used as power supply ports of the falling edge pulse generating circuit, and ground ports of the second to fifth inverters and the NAND gate are used as ground ports of the falling edge pulse generating circuit.

In one possible implementation, the high-precision voltage detection circuit includes: the power supply comprises a first high-voltage power MOSFET, a second current source, a third current source I2, a first inverter and a low-level control switch;

the grid electrode of the first high-voltage power MOSFET is connected with the grid electrode of the second high-voltage power MOSFET and the input port of the first inverter and then serves as a first input port of the high-precision voltage detection circuit; the drain electrode of the first high-voltage power MOSFET is used as a second input port of the high-precision voltage detection circuit; the source electrode of the first high-voltage power MOSFET, the source electrode of the second high-voltage power MOSFET and the inflow port of the third current source are connected; an outflow port of the third current source is connected with one end of the switch controlled to be turned on by the low level and then is used as a grounding port of the high-precision voltage detection circuit; the drain electrode of the second high-voltage power MOSFET is connected with the other end of the switch controlled to be turned on by the low level and the outflow port of the second current source and then serves as the output port of the high-precision voltage detection circuit; an inflow port of the second current source is used as a power supply port of the high-precision voltage detection circuit; and the output port of the first phase inverter is connected with the control port of the switch which is controlled to be turned on by the low level.

In one possible implementation, the current ratio of the second current source to the third current source is 1: 2, the first high-voltage power MOSFET and the second high-voltage power MOSFET have the same size and specification.

In one possible implementation, the comparator includes: first to fifth PMOS tubes and first to fourth NMOS tubes;

a source electrode of the first PMOS tube, a source electrode of the second PMOS tube and a source electrode of the third PMOS tube are connected and then connected to the low-voltage power supply, a grid electrode of the first PMOS tube and a grid electrode of the second PMOS tube are connected with bias voltage respectively, a drain electrode of the first PMOS tube, a source electrode of the fourth PMOS tube and a source electrode of the fifth PMOS tube are connected, a grid electrode of the fourth PMOS tube is used as a same-phase input port of the comparator, a grid electrode of the fifth PMOS tube is used as an opposite-phase input port of the comparator, a drain electrode of the fourth PMOS tube is connected with a grid electrode and a drain electrode of the first NMOS tube and a grid electrode of the second NMOS tube, a source electrode of the first NMOS tube, a source electrode of the second NMOS tube, a source electrode of the third NMOS tube and a source electrode of the fourth NMOS tube are connected and then connected to the low-voltage area, a drain electrode of the fifth PMOS tube, a drain electrode of the second NMOS tube and a grid electrode of the third NMOS tube are connected, a drain electrode of the second PMOS tube and a drain electrode of the second PMOS tube, And the drain electrode of the third NMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth NMOS tube are connected, and the grid electrode of the third PMOS tube and the drain electrode of the fourth NMOS tube are connected and then serve as the output port of the comparator.

In another aspect, an over-current detection method for a high-voltage driver chip is provided, where the over-current detection method is used in the over-current detection circuit, and the method includes:

when the falling edge detection circuit detects the falling edge of the high-voltage area floating ground and the output of the low-voltage output port is a high-level signal, the logic control circuit outputs the high-level signal to the high-precision voltage detection circuit; the high-precision voltage detection circuit starts over-current detection when receiving a high-level signal and sends detection voltage to the comparator;

when the output of the low-voltage output port is a low-level signal, the logic control circuit outputs the low-level signal to the high-precision voltage detection circuit; the high-precision voltage detection circuit turns off overcurrent detection when receiving a low level signal;

and the comparator generates an overcurrent detection result according to the detection voltage and the reference voltage.

In one possible implementation, the detection voltage is equal to the high voltage region floating ground.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

(1) the application utilizes the falling edge detection circuit to detect the high-voltage area in time and then combines the output signal of the low-voltage output port, so that overcurrent detection can be performed in time, the problem that misjudgment is easily formed due to too early detection time, the problem that narrow pulse width is missed in judgment is easily caused due to too late detection time is avoided, and the timeliness of overcurrent detection is improved.

(2) This application utilizes the same size, and same operational environment's high-voltage power MOSFET's on-resistance compensates for detect the precision and improve greatly, and when changing along with temperature variation, technology drift, mains voltage, this compensation effect can not the variation.

(3) The structure directly detects the voltage of the high-voltage area floating ground, and the static power consumption of the high-voltage area can be reduced without an additional circuit of the high-voltage area.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a power driving circuit;

FIG. 2 illustrates an on-chip integrated over-current detection circuit provided in the prior art;

fig. 3 is a waveform diagram of the prior art fig. 2 with LIN outputting wider and narrower pulses;

fig. 4 is a schematic structural diagram of an overcurrent detection circuit provided in the present application;

FIG. 5 is a schematic diagram of the falling edge detection circuit and the logic control circuit shown in FIG. 4;

FIG. 6 is a schematic diagram of the capacitive device of FIG. 5;

FIG. 7 is a schematic diagram of the falling edge pulse generating circuit shown in FIG. 5;

fig. 8 is a waveform diagram illustrating the operation of the over-current detection circuit according to the present invention when the falling edge of the VS voltage lags and the rising edge of the LO voltage;

fig. 9 is a waveform diagram illustrating the operation of the over-current detection circuit provided in the present application when the falling edge of the VS voltage precedes the rising edge of the LO voltage;

FIG. 10 is a schematic diagram of the high-precision voltage detection circuit shown in FIG. 4;

FIG. 11 shows an over-current detection circuit provided in the present application and V of the over-current detection circuit shown in FIG. 2 _SENSE The value varies with the VS voltage;

FIG. 12 is a schematic diagram of the comparator of FIG. 4;

FIG. 13 is a schematic diagram of the over-current detection circuit provided in the present application for detecting the switching signal under the conditions of wide pulse and narrow pulse;

fig. 14 is a flowchart of an overcurrent detection method of a high-voltage driver chip provided in the present application.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail with reference to the accompanying drawings.

Referring to fig. 4, a schematic structural diagram of an over-current detection circuit of a high-voltage driver chip according to an embodiment of the present disclosure is shown. The over-current detection circuit may include: a falling edge detection circuit, a logic control circuit, a high-precision voltage detection circuit, and a comparator, and the connection relationship between these four circuits will be described below.

The falling edge detection circuit comprises two input ports and an output port, wherein a first input port of the falling edge detection circuit is connected with a high-voltage side power supply VB or a high-voltage area floating ground VS, a second input port of the falling edge detection circuit is connected with a low-voltage power supply VCC, and the output port (the output V thereof) _DT ) Is connected to the first input port of the logic control circuit.

The logic control circuit comprises four input ports, two power supply ports and an output port. Wherein a first input port of the logic control circuit (which receives V) _DT ) Connected with the output port of the falling edge detection circuit; the second input port is connected with the low-voltage output port (receiving LO) of the low-voltage area gate drive circuit, the third input port is connected with the output port (receiving POR) of the power-on reset circuit, and the fourth input port (receiving VCC) and the power supply port are respectively connected with low-voltage powerSource VCC, ground port to low-voltage region ground GND, and output port (output V) _G ) And the first input port of the high-precision voltage detection circuit is connected with the first input port of the high-precision voltage detection circuit.

The high-precision voltage detection circuit comprises two input ports, two power supply ports and an output port. Wherein the first input port (which receives V) in the high-precision voltage detection circuit _G ) Is connected with the output port of the logic control circuit; a second input port connected to high-voltage floating ground VS, a power supply port connected to low-voltage power supply VCC, a ground port connected to low-voltage ground GND, and an output port (output V) _SENSE ) Connected to the non-inverting input port of the comparator.

The comparator comprises two input ports and one output port. In which the non-inverting input port in the comparator (which receives V) _SENSE ) The output port of the high-precision voltage detection circuit is connected with the output port of the high-precision voltage detection circuit; inverting input port and reference voltage V _ref And the output port is connected with the low-voltage area gate driving circuit.

In this embodiment, when the falling edge detection circuit detects the falling edge of the high-voltage floating ground VS and the output of the low-voltage output port is a high-level signal (i.e., LO is a high-level signal), the logic control circuit is configured to output the high-level signal (i.e., V) to the high-precision voltage detection circuit _G Is a high level signal); when the output of the low-voltage output port is a low-level signal (i.e., LO is a low-level signal), the logic control circuit is used for outputting a low-level signal (i.e., V) to the high-precision voltage detection circuit _G Is a low level signal); the high-precision voltage detection circuit is used for receiving a high-level signal (namely V) _G Is a high level signal) and a low level signal (i.e., V) is received _G Is a low level signal) to turn off overcurrent detection; the comparator is used for detecting the voltage V according to _SENSE And a reference voltage V _ref And generating an overcurrent detection result.

The circuit configurations of the falling edge detection circuit, the logic control circuit, the high-precision voltage detection circuit, and the comparator will be described below.

(1) The falling edge detection circuit includes: a capacitive device, a first current source I3 and a diode D3, as shown in fig. 5. One port of the capacitive device is used as a first input port of the falling edge detection circuit, the other port of the capacitive device is connected with the outflow port of the first current source I3 and the anode of the diode D3 and then used as an output port of the falling edge detection circuit, and the inflow port of the first current source I3 is connected with the cathode of the diode D3 and then used as a second input port of the falling edge detection circuit.

The capacitive device can be any one or combination of a capacitor, a source-drain parasitic capacitor of an NMOS tube with a short-circuited gate and a source-drain parasitic capacitor of a PMOS tube with a short-circuited gate and source. Referring to fig. 6, (a) in fig. 6 represents capacitance, (b) represents source-drain parasitic capacitance of NMOS transistor with gate-source short circuit, and (c) represents source-drain parasitic capacitance of PMOS transistor with gate-source short circuit.

(2) The logic control circuit includes: a first AND gate AND1, a second AND gate AND2, a D flip-flop, AND a falling edge pulse generation circuit. Two input ports of the first AND gate AND1 are respectively used as a second input port AND a third input port of the logic control circuit; output port of first AND gate AND1 (output V thereof) ₁ ) Connected to the input port of the falling edge pulse generating circuit AND one input port of the second AND gate AND2, respectively; output port of falling edge pulse generating circuit (output V thereof) _R ) Is connected with a Reset port (Reset) of the D flip-flop; an input port (D) of the D flip-flop is used as a fourth input port of the logic control circuit; a clock input port (Clk) of the D flip-flop is used as a first input port of the logic control circuit; output port (Q) of D flip-flop, its output V ₃ ) Is connected with the other input port of the second AND gate AND 2; the power supply ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop AND the falling edge pulse generating circuit are used as the power supply ports of the logic control circuit; the ground ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop AND the falling edge pulse generating circuit are used as the ground ports of the logic control circuit; output port of second AND gate AND2 (output V thereof) _G ) As an output port of the logic control circuit.

Note that the power supply port of the logic control circuit is connected to the low voltage power supply VCC, that is, the power supply ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, AND the falling edge pulse generating circuit are connected to the low voltage power supply VCC, AND the power supply ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, AND the falling edge pulse generating circuit are not shown in fig. 5. The ground ports of the logic control circuit are connected to the low voltage region ground GND, that is, the ground ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, AND the falling edge pulse generating circuit are connected to the low voltage region ground GND, AND the ground ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, AND the falling edge pulse generating circuit are not shown in fig. 5.

The falling edge pulse generating circuit in the present embodiment includes: second-fifth inverters INV2-INV5 and a NAND gate NAND3, as shown in FIG. 7. An input port of the second inverter INV2 is used as an input port of the falling edge pulse generating circuit, and an output port of the second inverter INV2 is respectively connected with an input port of the third inverter INV3 and one input port of the NAND gate NAND 3; an output port of the third inverter INV3 is connected to an input port of the fourth inverter INV4, and an output port of the fourth inverter INV4 is connected to an input port of the fifth inverter INV 5; an output port of the fifth inverter INV5 is connected to another input port of the NAND gate NAND 3; the output port of the NAND gate 3 is used as the output port of the falling edge pulse generating circuit; the power supply ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 serve as the power supply port of the falling edge pulse generating circuit, and the ground port of the second to fifth inverters and the NAND gate NAND3 serve as the ground port of the falling edge pulse generating circuit.

It should be noted that the power interface of the falling edge pulse generating circuit is connected to the low voltage power supply VCC, that is, the power ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 are connected to the low voltage power supply VCC, and the power ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 are not shown in fig. 7. The ground interface of the falling edge pulse generating circuit is connected to the low voltage region ground GND, i.e., the ground ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 are connected to the low voltage region ground GND, and the ground ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 are not shown in FIG. 7.

The operation of the logic control circuit is explained below.

Referring to fig. 8, it shows the waveform diagram of the operation of the over-current detection circuit when the falling edge of the VS voltage lags the rising edge of the LO. After the LO goes high, the low side power transistor M takes a short time _L Is completely turned on, the voltage of VS begins to drop, and the falling edge detection circuit outputs a low-level pulse (V) after detecting the falling edge _DT ) The low level pulse (V) _DT ) Acting on the clock input port (Clk) of the D flip-flop so that the level (VCC) of the input port (D) is transmitted to the output port (Q), i.e. V ₃ Is high. LO remains high at this time _G Is pulled high to trigger the on of the over-current detection. When the LO becomes low level, the falling edge pulse generating circuit outputs a low level pulse (V) _R ) The low level pulse (V) _R ) Acting on the Reset port (Reset) of the D flip-flop so that the output V of the output port ₃ Is set to zero, i.e. V is caused _G Is set to zero, thereby triggering the shutdown of the over-current detection.

Referring to fig. 9, it shows the operating waveform diagram of the over-current detection circuit when the falling edge of the VS voltage precedes the rising edge of the LO. When the inductive current is positive towards the VO direction, the high-side power tube M _H Is turned off due to M _L Is instantaneously pulled to a negative voltage, and the falling edge detection circuit outputs a low level pulse (V) after detecting the falling edge _DT ) The low level pulse (V) _DT ) Acting on the clock input port (Clk) of the D flip-flop so that the level (VCC) of the input port (D) is transmitted to the output port (Q), i.e. V ₃ Is high, V is high until LO goes high ₁ Goes high, V ₁ And V ₃ The high level is considered after AND-gate AND2, namely the output V of AND-gate AND2 _G High, triggering over-current detection. When the LO becomes low level, the falling edge pulse generating circuit outputs a low level pulse (V) _R ) The low level pulse (V) _R ) Acting on the Reset port (Reset) of the D flip-flop so that the output V of the output port ₃ Is set to zero, i.e. V is caused _G Is set to zero, thereby triggering the shutdown of the over-current detection.

(3) The high-precision voltage detection circuit includes: a first high voltage power MOSFET LM1, a second high voltage power MOSFET LM2, a second current source I1, a third current source I2, a first inverter INV1, and a low-level controlled-on switch S1, as shown in fig. 10. The grid electrode of the first high-voltage power MOSFET LM1, the grid electrode of the second high-voltage power MOSFET LM2 and the input port of the first inverter INV1 are connected and then serve as a first input port of the high-precision voltage detection circuit; the drain electrode of the first high-voltage power MOSFET LM1 is used as a second input port of the high-precision voltage detection circuit; the source of the first high-voltage power MOSFET LM1, the source of the second high-voltage power MOSFET LM2 and the inflow port of the third current source I2 are connected (the signal at the node formed after the connection is marked as V1); the outflow port of the third current source I2 is connected with one end of a switch S1 which is controlled to be turned on by low level and then is used as the ground port of the high-precision voltage detection circuit; the drain of the second high-voltage power MOSFET LM2 is connected with the other end of the switch S1 controlled to be turned on by low level and the outflow port of the second current source I1 to be used as the output port of the high-precision voltage detection circuit; the inflow port of the second current source I1 is used as the power supply port of the high-precision voltage detection circuit; an output port of the first inverter INV1 is connected to the control port of the switch S1 which is turned on by low-level control.

In this embodiment, the current ratio between the second current source I1 and the third current source I2 is 1: 2, the first high voltage power MOSFET LM1 and the second high voltage power MOSFET LM2 are the same size and gauge.

Wherein, the formula of the on-resistance of the MOS tube is as follows

Where μ 0 is the carrier mobility, C _ox Is the gate oxide capacitance, W and L are the width and length of the MOS transistor, respectively, V _GS Is the gate-source voltage difference, V, of the MOS transistor _TH Is the threshold voltage of MOS transistor, can obtain

V _SENSE ＝V ₁ +I ₁ ·R _on2 (2)

And also

V ₁ ＝V _S -(I ₂ -I ₁ )·R _on1 (3)

Wherein R is _on1 Is the on-resistance of LM1, R _on2 It is the on-resistance of LM2, and from equation (1), when the size and specification of LM1 and LM2 are the same, the on-resistance of MOS transistor is only related to its gate-source voltage difference, and the source-connected gates of LM1 and LM2 in fig. 10 are connected, so the on-resistance of both is the same, that is, the on-resistance of LM1 and LM2 are the same

R _on1 ＝R _on2 (4)

Due to the fact that

I ₂ ＝2*I ₁ (5)

Substituting and simplifying the equations (3) to (5) into the equation (2) to obtain

V _SENSE ＝VS (6)

Please refer to fig. 11, which shows the over-current detection circuit provided in the present application and the V of the over-current detection circuit in the prior art _SENSE The values are plotted as a function of VS voltage. As can be seen from fig. 11, the voltage V detected in the prior art _SENSE There is a large error between the value and the value VS. When the VS voltage value is larger than 0.3V, the voltage V detected by the overcurrent detection circuit is applied _SENSE The value is wirelessly close to the VS value and changes along with the voltage change of VS, because the sizes and specifications of LM1 and LM2 are the same, so the voltage value V detected by the application _SENSE The relationship to the VS value does not change with changes in temperature and process drift.

(4) The comparator includes: the first to fifth PMOS transistors MP1-MP5 and the first to fourth NMOS transistors MN1-MN4 are shown in FIG. 12. The source of the first PMOS transistor MP1, the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are connected and then connected to a low voltage power supply VCC, the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are connected to a Bias voltage Bias, the drain of the first PMOS transistor MP1, the source of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5 are connected, the gate of the fourth PMOS transistor MP4 is used as an in-phase input port of the comparator, the gate of the fifth PMOS transistor MP5 is used as an inverting input port of the comparator, the drain of the fourth PMOS transistor MP4 is connected to the gate and drain of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2, the source of the first NMOS transistor MN1, the source of the second NMOS transistor MN2, the source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are connected to a low voltage area after the drains of the NMOS transistors MN 5, the drain of the fifth PMOS transistor MP2, the second NMOS transistor MP 5848 and the third NMOS transistor MP 4623 are connected, the drain of the NMOS transistor MN 4624 and the third PMOS transistor MP 57323, and the drain of the NMOS transistor MP 7375 are connected to a drain of the PMOS transistor MN 4623, and the drain of the PMOS transistor MN The gate of the third PMOS transistor MP3 is connected to the gate of the fourth NMOS transistor MN4, and the gate of the third PMOS transistor MP3 is connected to the drain of the fourth NMOS transistor MN4, and then serves as the output port of the comparator.

Please refer to fig. 13, which shows a schematic diagram of the over-current detection circuit provided by the present application for detecting the switching signal under the conditions of the wide pulse and the narrow pulse. As can be seen from fig. 13, compared with the prior art, the over-current detection circuit provided by the present application outputs over-current detection pulse signals for both the wide pulse and the narrow pulse in time, so as to avoid the problem of detection omission of the narrow pulse output caused by too long filtering time.

Referring to fig. 14, a flowchart of an over-current detection method of a high voltage driver chip according to an embodiment of the present application is shown. The over-current detection method can comprise the following steps:

1401, when the falling edge detection circuit detects the falling edge of the floating ground of the high-voltage area and the output of the low-voltage output port is a high-level signal, the logic control circuit outputs the high-level signal to the high-precision voltage detection circuit; the high-precision voltage detection circuit starts over-current detection when receiving a high-level signal and sends a detection voltage to the comparator.

In this embodiment, the detection voltage V _SENSE Equal to the high-voltage region floating ground VS.

Step 1402, when the output of the low voltage output port is a low level signal, the logic control circuit outputs the low level signal to the high precision voltage detection circuit; the high-precision voltage detection circuit turns off over-current detection when receiving a low level signal.

In step 1403, the comparator generates an over-current detection result from the detection voltage and the reference voltage.

Specifically, the working principle of the over-current detection circuit is described in detail in the foregoing description, and is not described again here.

In summary, the over-current detection method provided in this embodiment can detect the floating ground of the high voltage region in time by using the falling edge detection circuit, and then combine the output signal of the low voltage output port, so as to perform over-current detection in time, avoid the problems that the detection time is too early and the false judgment is easily formed, and the detection time is too late and the narrow pulse width is easily missed, and improve the timeliness of over-current detection.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description should not be taken as limiting the embodiments of the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the embodiments of the present application.

Claims

1. An overcurrent detection circuit of a high-voltage driving chip is characterized by comprising: the circuit comprises a falling edge detection circuit, a logic control circuit, a high-precision voltage detection circuit and a comparator;

2. The over-current detection circuit of a high-voltage driver chip according to claim 1, wherein the falling edge detection circuit comprises: the capacitive device, the first current source and the diode;

3. The over-current detection circuit of the high-voltage driving chip according to claim 2, wherein the capacitive device is any one or more of a capacitor, a source-drain parasitic capacitor of an NMOS tube with a short-circuited gate and source, and a source-drain parasitic capacitor of a PMOS tube with a short-circuited gate and source.

4. The over-current detection circuit of a high-voltage driving chip according to claim 1, wherein the logic control circuit comprises: the circuit comprises a first AND gate, a second AND gate, a D trigger and a falling edge pulse generating circuit;

5. The over-current detection circuit of a high-voltage driver chip according to claim 4, wherein the falling edge pulse generating circuit comprises: second to fifth inverters and a nand gate;

6. The over-current detection circuit of a high-voltage driving chip according to claim 1, wherein the high-precision voltage detection circuit comprises: the power supply comprises a first high-voltage power MOSFET, a second current source, a third current source I2, a first inverter and a low-level control switch;

the grid electrode of the first high-voltage power MOSFET is connected with the grid electrode of the second high-voltage power MOSFET and the input port of the first inverter and then serves as a first input port of the high-precision voltage detection circuit; the drain electrode of the first high-voltage power MOSFET is used as a second input port of the high-precision voltage detection circuit; the source electrode of the first high-voltage power MOSFET, the source electrode of the second high-voltage power MOSFET and the inflow port of the third current source are connected; an outflow port of the third current source is connected with one end of the switch controlled to be turned on by the low level and then is used as a grounding port of the high-precision voltage detection circuit; the drain electrode of the second high-voltage power MOSFET is connected with the other end of the switch controlled to be turned on by the low level and the outflow port of the second current source and then serves as the output port of the high-precision voltage detection circuit; an inflow port of the second current source is used as a power supply port of the high-precision voltage detection circuit; and the output port of the first inverter is connected with the control port of the switch which is controlled to be turned on by the low level.

7. The over-current detection circuit of the high-voltage driver chip according to claim 6, wherein a current ratio of the second current source to the third current source is 1: 2, the first high-voltage power MOSFET and the second high-voltage power MOSFET have the same size and specification.

8. The over-current detection circuit of a high-voltage driving chip according to claim 1, wherein the comparator comprises: first to fifth PMOS tubes and first to fourth NMOS tubes;

9. An overcurrent detection method of a high-voltage driver chip, used in the overcurrent detection circuit according to any one of claims 1 to 8, the method comprising:

10. The method for detecting the overcurrent of the high-voltage driver chip as recited in claim 9, wherein the detection voltage is equal to the high-voltage region floating ground.