CN110208673B - Power tube grid source voltage under-voltage detection circuit suitable for DC-DC converter - Google Patents

Power tube grid source voltage under-voltage detection circuit suitable for DC-DC converter Download PDF

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CN110208673B
CN110208673B CN201910504709.8A CN201910504709A CN110208673B CN 110208673 B CN110208673 B CN 110208673B CN 201910504709 A CN201910504709 A CN 201910504709A CN 110208673 B CN110208673 B CN 110208673B
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tube
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transistor
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CN110208673A (en
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明鑫
胡晓冬
张�杰
范子威
王卓
张波
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16557—Logic probes, i.e. circuits indicating logic state (high, low, O)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters

Abstract

A power tube grid source voltage under-voltage detection circuit suitable for a DC-DC converter comprises a voltage sampling module, a time reference generation module and a logic operation module, wherein the voltage sampling module is used for sampling a grid signal of a power tube and outputting a sampling signal, and the delay time of the sampling signal and the grid signal of the power tube is T1; the time reference generating module is used for delaying a control signal of the power tube for T2 to generate a narrow pulse signal, the narrow pulse signal is used as a time reference signal, and the control signal of the power tube is in phase with a grid signal of the power tube; the logic operation module is used for comparing the sampling signal with the time reference signal and generating an under-voltage signal when T1 is greater than T2. The invention compares the time reference signal with the sampling voltage of the power tube, can detect whether the high-side power tube and the low-side power tube in the DC-DC converter are under-voltage, has the characteristics of rapidness and accuracy, and can improve the stability and the efficiency of the DC-DC converter by controlling the power tube by returning the under-voltage signal.

Description

Power tube grid source voltage under-voltage detection circuit suitable for DC-DC converter
Technical Field
The invention belongs to the technical field of electronic circuits, and relates to an undervoltage detection circuit for detecting whether the grid source voltage of a power tube in a DC-DC converter is undervoltage or not, which can detect a high-side power tube and a low-side power tube of the DC-DC converter.
Background
Efficiency is one of the important metrics for the performance of a DC-DC converter, which can be measured as the ratio of the output power to the input power of the converter. Taking the Buck converter as an example, there are many factors that affect the efficiency of the Buck converter, such as switching loss generated during the turn-on and turn-off processes of the power tube, conduction loss generated during the conduction process of the power tube, magnetic core loss of the inductor, static power consumption of the internal circuit, and the like. As shown in fig. 1, the Buck converter works most efficiently under medium load conditions, and the efficiency is attenuated under light load conditions and heavy load conditions. Light load efficiency attenuation is mainly caused by switching losses; heavy duty efficiency degradation is mainly caused by conduction losses.
Conduction loss PconCan be calculated by the following formula:
Figure BDA0002091432300000011
wherein, IrmsIs the effective value of the inductor current, Rds(on)Is the power tube on-resistance. Since the power tube operates in the linear region, the on-resistance thereof is expressed as follows:
Figure BDA0002091432300000012
wherein, for the N-type power tube k, the product of the electron mobility and the unit area gate oxide capacitance is obtained, Vth is the threshold voltage of the power tube,
Figure BDA0002091432300000013
for the width-to-length ratio of the power tube, k and Vth are the process parameters of the power tube itself, W, L are selected during the circuit design, so the parameter determining the conduction impedance of the power tube is only the gate-source voltage V of the power tubeGS。
When a high-side power tube is turned on, the gate voltage of a conventional Buck converter with an N-type transistor as a power tube generally needs to be raised to a value higher than the input voltage of the converter through a bootstrap technique, and in the case of high-frequency application or the converter operating in a discontinuous conduction mode, a bootstrap capacitor may have a problem of insufficient electric quantity, so that the gate-source voltage of the high-side power tube is lower than a target value in the turning-on process, thereby attenuating the system efficiency.
Conventional gate-source voltage brown-out detection for high-side power transistors typically generates a reference voltage between the floating power rails SW and BST, and compares the gate-source voltage of the high-side power transistor with the reference voltage. In this design, the reference generating circuit is located on the floating power supply rail, and the reference voltage value is changed along with the switching frequency relative to the signal ground, so that the speed and the precision are limited for high-frequency and high-voltage applications.
Disclosure of Invention
Aiming at the problem of efficiency attenuation possibly caused by grid source voltage undervoltage of a high-side power tube in the working process of the Buck converter and the problem of limited speed and precision in high-frequency and high-voltage application caused by generation of reference voltage in a floating power rail in the traditional undervoltage detection method, the invention provides an undervoltage detection circuit which adopts a time reference detection mode, detects whether the grid source voltage of the high-side power tube or a low-side power tube is undervoltage or not by sampling grid signals of the high-side power tube or the low-side power tube and comparing the grid signals with time reference signals, and is suitable for a DC-DC converter; when the undervoltage detection circuit provided by the invention is used for detecting the undervoltage of the high-side power tube, the high-side power tube is turned off by taking the undervoltage signal as an enabling signal until the undervoltage is over, so that unnecessary conduction loss can be avoided.
The technical scheme of the invention is as follows:
a power tube grid source voltage under-voltage detection circuit suitable for a DC-DC converter comprises a voltage sampling module, a time reference generation module and a logic operation module,
the voltage sampling module is used for sampling a grid signal of the power tube and outputting a sampling signal, and the delay time of the sampling signal and the grid signal of the power tube is T1;
the time reference generating module is used for delaying a control signal of the power tube for a time delay time of T2 to generate a narrow pulse signal, the narrow pulse signal is used as a time reference signal, and the control signal of the power tube is in phase with a grid signal of the power tube;
the logic operation module is used for comparing the sampling signal with a time reference signal and generating an under-voltage signal when T1 is greater than T2.
Specifically, the voltage sampling module comprises a sampling unit, the sampling unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor and a first current source,
the grid electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube and serves as the input end of the voltage sampling module, the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the fourth PMOS tube and the sixth PMOS tube and is connected with the relatively high level of the power supply rail of the sampling unit, and the drain electrode of the first PMOS tube is connected with the drain electrodes of the first NMOS tube and the second PMOS tube and the grid electrodes of the second NMOS tube and the fourth PMOS tube;
the grid electrode of the first NMOS tube is connected with the grid electrode and the drain electrode of the third PMOS tube, and is connected with the source electrodes of the first NMOS tube and the second NMOS tube and the relatively low level of the power rail of the sampling unit after passing through the first resistor;
the grid electrode of the fifth PMOS tube is connected with the grid electrode of the second PMOS tube and the grid electrode and the drain electrode of the sixth PMOS tube and is connected with the relatively low level of the power rail of the sampling unit after passing through the first current source, the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube and outputs the output signal of the sampling unit, and the output signal of the sampling unit changes along with the grid electrode signal of the power tube.
Specifically, when the power transistor is a low-side power transistor, the power rail of the sampling unit is a low-side power rail of the DC-DC converter, a relatively high level of the power rail of the sampling unit is a low-voltage power supply, a relatively low level of the power rail of the sampling unit is a ground level, an input end of the sampling unit is connected to a gate signal of the low-side power transistor, and an output signal of the sampling unit is the sampling signal.
Specifically, when the power transistor is a high-side power transistor, the power rail of the sampling unit is a high-side power rail of the DC-DC converter, a relatively high level of the power rail of the sampling unit is a floating power supply of the DC-DC converter, a relatively low level of the power rail of the sampling unit is a level at a switch node of the DC-DC converter, and an input end of the sampling unit is connected to a gate signal of the high-side power transistor;
the voltage sampling module further comprises a level shift unit, and the level shift unit is used for converting an output signal of the sampling unit from a high-side power rail of the DC-DC converter to a low-side power rail of the DC-DC converter to be used as the sampling signal.
Specifically, the level shift unit comprises a third NMOS transistor, a fourth NMOS transistor, a seventh PMOS transistor, a second resistor, a first voltage-withstanding transistor, a second voltage-withstanding transistor, a first inverter and a second inverter,
the grid electrode of the second voltage-resistant transistor is connected with the grid electrode and the source electrode of the first voltage-resistant transistor and the level of the switch node of the DC-DC converter, the source electrode of the second voltage-resistant transistor is connected with the output signal of the sampling unit, and the drain electrode of the second voltage-resistant transistor is connected with the drain electrodes of the fourth NMOS transistor and the seventh PMOS transistor and the input end of the first inverter;
the grid electrode and the drain electrode of the third NMOS tube are connected with the drain electrode of the first voltage-withstanding transistor and the grid electrode of the fourth NMOS tube, and are connected with the grid electrode and the source electrode of the seventh PMOS tube and the low-voltage power supply through the second resistor, and the source electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube and is connected with the ground level in parallel;
the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter outputs the sampling signal.
Specifically, the time reference generation module comprises a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a third resistor, a first capacitor, a second capacitor, a fifth NMOS transistor, an eighth PMOS transistor and a first NAND gate,
the input end of the third phase inverter is connected with the control signal of the power tube, and the output end of the third phase inverter is connected with the grids of the fifth NMOS tube and the eighth PMOS tube;
the source electrode of the eighth PMOS tube is connected with a low-voltage power supply, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the input end of the fourth phase inverter after passing through the third resistor and is connected with the source electrode and the ground level of the fifth NMOS tube after passing through the first capacitor;
the input end of the fifth inverter is connected with the output end of the fourth inverter, and the output end of the fifth inverter is connected with the input end of the sixth inverter and the first input end of the first NAND gate;
the input end of the seventh inverter is connected with the output end of the sixth inverter and is connected with the ground level through the second capacitor, and the output end of the seventh inverter is connected with the second input end of the first NAND gate through the eighth inverter;
the output end of the first NAND gate outputs the time reference signal.
Specifically, the logic operation module includes a first nor gate, two input ends of the first nor gate are respectively connected to the time reference signal and the sampling signal, and an output end of the first nor gate outputs the under-voltage signal.
The invention has the beneficial effects that: the undervoltage detection circuit is used for detecting whether the grid source voltage of the power tube is undervoltage or not by comparing the generated time reference signal with the sampling signal of the power tube, and compared with the traditional method of generating the reference voltage between the floating power rails, the undervoltage detection circuit has the advantages of being high in speed and accuracy; the undervoltage detection provided by the invention can be used for detecting a high-side power tube and a low-side power tube in a DC-DC converter, and the detected undervoltage signal can be returned to control the on and off of the power tube, so that the problem of signal false triggering possibly generated in the working process of a system can be optimized.
Drawings
Fig. 1 is a diagram illustrating the characteristics of the Buck converter efficiency with the change of the output impedance.
Fig. 2 is a schematic structural diagram of a power tube gate-source voltage under-voltage detection circuit for a DC-DC converter according to the present invention, when the circuit is used for detecting a high-side power tube.
Fig. 3 is a circuit structure diagram of a sampling unit when the power transistor gate-source voltage under-voltage detection circuit suitable for the DC-DC converter is used for detecting a high-side power transistor.
Fig. 4 is an actual circuit diagram of a level shift level-down unit when the power tube gate-source voltage under-voltage detection circuit suitable for the DC-DC converter provided by the invention is used for detecting a high-side power tube.
Fig. 5 is an actual circuit diagram of a time reference generation module and a logic operation module when the power transistor gate-source voltage under-voltage detection circuit for a DC-DC converter provided by the invention is used for detecting a high-side power transistor.
Fig. 6 is a timing diagram of a power tube gate-source voltage under-voltage detection circuit for a DC-DC converter according to the present invention when the circuit is used to detect a high-side power tube.
Detailed Description
The invention is further illustrated with reference to the figures and the specific examples.
The undervoltage detection circuit detects whether a power tube in a DC-DC converter is in overvoltage or not by utilizing a time reference, and comprises a voltage sampling module, a time reference generation module and a logic operation module, wherein the voltage sampling module is used for sampling a grid signal of the power tube and generating a sampling signal, the time reference generation module is used for generating a narrow pulse signal as a time reference signal, and the sampling signal is compared with the time reference signal to obtain an undervoltage signal. The working process and working principle of the present invention will be described in detail below by taking the detection of the high-side power transistor as an example.
Fig. 2 is a schematic structural diagram of the undervoltage detection circuit for detecting a high-side power transistor, which includes a voltage sampling module, a time reference generation module, and a logic operation module. The voltage sampling module comprises a sampling unit for sampling gate source voltage of the high-side power tube, and as shown in fig. 3, the sampling unit is an implementation circuit of the sampling unit, and comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first NMOS tube MN1, a second NMOS tube MN2, a first resistor R1 and a first current source, wherein a gate of the first PMOS tube MP1 is connected with a source of the third PMOS tube MP3 and serves as an input end of the voltage sampling module to be connected with a gate signal DRVH of the high-side power tube, a source of the first PMOS tube MP2, a source of the fourth PMOS tube MP4 and a source of the sixth PMOS tube MP6 are connected with a relatively high level of a power rail of the sampling unit, and a drain of the first PMOS tube MN1 and the second PMOS tube MP2 and a drain of the second PMOS tube MN2 and a drain of the fourth PMOS tube MP4 are connected with a drain of the PMOS tube MP1 and a; the grid electrode of the first NMOS transistor MN1 is connected with the grid electrode and the drain electrode of the third PMOS transistor MP3, and is connected with the source electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 and the relatively low level of the power rail of the sampling unit through a first resistor R1; the grid electrode of the fifth PMOS transistor MP5 is connected to the grid electrode of the second PMOS transistor MP2 and the grid electrode and the drain electrode of the sixth PMOS transistor MP6, and is connected to the relatively low level of the power rail of the sampling unit after passing through the first current source, the source electrode thereof is connected to the drain electrode of the fourth PMOS transistor MP4, the drain electrode thereof is connected to the drain electrode of the second NMOS transistor MN2 and outputs the output signal DRVH' of the sampling unit, and the output signal of the sampling unit changes with the grid electrode signal of the power transistor.
Taking a Buck converter taking an N-type transistor as a power tube as an example, a switch node SW is a source electrode of a high-side power tube, and when the low-side power tube of the Buck converter is switched on, the SW level is approximate to the low level of a chip; when the Buck converter high-side power tube is turned on, the SW level is approximate to the chip input voltage. The difference between BST and SW is the difference between the two terminals of the bootstrap capacitor, and can be approximately regarded as a fixed value. During the turn-on process of the high-side power tube, the level of the gate signal DRVH of the high-side power tube is gradually raised relative to the level of SW. When the gate signal DRVH voltage of the high-side power transistor rises to turn on the third PMOS transistor MP3, the level of the A point, namely the drain terminal of the third PMOS transistor MP3, is established, and the voltage value V of the A pointACan be determined by the following equation:
Figure BDA0002091432300000051
wherein, KMP3Is the product of the process parameter and the width-to-length ratio of the third PMOS transistor MP3, Vth,MP3Is the threshold voltage of the third PMOS transistor MP 3. As the level of the gate signal DRVH of the high-side power transistor rises, the level at point a rises continuously, and the current flowing through the first NMOS transistor MN1 is established when the level at point a rises to turn on the first NMOS transistor MN 1. The first current source I1 is a constant bias current, and is mirrored to the second PMOS transistor MP2 through the sixth PMOS transistor MP 6.When the level of the gate signal DRVH of the high-side power transistor rises to a level where the current flowing through the first NMOS transistor MN1 exceeds the current flowing through the first PMOS transistor MP1 plus the current I1 of the first current source, the level at point B, i.e., the drain terminal of the first NMOS transistor MN1, is gradually pulled low. When the level of the point B is lowered to the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are turned on, the level of the output signal DRVH 'of the sampling unit is raised, and thus the rise of the level of the gate signal DRVH of the high-side power transistor finally raises the level of the output signal DRVH' of the sampling unit. The time from the rise of the gate signal DRVH level of the high-side power transistor to the rise of the output signal DRVH' signal of the sampling unit to the rise of the level detectable by the next-stage circuit (the next-stage circuit is a level shift circuit when the high-side power transistor is detected, and the next-stage circuit is a logic operation module when the low-side power transistor is detected) is denoted as t 1. The rising and falling of the a point level can be regarded as the result of the charging and discharging of the parasitic capacitance of the transistor gate by the third PMOS transistor MP3 and the first resistor R1, the rising and falling of the B point level can be regarded as the result of the charging and discharging of the parasitic capacitance of the transistor gate by the first NMOS transistor MN1, the first PMOS transistor MP1 and the second PMOS transistor MP2, and the rising and falling of the level of the output signal DRVH' of the sampling unit can be regarded as the result of the charging and discharging of the parasitic capacitance of the transistor gate by the fourth PMOS transistor MP4, the fifth PMOS transistor MP5 and the second NMOS transistor MN 2. According to the capacitance characteristic expression:
Figure BDA0002091432300000061
it is known that the time required for charging and discharging a capacitor of a certain size to a fixed voltage is inversely proportional to the magnitude of the charge and discharge current. Therefore, when the DRVH level is low with respect to the SW level, the level changes slowly at the points a, B, and DRVH', and t1 is long. Specifically, the relationship between DRVH level and t1 can be obtained by combining the following equations:
Figure BDA0002091432300000062
Figure BDA0002091432300000063
Figure BDA0002091432300000064
wherein, KMP3、KMN1、KMP4Corresponding to the product of the process parameters and the width-to-length ratio of the third PMOS transistor MP3, the first NMOS transistor MN1 and the fourth PMOS transistor MP 4; a point level VAB point level VBDRVH' level VDRVH’Respectively determining voltage values of relevant nodes under the DRVH voltage in a steady state; cB、CDRVH’Parasitic capacitance values, V, of points B and DRVH' respectivelyth,MN1、Vth,MP4The threshold voltages of the first NMOS transistor MN1 and the fourth PMOS transistor MP4, respectively, t1 'represents the time required for DRVH to flip from low to high until the node B reaches a steady state value, and t1 "represents the time required for DRVH' to flip from the point B into the steady state to enter the steady state. If the magnitude of the parasitic capacitance of each node is known, the magnitude of t1 can be calculated by the above expression, and the value is t1 ═ t 1' + t1 ".
Because the sampling unit is used for detecting the high-side power tube, because the input end of the sampling unit is connected with the gate signal DRVH of the high-side power tube, the power rail of the sampling unit is a high-side floating power rail (SW-BST) of the DC-DC converter, that is, at this time, the relatively high level of the power rail of the sampling unit is the floating power BST of the DC-DC converter, the relatively low level of the power rail of the sampling unit is the level at the switch node SW of the DC-DC converter, the gate signal DRVH of the high-side power tube is converted into the output signal DRVH 'of the sampling unit after passing through the sampling unit for sampling the gate source voltage of the high-side power tube, and the power rail of the output signal DRVH' of the sampling unit is also the high-side floating power rail of the DC-DC converter, and the reference ground is the level at the switch node. The power rails of the logic operation module and the time reference generation module are low-side power rails, and the reference ground is a chip ground signal, so that a level shift level-Down unit is needed to convert an output signal DRVH' of the sampling unit positioned on the high-side power rail into a sampling signal DRVH _ Down of the high-side power tube positioned on the low-side power rail, which can be identified by the logic operation module, when detecting the high-side power tube.
Fig. 4 is a schematic diagram of an implementation structure of a level shift unit, which includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a seventh PMOS transistor MP7, a second resistor R2, a first voltage-withstanding transistor MPH1, a second voltage-withstanding transistor MPH2, a first inverter INV1, and a second inverter INV2, wherein a gate of the second voltage-withstanding transistor MPH2 is connected to a gate and a source of the first voltage-withstanding transistor MPH1 and a level of a switch node SW of the DC-DC converter, a source of the second voltage-withstanding transistor MPH2 is connected to an output signal DRVH' of the sampling unit, and a drain of the second voltage-withstanding transistor MPH 4 and a drain of the seventh PMOS transistor MP7 and an input end of the first inverter INV 1; the grid and the drain of the third NMOS transistor MN3 are connected to the drain of the first withstand voltage transistor MPH1 and the grid of the fourth NMOS transistor MN4, and are connected to the grid and the source of the seventh PMOS transistor MP7 and the low voltage power supply VCC through the second resistor R2, and the source thereof is connected to the source of the fourth NMOS transistor MN4 and is connected to the ground level; the input end of the second inverter INV2 is connected to the output end of the first inverter INV1, and the output end thereof outputs the sampling signal DRVH _ Down of the high-side power transistor.
When the level of the output signal DRVH' of the sampling unit rises to turn on the second voltage-withstanding transistor MPH2, a current will be injected into the node C, i.e., the drain terminal of the second voltage-withstanding transistor MPH2, so that the level of the node C rises. Due to the clamping effect of the seventh PMOS transistor MP7, the voltage at the point C is raised to VCC + VBE at most, where VBE is the conduction voltage drop of the parasitic body diode D1 of the seventh PMOS transistor MP 7. The second resistor R2 and the third NMOS transistor MN3 determine a small bias current I2, which is mirrored to the fourth NMOS transistor MN4, for maintaining a low level of the C point when the second voltage withstanding transistor MPH2 is not turned on by the output signal DRVH' of the sampling unit. When the high-side power transistor is turned on to raise the SW node level, a current I3 passes through the parasitic capacitance C between the gate and the drain of the first voltage-withstanding transistor MPH1GDAnd coupling, at the moment, the I2 and the I3 act together to prevent the C point level from being turned over by mistake caused by sensitive node disturbance in the starting process of the high-side power tube, and detection errors caused by false triggering are effectively avoided. The sampling signal DRVH _ Down finally output after being shaped by the first inverter INV1 and the second inverter INV2, and the obtained sampling signal DRVH _ DownThe reference ground level is the chip ground. The time from the detection of the rise of the output signal DRVH' of the sampling unit to the output of the valid sampling signal DRVH _ Down by the level shift level-Down unit is denoted as t2, and can be regarded as the time required for charging the parasitic capacitance of the node C to VCC + VBE.
When the high-side power tube is detected, the delay generated by the sampling unit is T1, the delay generated by the level shifting unit is T2, and the delay time T1 between the sampling signal and the gate signal of the power tube is T1+ T2.
The invention introduces the clock reference into the undervoltage detection, and utilizes the time reference generation module to generate a narrow pulse as the time reference signal T, as shown in FIG. 5, an implementation circuit of the time reference generation module is provided, which comprises a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a third resistor R3, a first capacitor C1, a second capacitor C2, a fifth NMOS transistor MN5, an eighth PMOS transistor MP8 and a first NAND gate 1, wherein the input end of the third inverter INV3 is connected with the control signal TG _ ctr1 of the high-side power transistor, and the output end is connected with the gates of the fifth NMOS transistor MN5 and the eighth PMOS transistor MP 8; the source of the eighth PMOS transistor MP8 is connected to the low voltage power VCC, and the drain thereof is connected to the drain of the fifth NMOS transistor MN5 and the input terminal of the fourth inverter INV4 through the third resistor R3 and to the source and ground of the fifth NMOS transistor MN5 through the first capacitor C1; an input end of the fifth inverter INV5 is connected to the output end of the fourth inverter INV4, and an output end of the fifth inverter INV5 is connected to an input end of the sixth inverter INV6 and the first input end of the first NAND gate 1; an input end of the seventh inverter INV7 is connected to the output end of the sixth inverter INV6, passes through the second capacitor C2, and is connected to the ground, and an output end of the seventh inverter INV7 passes through the eighth inverter INV8 and is connected to the second input end of the first NAND gate NAND 1; the output of the first NAND gate NAND1 outputs the time reference signal T.
When the high-side power tube is detected, the time reference generation module generates a narrow pulse by using a control signal TG _ ctr1 of the high-side power tube, a TG _ ctr1 signal is a control signal for controlling the on and off of the high-side power tube and is a periodic square wave, a control signal TG _ ctr1 of the high-side power tube is in phase with a gate signal DRVH of the high-side power tube, the gate signal DRVH of the high-side power tube is turned up along with the turning-up of the control signal TG _ ctr1 of the high-side power tube so as to control the on and off of the high-side power tube, and the high-side power tube is turned on when the square wave signal is in a high level stage. The delay generated by the third resistor R3 and the first capacitor C1 is denoted as T3, and T3 is the delay T2 of the time reference signal T and the control signal TG _ ctr1 of the high-side power transistor. The delay caused by the second capacitor C2 determines the narrow pulse width of the time reference signal T, the fourth inverter INV4, the fifth inverter INV5, the seventh inverter INV7 and the eighth inverter INV8 are used to shape the delayed waveform, and the first NAND gate NAND1 is used to generate a narrow pulse signal, which is the time reference signal T generated in the present embodiment.
The logic operation module is used for carrying out logic operation on a sampling signal DRVH _ Down and a time reference signal T of the high-side power tube to generate an undervoltage signal TG _ ctr2, the undervoltage signal TG _ ctr2 is a high-side power tube grid-source voltage detection result, and the undervoltage signal TG _ ctr2 can be returned to be used for controlling the on-off of the high-side power tube. As shown in fig. 5, in the present embodiment, the first NOR gate NOR1 is used to perform a logic operation, and when the sampling signal DRVH _ Down of the high-side power transistor and the time reference signal T are both low, the undervoltage signal TG _ ctr2 with a high level is generated. In this embodiment, a nor logic is taken as an example, but the logic operation module with the rest of structures and logics can also be used for comparing the sampling signal with the time reference logic signal T to generate a corresponding under-voltage signal.
As shown in fig. 6, which is a timing diagram of the high-side power transistor in this embodiment, the delay due to the inverter is very short and can be ignored here. The shaded part in the figure is a waveform when the undervoltage of the high-side power tube is triggered, a gate signal DRVH of the high-side power tube is turned up along with the turning-up of a high-side power tube control signal TG _ ctr1, an output signal DRVH 'of a sampling unit is turned up after t1 time delay brought by a sampling unit of the gate source voltage of the high-side power tube, and then the output signal DRVH' is turned up after t2 time delay brought by a level-Down unit, and the sampling signal DRVH _ Down is turned up. When the grid-source voltage of the high-side power tube is not under-voltage, t1+ t2 is not more than t3, the under-voltage signal TG _ ctr2 is at low level, and the high-side power tube can be normally started; when the gate source voltage of the high-side power tube is under-voltage, T1+ T2 is greater than T3, the under-voltage signal TG _ ctr2 changes to a high level when the sampling signal DRVH _ Down and the time reference signal T are simultaneously at a low level, and the under-voltage signal TG _ ctr2 at the high level can be used for shielding a high-side power tube opening signal to close the high-side power tube and open the high-side power tube again until the under-voltage is over, so that the excessive conduction loss caused by the too low gate source voltage of the high-side power tube is avoided.
Similarly, when the undervoltage detection circuit provided by the invention is used for a low-side power tube, the undervoltage detection circuit comprises a voltage sampling module, a time reference generation module and a logic operation module, wherein the voltage sampling module is used for sampling a gate signal of the low-side power tube, and since a power rail of a sampling unit is a low-side power rail of a DC-DC converter at the moment, a level shift unit is not required to be arranged, an output signal of the sampling unit is directly used as a sampling signal, and T1 only has a delay T1 generated by the sampling unit; the time reference generating module generates a narrow pulse as a time reference signal after delaying the control signal of the low-side power tube by T2, T2 is a delay T3 between the time reference signal and the control signal of the low-side power tube, and the time reference generating module can be determined by a third resistor R3 and a first capacitor C1 in the embodiment as well; and comparing t1 with t3 by the logic operation module, wherein the low-side power tube can be normally turned on when t1 is not greater than t3, and the low-side power tube is turned off by generating an under-voltage signal to shield the turn-on signal of the low-side power tube when t1 is greater than t 3. In the present embodiment, a Buck converter is taken as an example, but the present invention is also applicable to DC-DC converters of other modes.
The above examples are only for illustrating the technical solutions of the present invention, and those skilled in the art should understand that modifications and variations can be made to the present invention, but all within the scope of the present invention should be covered by the protection scope of the present invention.

Claims (5)

1. A power tube grid source voltage under-voltage detection circuit suitable for a DC-DC converter is characterized by comprising a voltage sampling module, a time reference generation module and a logic operation module,
the voltage sampling module is used for sampling a grid signal of the power tube and outputting a sampling signal, and the delay time of the sampling signal and the grid signal of the power tube is T1; the voltage sampling module comprises a sampling unit, the sampling unit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor and a first current source,
the grid electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube and serves as the input end of the voltage sampling module, the source electrode of the first PMOS tube is connected with the source electrodes of the second PMOS tube, the fourth PMOS tube and the sixth PMOS tube and is connected with the relatively high level of the power supply rail of the sampling unit, and the drain electrode of the first PMOS tube is connected with the drain electrodes of the first NMOS tube and the second PMOS tube and the grid electrodes of the second NMOS tube and the fourth PMOS tube;
the grid electrode of the first NMOS tube is connected with the grid electrode and the drain electrode of the third PMOS tube, and is connected with the source electrodes of the first NMOS tube and the second NMOS tube and the relatively low level of the power rail of the sampling unit after passing through the first resistor;
the grid electrode of the fifth PMOS tube is connected with the grid electrode of the second PMOS tube and the grid electrode and the drain electrode of the sixth PMOS tube and is connected with the relatively low level of the power supply rail of the sampling unit after passing through the first current source, the source electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube and outputs the output signal of the sampling unit, the output signal of the sampling unit changes along with the grid electrode signal of the power tube, and the sampling signal is generated according to the output signal of the sampling unit;
the time reference generating module is used for delaying a control signal of the power tube for a time delay time of T2 to generate a narrow pulse signal, the narrow pulse signal is used as a time reference signal, and the control signal of the power tube is in phase with a grid signal of the power tube; the time reference generating module comprises a third phase inverter, a fourth phase inverter, a fifth phase inverter, a sixth phase inverter, a seventh phase inverter, an eighth phase inverter, a third resistor, a first capacitor, a second capacitor, a fifth NMOS transistor, an eighth PMOS transistor and a first NAND gate,
the input end of the third phase inverter is connected with the control signal of the power tube, and the output end of the third phase inverter is connected with the grids of the fifth NMOS tube and the eighth PMOS tube;
the source electrode of the eighth PMOS tube is connected with a low-voltage power supply, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the input end of the fourth phase inverter after passing through the third resistor and is connected with the source electrode and the ground level of the fifth NMOS tube after passing through the first capacitor;
the input end of the fifth inverter is connected with the output end of the fourth inverter, and the output end of the fifth inverter is connected with the input end of the sixth inverter and the first input end of the first NAND gate;
the input end of the seventh inverter is connected with the output end of the sixth inverter and is connected with the ground level through the second capacitor, and the output end of the seventh inverter is connected with the second input end of the first NAND gate through the eighth inverter;
the output end of the first NAND gate outputs the time reference signal;
the logic operation module is used for comparing the sampling signal with a time reference signal and generating an under-voltage signal when T1 is greater than T2.
2. The under-voltage detection circuit for gate-source voltage of power transistor of DC-DC converter according to claim 1, wherein when the power transistor is a low-side power transistor, the power rail of the sampling unit is a low-side power rail of the DC-DC converter, the relatively high level of the power rail of the sampling unit is a low-voltage power supply, the relatively low level of the power rail of the sampling unit is a ground level, the input terminal of the sampling unit is connected to the gate signal of the low-side power transistor, and the output signal of the sampling unit is the sampling signal.
3. The under-voltage detection circuit for gate-source voltage of power tube of DC-DC converter according to claim 1, wherein when the power tube is a high-side power tube, the power rail of the sampling unit is the high-side power rail of the DC-DC converter, the relatively high level of the power rail of the sampling unit is the floating power supply of the DC-DC converter, the relatively low level of the power rail of the sampling unit is the level at the switch node of the DC-DC converter, and the input terminal of the sampling unit is connected to the gate signal of the high-side power tube;
the voltage sampling module further comprises a level shift unit, and the level shift unit is used for converting an output signal of the sampling unit from a high-side power rail of the DC-DC converter to a low-side power rail of the DC-DC converter to be used as the sampling signal.
4. The under-voltage detection circuit for gate-source voltage of power transistor of DC-DC converter as claimed in claim 3, wherein said level shift unit comprises a third NMOS transistor, a fourth NMOS transistor, a seventh PMOS transistor, a second resistor, a first voltage-withstanding transistor, a second voltage-withstanding transistor, a first inverter and a second inverter,
the grid electrode of the second voltage-resistant transistor is connected with the grid electrode and the source electrode of the first voltage-resistant transistor and the level of the switch node of the DC-DC converter, the source electrode of the second voltage-resistant transistor is connected with the output signal of the sampling unit, and the drain electrode of the second voltage-resistant transistor is connected with the drain electrodes of the fourth NMOS transistor and the seventh PMOS transistor and the input end of the first inverter;
the grid electrode and the drain electrode of the third NMOS tube are connected with the drain electrode of the first voltage-withstanding transistor and the grid electrode of the fourth NMOS tube, and are connected with the grid electrode and the source electrode of the seventh PMOS tube and the low-voltage power supply through the second resistor, and the source electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube and is connected with the ground level in parallel;
the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter outputs the sampling signal.
5. The power tube grid-source voltage undervoltage detection circuit suitable for the DC-DC converter according to any one of claims 1 to 4, wherein the logic operation module comprises a first NOR gate, two input terminals of the first NOR gate are respectively connected to the time reference signal and the sampling signal, and an output terminal of the first NOR gate outputs the undervoltage signal.
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