CN114744604B

CN114744604B - Clamping circuit

Info

Publication number: CN114744604B
Application number: CN202210649234.3A
Authority: CN
Inventors: 殷一文; 阮剑聪; 谭润钦
Original assignee: Shenzhen Danyuan Semiconductor Co ltd
Current assignee: Shenzhen Danyuan Semiconductor Co ltd
Priority date: 2022-06-10
Filing date: 2022-06-10
Publication date: 2022-09-13
Anticipated expiration: 2042-06-10
Also published as: CN114744604A

Abstract

The invention provides a clamping circuit which comprises a first PMOS (P-channel metal oxide semiconductor) tube and a first NMOS (N-channel metal oxide semiconductor) tube. The first PMOS tube and the first NMOS tube, the input voltage of the clamping circuit and the reference voltage form a common clamping circuit together. On the basis of a common clamping circuit, the invention also comprises a pulse delay circuit, a second PMOS tube and a second NMOS tube. The second PMOS tube can detect the state of the input voltage of the clamping circuit, when voltage spikes occur, the second PMOS tube is conducted to provide pulse signals for the pulse delay circuit, after the pulse delay circuit receives the pulse signals, high level is output to the grid electrode of the second NMOS tube in a delayed mode, and the second NMOS tube is conducted. At the moment, the grid electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube actively discharges, so that the energy loss of the circuit is reduced.

Description

Clamping circuit

Technical Field

The invention relates to the technical field of integrated circuit design, in particular but not limited to a clamping circuit.

Background

In an integrated circuit, a voltage spike may occur when a large current path is instantaneously turned on or off, and a circuit connected to the voltage spike may be damaged. In order to protect the circuit, the energy causing the voltage spike needs to be discharged in time, and the circuit playing this role is called a Snubber (voltage clamp) circuit. A typical Snubber circuit is shown in FIG. 1, and the Ids waveforms for VIN, NGATE, and NM1 are shown in FIG. 2.

The operating principle of the Snubber circuit shown in fig. 1 is as follows: when the voltage of VIN rises to be higher than VREF by a PMOS threshold voltage (time t 1), PM1 is turned on to charge the gate capacitance of NM 1; when the gate voltage of NM1 is higher than the threshold voltage of NMOS (time t 2), NM1 turns on and starts to discharge VIN, thereby realizing voltage clamping on VIN; when VIN voltage is lower than VREF plus a PMOS threshold voltage (at time t 3), PM1 is turned off, and resistor R1 gradually drains the gate voltage of NM1 to ground; when the gate voltage of NM1 is lower than the threshold voltage of NMOS (time t 4), NM1 turns off.

However, at time t3, the VIN voltage has been pulled down below the target voltage (VREF + PMOS _ Vth), at which point the mission of the Snubber circuit has been completed, and the Snubber circuit should ideally be turned off immediately. However, NGATE voltage is high at time t3, and NM1 gate voltage needs to be drained to ground by resistor R1. During the time period t 3-t 4, the charge Q2 that NM1 discharges from VIN is not necessary, an inefficient loss of efficiency.

One solution to reduce the value of the reactive loss Q2 is to reduce the resistor R1, but R1 cannot be reduced without limit because too small R1 would slow the PM1 charging the NGATE, delaying the arrival at time t2, making the clamping untimely and less effective.

Another solution is to increase the size of the NM1 transistor, i.e. increase the saturation current of NM1, so that Ids of NM1 can pull VIN down below VREF + PMOS _ Vth once the voltage of NGATE just exceeds the threshold voltage of NMOS. R1 then only needs to let the NGATE voltage drain a little to turn off NM1, thereby reducing the time from t3 to t 4. However, in this method, when NM1 is clamped, NGATE voltage is only a little higher than NMOS threshold voltage, and the discharge capability of NM1 cannot be fully utilized, and a larger NM1 size is required to realize the same clamping capability, which wastes chip area.

In view of the above, there is a need to provide a new structure or control method to solve at least some of the above problems.

Disclosure of Invention

In view of the above situation, a primary object of the present invention is to provide a clamp circuit capable of increasing the circuit area by a very small amount without losing the clamping effect, thereby greatly reducing the time from t3 to t4 and improving the efficiency of the Snubber circuit.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

in a first aspect, an embodiment of the present invention provides a clamping circuit, including:

the first NMOS tube is provided with a source electrode, a drain electrode and a grid electrode, the source electrode of the first NMOS tube is coupled with the reference ground, and the drain electrode of the first NMOS tube is coupled with the input voltage of the clamping circuit;

the second NMOS tube is provided with a source electrode, a drain electrode and a grid electrode, the source electrode of the second NMOS tube is coupled with the reference ground, and the drain electrode of the first NMOS tube is coupled with the grid electrode of the first NMOS tube;

the first PMOS tube is provided with a source electrode, a drain electrode and a grid electrode, the source electrode of the first PMOS tube is coupled with the input voltage of the clamping circuit, the drain electrode of the first PMOS tube is coupled with the grid electrode of the first NMOS tube, and the grid electrode of the first PMOS tube is coupled with the reference voltage;

the source electrode of the second PMOS tube is coupled with the input voltage of the clamping circuit, and the grid electrode of the second PMOS tube is coupled with the reference voltage;

and the input end of the pulse delay circuit is coupled with the drain electrode of the second PMOS tube, and the output end of the pulse delay circuit is coupled with the grid electrode of the second NMOS tube.

Optionally, the clamp circuit further includes a third NMOS transistor, the third NMOS transistor is coupled between the second NMOS transistor and a ground reference, and has a source, a drain, and a gate, the source of the third NMOS transistor is coupled to the ground reference, the drain of the third NMOS transistor is coupled to the source of the second NMOS transistor, and the gate of the third NMOS transistor is coupled to a pulse signal, where the pulse signal normally outputs a high level and when an ESD event occurs, outputs a low level.

The embodiment of the invention provides a clamping circuit which comprises a first PMOS (P-channel metal oxide semiconductor) tube and a first NMOS (N-channel metal oxide semiconductor) tube. The first PMOS tube and the first NMOS tube, the input voltage of the clamping circuit and the reference voltage form a common clamping circuit. On the basis of a common clamping circuit, the invention also comprises a pulse delay circuit, a second PMOS tube and a second NMOS tube. The second PMOS tube can detect the state of the power supply voltage, when voltage spikes occur, the second PMOS tube is conducted to provide pulse signals for the pulse delay circuit, after the pulse delay circuit receives the pulse signals, the pulse delay circuit delays to output high level to the grid electrode of the second NMOS tube, and the second NMOS tube is conducted. At the moment, the grid electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube actively discharges, so that the energy loss of the circuit is reduced.

In a second aspect, an embodiment of the present invention provides a clamp circuit, including:

the first detection circuit is used for detecting the input voltage of the clamping circuit and conducting when the input voltage of the clamping circuit is higher than a first preset value;

the first switch tube is provided with a first end, a second end and a control end, wherein the first end of the first switch tube is coupled with the input voltage of the clamping circuit, the second end of the first switch tube is coupled with the reference ground, the control end of the first switch tube is coupled with the first detection circuit, and after the first detection circuit is conducted, the voltage of the control end of the first switch tube is increased to a second preset value and controls the first switch tube to be conducted, so that the input voltage of the clamping circuit is reduced;

and the discharge circuit is coupled with the control end of the first switching tube and used for controlling the voltage of the control end of the first switching tube to be reduced to be lower than the second preset value after the first switching tube is conducted for a period of time.

Optionally, the first detection circuit includes a first comparison circuit having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first comparison circuit is coupled to the input voltage of the clamp circuit, the second input terminal of the first comparison circuit is coupled to a first reference voltage, and the output terminal of the first comparison circuit is coupled to the control terminal of the first switch tube, where the first reference voltage reflects the first preset value.

Optionally, the first detection circuit includes a second switch tube, the second switch tube has a first end, a second end and a control end, wherein the first end of the second switch tube is coupled to the input voltage of the clamping circuit, the second end of the second switch tube is coupled to the control end of the first switch tube, and the control end of the second switch tube is coupled to a second reference voltage, wherein a sum of the second reference voltage and a switching threshold of the second switch tube reflects the second preset value.

Optionally, the discharge circuit includes a third switching tube, where the third switching tube has a first end, a second end, and a control end, where the first end of the third switching tube is coupled to the control end of the first switching tube, the second end of the third switching tube is coupled to a ground reference, and the control end of the third switching tube is coupled to a first pulse signal, where the first pulse signal outputs a high level after the first switching tube is turned on for a period of time.

Optionally, the clamping circuit further includes a pulse delay circuit, the pulse delay circuit has an input end and an output end, the input end of the pulse delay circuit is coupled to the first detection circuit, the output end of the pulse delay circuit is coupled to the control end of the third switching tube, and the output end of the pulse delay circuit delays to output the first pulse signal after the input end of the pulse delay circuit receives the rising edge signal from the first detection circuit.

Optionally, the clamping circuit further includes a second detection circuit and a pulse delay circuit, the second detection circuit is configured to detect an input voltage of the clamping circuit and is turned on when the input voltage of the clamping circuit is higher than a first preset value, the pulse delay circuit has an input end and an output end, the input end of the pulse delay circuit is coupled to the second detection circuit, the output end of the pulse delay circuit is coupled to the control end of the third switching tube, and when the first end of the pulse delay circuit receives a rising edge signal from the second detection circuit, the second end of the pulse delay circuit delays to output the first pulse signal.

Optionally, the second detection circuit includes a fourth switching tube, the fourth switching tube has a first end, a second end and a control end, wherein the first end of the fourth switching tube is coupled to the input voltage of the clamping circuit, the second end of the fourth switching tube is coupled to the control end of the first switching tube, and the control end of the fourth switching tube is coupled to a second reference voltage, wherein a sum of the second reference voltage and a switching threshold of the second switching tube reflects the second preset value.

Optionally, the size of the fourth switching tube is much smaller than that of the second switching tube.

Optionally, the clamping circuit further comprises an electrostatic protection circuit, the electrostatic protection circuit is coupled between the third switching tube and a reference ground, the electrostatic protection circuit is normally turned on, and when an ESD event occurs, the electrostatic protection circuit is turned off.

Optionally, the ESD protection circuit includes a fifth switching tube, where the fifth switching tube has a first end, a second end, and a control end, the first end of the fifth switching tube is coupled to the second end of the third switching tube, the second end of the fifth switching tube is coupled to a ground reference, and the control end of the fifth switching tube is coupled to a second pulse signal, where the second pulse signal outputs a high level at normal state and outputs a low level when an ESD event occurs.

Optionally, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are MOS tubes, wherein the first switch tube, the third switch tube and the fifth switch tube are NMOS tubes, and the second switch tube and the fourth switch tube are PMOS tubes.

Optionally, the clamping circuit further includes a first zener diode and a second zener diode, two ends of the first zener diode are respectively coupled to the control end of the first switching tube and the reference ground, and two ends of the second zener diode are respectively coupled to the input end of the pulse delay circuit and the reference ground.

Optionally, the clamping circuit further includes a first capacitor, a second capacitor, and a third capacitor, two ends of the first capacitor are respectively coupled to the control terminal of the first switching tube and the input voltage of the clamping circuit, two ends of the second capacitor are respectively coupled to the output terminal of the pulse delay circuit and the input voltage of the clamping circuit, and two ends of the third capacitor are respectively coupled to the control terminal of the fifth switching tube and the reference ground.

Optionally, the clamping circuit further includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor, two ends of the first resistor are respectively coupled to the control terminal of the first switching transistor and the ground reference, two ends of the second resistor are respectively coupled to the first terminal of the second switching transistor and the input voltage of the clamping circuit, two ends of the third resistor are respectively coupled to the first terminal of the fourth switching transistor and the input voltage of the clamping circuit, two ends of the fourth resistor are respectively coupled to the input terminal of the pulse delay circuit and the ground reference, and two ends of the fifth resistor are respectively coupled to the control terminal of the fifth switching transistor and the second pulse signal.

The embodiment of the invention provides a clamping circuit which comprises a first detection circuit, a first switching tube and a discharge circuit. The first detection circuit can detect the state of the input voltage of the clamping circuit input voltage clamping circuit, when a voltage peak occurs, the first detection circuit is conducted to provide a high level signal for the control end of the first switch, and the control end of the first switch tube is controlled to be conducted after receiving the high level signal. After the first switching tube is conducted, the input voltage of the clamping circuit input voltage clamping circuit is directly grounded, so that voltage spikes are restrained. When the input voltage of the clamp circuit input voltage is reduced, the control end of the first switch tube is still in a high level state, and the control end in the high level state can cause the clamp circuit to generate more power consumption. The discharge circuit is arranged to actively discharge the control end of the first switch tube, so that the power consumption of the clamping circuit can be reduced.

Other advantages of the present invention will be described in the detailed description, which is provided by the technical features and technical solutions.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a block diagram of a conventional clamping circuit;

FIG. 2 is a waveform diagram of a conventional clamp circuit;

FIG. 3 shows a clamp circuit diagram according to an embodiment of the invention;

FIG. 4 illustrates a waveform diagram of a clamp circuit according to an embodiment of the present invention;

fig. 5 shows a diagram of a clamp circuit configuration according to an embodiment of the present invention.

Detailed Description

For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.

The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. Combinations of different embodiments, and substitutions of features from different embodiments, or similar prior art means may be substituted for or substituted for features of the embodiments shown and described.

The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a conductor, wherein the electrically conductive medium may contain parasitic inductance or parasitic capacitance, or through an intermediate circuit or component as described in the embodiments in the specification; indirect connections may also include connections through other active or passive devices that perform the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, and so on. "plurality" or "plurality" means two or more.

Example one

Before the embodiments of the present invention are specifically described, VIN, VREF, and GND in the drawings respectively represent an input voltage, a reference voltage, and a reference ground of the clamp circuit; PM1, PM2, NM1, NM2 and NM3 respectively represent a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube; n1 and n2 respectively represent the input end of the pulse delay circuit and the output end of the pulse delay circuit; NGATE represents the gate voltage of the first NMOS.

Referring to fig. 3 and 4, the embodiment of the invention provides a clamp circuit, which adds a pulse delay circuit 100, a second PMOS transistor PM2 and a second NMOS transistor NM2 on the basis of a conventional clamp circuit.

In a common clamp circuit, a first PMOS transistor PM1 and a first NMOS transistor NM1 are included. The source, the gate and the drain of the PM1 are respectively connected with the gates of VIN, VREF and NM 1; the source and drain of NM1 are connected to GND and VIN, respectively.

When voltage spike occurs and VIN rises to be higher than VREF by a PMOS threshold voltage (time t 1), PM1 is conducted to charge the gate capacitance of NM 1; when the gate voltage of NM1 is higher than the threshold voltage of NMOS (time t 2), NM1 turns on and starts to discharge VIN, thereby realizing voltage clamping on VIN;

when VIN voltage is lower than VREF plus a PMOS threshold voltage (at time t 3), PM1 is turned off, and the first resistor R1 gradually drains the gate voltage of NM1 to ground; when the gate voltage of NM1 is lower than the threshold voltage of NMOS (time t 4), NM1 is turned off.

The pulse delay circuit 100, the PM2, and the NM2 are components added on the basis of a common clamp circuit. Wherein, the source, gate and drain of PM2 are connected to VIN, VREF and the input of pulse delay circuit 100, respectively; the source, gate and drain of NM2 are connected to GND, the output terminal of pulse delay circuit 100 and the gate of NM1, respectively.

Where PM2 may be viewed as a copy of PM1 such that changes in VIN felt by PM2 are synchronized with PM 1. Further, by sizing PM2 to be much smaller than PM1, i.e., the parasitic capacitance of n1 to be much smaller than that of NGATE, the voltage at point n1 rises faster than NGATE, so that the pulse delay circuit can more effectively detect the rising edge at point n 1. In the present embodiment, the dimension of PM2 is significantly smaller than the dimension of PM1 by a factor of 5 or more.

The pulse delay circuit 100 is used as a dc converter to convert an input voltage n1 into an output voltage n2, and when a delay time elapses from the start of rising n1 to the start of rising n2, NM2 is turned on when n2 rises (time t 3). Further, the pulse delay circuit 100 is a pulse stretching delay circuit, which can stretch the pulse signal of n2, and extend the time that n2 remains high, ensuring that NGATE is pulled down to ground.

NM2 is turned on when n2 is kept at a high level, and discharges the gate voltage of NM 1. It should be noted that NM2 may be replaced by a PMOS transistor instead of an NMOS transistor, but the effect of using a PMOS transistor is not as good as that of using an NMOS transistor. The reason is that: the gate of the PMOS is at 0 level, and its source terminal (i.e. NGATE node) can only be lowered to the threshold voltage of the PMOS at the lowest, and under some process conditions, the threshold voltage of the PMOS is higher than the threshold voltage of NM1, then NM1 cannot be effectively turned off, and Q2 cannot be effectively reduced.

Further, the clamp circuit further includes a third NMOS transistor NM 3. The source, gate, and drain of NM3 are connected to GND, a pulse signal that outputs a high level at normal state, and a low level when an ESD event occurs, and the source, gate, and drain of NM2, respectively. The pulse signal enables NM3 to be in a conducting state in a normal state, and NM3 is in a shutdown state when an ESD event occurs (VIN is positive to GND), so that NGATE can keep a high level for a long time and completely discharge ESD energy on VIN.

Specifically, referring to fig. 3 and 4, the operating principle of the clamp circuit according to the embodiment of the present invention is as follows:

when VIN rises one PMOS _ Vth higher than VREF (time t 1), PM1 and PM2 turn on, NGATE and n1 start rising; when the NGATE voltage rises to an NMOS _ Vth (time t 2), NM1 turns on, and starts to discharge VIN; after a period of time from the rise of n1 to the rise of n2, when n2 rises (at time t 3), NM2 turns on, NM2 pulls the NGATE voltage low quickly, and n2 remains high for a period of time, ensuring that NGATE is pulled low to ground. When the NGATE voltage is below an NMOS _ Vth (time t 4), NM1 turns off, stopping drawing current from VIN. Through the active discharge of NM2, the time of t3~ t4 has been shortened greatly, has reduced the loss to the VIN energy.

Therefore, the present embodiment has at least the following advantages compared to the clamp circuit in the background art:

(1) the NM2 is adopted to carry out active discharge on the grid voltage of NM1, so that the time of t 3-t 4 is shortened, and the loss of VIN energy is reduced;

(2) on the basis of the original clamping circuit, only a few circuit components are added, the size of PM2 is far smaller than that of PM1, only a very small circuit area is added, and the chip area is not wasted;

(3) the size of PM2 is much smaller than PM1, i.e., the parasitic capacitance of n1 is much smaller than that of NGATE, and the voltage at point n1 rises faster than that at NGATE, so that the pulse delay circuit can more effectively detect the rising edge at point n 1.

Example two

The first embodiment shows that the loss of VIN energy is high because the gate voltage of NM1 cannot be released in time, and therefore, referring to fig. 3 and 5, the embodiment of the present invention provides a more applicable clamping circuit, which includes a first detecting circuit 210, a first switch 220 and a discharging circuit 230.

The first detection circuit 210 is connected to the input voltage of the clamp circuit and the control terminal of the first switch tube 220, and is turned on when the input voltage of the clamp circuit is higher than a first preset value, and the control terminal of the first switch tube 220 starts to rise, that is, the first detection circuit 210 in this embodiment serves as a control circuit that can detect a change in the input voltage of the clamp circuit and perform on/off control according to the detected input voltage of the clamp circuit.

Specifically, one possible embodiment of the first detection circuit 210 is: the first detecting circuit 210 includes a first comparing circuit, a first input terminal of the first comparing circuit is coupled to the input voltage of the clamping circuit, a second input terminal of the first comparator is coupled to a first reference voltage, a voltage value of the first reference voltage is a first predetermined value, and an output terminal of the first comparing circuit is coupled to the first control of the first switch 220. When the input voltage of the clamping circuit is greater than the first reference voltage, the first comparing circuit is turned on, and at this time, the first comparing circuit outputs a high level, and the voltage at the control terminal of the first switching tube 220 starts to rise. When the input voltage of the clamping circuit is not greater than the first reference voltage, the first comparison circuit is turned off, and the first comparison circuit outputs a low level without affecting the voltage of the control terminal of the first switching tube 220.

Specifically, one possible embodiment of the first detection circuit 210 is: the first detection circuit 210 includes a second switch tube (refer to PM1 in fig. 3) having a first terminal, a second terminal and a third terminal, wherein the first terminal, the second terminal and the third terminal are an input terminal, an output terminal and a control terminal of the second switch tube, respectively. The first end of the second switch tube is coupled to the input voltage of the clamping circuit, the second end of the second switch tube is coupled to the control end of the first switch tube 220, and the control end of the second switch tube is coupled to a second reference voltage, wherein the second reference voltage and the switching threshold of the second switch tube are a second preset value. When the input voltage of the clamping circuit exceeds the second reference voltage by at least one switching threshold voltage, the second switching tube is turned on, and the control end voltage of the first switching tube 220 begins to rise. When the input voltage of the clamp circuit does not exceed the sum of the second reference voltage and the switching threshold voltage, the second switching tube is turned off, and the voltage of the third end of the first switching tube 220 is not affected. Considering that a faster feedback speed is required for adjusting the voltage and the coupling manner of the second switch tube, the second switch tube in this embodiment is preferably a PMOS tube.

The first switch tube 220 controls the on/off of the first switch tube 220 by controlling the change of the terminal voltage. The first switch tube 220 has a first end, a second end and a third end, wherein the first end, the second end and the third end are an input end, an output end and a control end of the first switch tube 220, respectively. A first terminal of the first switch tube 220 is coupled to the input voltage of the clamping circuit, and a second terminal of the first switch tube 220 is coupled to the ground reference. As can be seen from the above, after the first detection circuit 210 is turned on, the control terminal voltage of the first switch tube 220 starts to rise. When the voltage at the control end of the first switch tube 220 rises to the second preset value, the first switch tube 220 is turned on, and at this time, the input voltage of the clamp circuit is grounded through the first switch tube 220, so that the input voltage of the clamp circuit is reduced, and the voltage spike is suppressed. When the input voltage of the clamp circuit decreases to be lower than the first predetermined value, as can be seen from the above, the first detection circuit 210 is turned off, and the third terminal voltage of the first switch 220 is no longer affected by the first detection circuit 210. Considering the requirement of faster feedback speed for adjusting the voltage and the coupling manner of the first switch tube 220, the first switch tube 220 in this embodiment is preferably an NMOS tube.

The discharge circuit 230 is configured to timely release the voltage at the control end of the first switch tube 220, so as to reduce energy loss of the clamp circuit. Specifically, the discharging circuit 230 is coupled to the control terminal of the first switch tube 220, and controls the voltage of the control terminal of the first switch tube 220 to decrease after the first switch tube 220 is turned on for a period of time. Specifically, the discharge circuit 230 includes a third switching tube (refer to NM2 of fig. 3) having a first terminal, a second terminal, and a third terminal, wherein the first terminal, the second terminal, and the third terminal are an input terminal, an output terminal, and a control terminal of the discharge circuit 230, respectively. The first terminal of the third switch is coupled to the control terminal of the first switch 220, the second terminal of the third switch is coupled to the ground reference, and the control terminal of the third switch is coupled to the first pulse signal. The first pulse signal can output a high level after the first switch tube 220 is turned on for a period of time, and control the third switch tube to be turned on. The first pulse signal may be set to different start times and durations depending on the clamp parameters. Considering that a faster feedback speed is required for adjusting the voltage and the coupling manner of the third switch tube, the NMOS tube is preferably selected as the third switch tube in this embodiment.

Optionally, the clamping circuit further includes a delay pulse circuit 100, and an input end and an output end of the delay pulse circuit 100 are coupled to the first detection circuit 210 and a control end of the third switch transistor, respectively. The delay pulse signal can delay the input pulse signal and output, that is, the first pulse signal is provided to the third switch tube, so that after the first switch tube 220 is turned on for a period of time, the third end of the third switch tube can receive a high level to control the third switch tube to be turned on. When the input terminal of the delay pulse circuit 100 receives the rising edge signal of the first detection circuit 210, it indicates that the first detection circuit 210 is turned on at this time, and the voltage at the third terminal of the first switch tube 220 starts to rise. And calculating a time period t1 when the voltage at the third end of the first switch tube 220 starts to rise to the second preset value and a minimum time period t2 when the first switch tube 220 needs to be conducted, wherein the delay time period of the delay pulse circuit 100 is a certain time period which is greater than the sum of t1 and t 2.

Optionally, the clamping circuit further comprises a second detection circuit. After the second detection circuit is added, the input terminal of the aforementioned delay pulse circuit 100 is coupled to the second detection circuit instead. The second detection circuit can be regarded as a replica of the first detection circuit 210, and by providing the second detection circuit, the first detection circuit 210 can be prevented from overcurrent. Referring to the above-described embodiment of the first detection circuit 210, the second detection circuit includes a second comparison circuit or a fourth switching tube (see PM2 of fig. 3). Furthermore, the fourth switch tube is a PMOS tube. In order to enable the input end of the pulse delay circuit to more effectively detect the rising edge signal, considering that the rising speed of the output voltage is faster after the small-size PMOS tube is conducted, the size of the fourth switching tube PMOS tube is set to be far smaller than that of the second switching tube PMOS tube.

Optionally, the clamping circuit further comprises an electrostatic protection circuit. The electrostatic protection circuit is coupled between the third switching tube and the reference ground. In a normal state, the electrostatic protection circuit is in a conducting state, and when an ESD event occurs (VIN is positive to GND), the electrostatic protection circuit is turned off, so that the control end of the first switch tube 220 can be kept at a high level for a long time, and ESD energy on the input voltage of the clamp circuit is completely discharged.

Optionally, the electrostatic protection circuit includes a fifth switching tube (refer to NM3 of fig. 3) and a second pulse signal controlling on/off of the fifth switching tube. The fifth switch tube is provided with a first end, a second end and a third end, wherein the first end, the second end and the third end are respectively an input end, an output end and a control end of the fifth switch tube. The first end of the fifth switching tube is coupled to the second end of the third switching tube, the second end of the fifth switching tube is coupled to the reference ground, and the control end of the fifth switching tube is coupled to the second pulse signal. The second pulse signal outputs a high level at normal state, and outputs a low level when an ESD event occurs. Furthermore, the fifth switch tube is an NMOS tube.

Optionally, the clamping circuit further comprises a first Zener diode Zener1 and a second Zener diode Zener 2. Two ends of the Zener1 are respectively coupled to the third terminal of the first switch tube 220 and the ground, and two ends of the Zener2 are respectively coupled to the input terminal of the pulse delay circuit and the ground. Wherein Zener1 protects the control terminal of the first switch tube 220 from over-voltage, and Zener2 protects the input terminal of the pulse delay circuit from over-voltage.

Optionally, the clamping circuit further includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. Two ends of the C1 are respectively coupled to the control end of the first switch tube 220 and the input voltage of the clamp circuit, two ends of the C2 are respectively coupled to the input end of the pulse delay circuit 100 and the input voltage of the clamp circuit, and two ends of the C3 are respectively coupled to the control end of the fifth switch tube and the reference ground. The C1 is used to increase the response speed of the control terminal of the first switch tube 220, the C2 is used to increase the response speed of the input terminal of the pulse delay circuit 100, and the C3 is used to increase the response speed of the control terminal of the fifth switch tube.

Optionally, the clamp circuit further includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. Two ends of the first resistor are respectively coupled to the control end of the first switch tube 220 and the reference ground, two ends of the second resistor are respectively coupled to the first end of the second switch tube and the input voltage of the clamping circuit, two ends of the third resistor are respectively coupled to the first end of the fourth switch tube and the input voltage of the clamping circuit, two ends of the fourth resistor are respectively coupled to the first end of the pulse delay circuit and the reference ground, and two ends of the fifth resistor are respectively coupled to the control end of the fifth switch tube and the second pulse signal. Wherein, R2 is used for limiting the current flowing through Zener1 while protecting the parasitic capacitance of the second switching tube from overvoltage, R3 is used for limiting the current flowing through Zener2 while protecting the parasitic capacitance of the fourth switching tube from overvoltage, and R4 is used for protecting the input end of the pulse delay circuit from overvoltage together with Zener 2.

The embodiment of the invention provides a clamping circuit, which comprises a first detection circuit 210, a first switch tube 220 and a discharge circuit 230. The first detection circuit 210 may detect a state of an input voltage of the clamp circuit, when a voltage spike occurs, the first detection circuit 210 is turned on to provide a high level signal to the control end of the first switch, and the control end of the first switch tube 220 receives the high level signal to control the first switch tube 220 to be turned on. After the first switch tube 220 is turned on, the input voltage of the clamp circuit is directly grounded, so that voltage spike is suppressed. When the input voltage of the clamp circuit is reduced, the control terminal of the first switch 220 is still in a high level state, and the control terminal in this state may cause the clamp circuit to generate more power consumption. The discharge circuit 230 is arranged to actively discharge the control end of the first switch tube 220, so that the power consumption of the clamping circuit can be reduced.

Those skilled in the art should understand that the logic controls such as "high level" and "low level", "set" and "reset", "and gate" and "or gate", "non-inverting input" and "inverting input" in the logic controls referred to in the specification or the drawings can be interchanged or changed, and the subsequent logic controls can be adjusted to achieve the same functions or purposes as the above-described embodiments.

The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. The description related to the effect or advantage mentioned in the specification may not be embodied in the actual experimental examples due to the uncertainty of specific condition parameters or other factors, and the description related to the effect or advantage is not intended to limit the scope of the invention. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims

1. A clamping circuit, comprising:

the second NMOS tube is provided with a source electrode, a drain electrode and a grid electrode, the source electrode of the second NMOS tube is coupled with the reference ground, and the drain electrode of the second NMOS tube is coupled with the grid electrode of the first NMOS tube;

2. The clamping circuit of claim 1, wherein: the third NMOS tube is coupled between the second NMOS tube and a reference ground and is provided with a source electrode, a drain electrode and a grid electrode, the source electrode of the third NMOS tube is coupled with the reference ground, the drain electrode of the third NMOS tube is coupled with the source electrode of the second NMOS tube, and the grid electrode of the third NMOS tube is coupled with a pulse signal, wherein the pulse signal normally outputs a high level, and when an ESD event occurs, the pulse signal outputs a low level.

3. A clamping circuit, comprising:

the discharge circuit is coupled with the control end of the first switching tube and used for controlling the voltage of the control end of the first switching tube to be reduced to be lower than the second preset value after receiving the first pulse signal;

the input end of the pulse delay circuit is coupled with the first detection circuit, the output end of the pulse delay circuit is coupled with the discharge circuit, and after the input end of the pulse delay circuit receives a rising edge signal from the first detection circuit, the output end of the pulse delay circuit delays and outputs the first pulse signal.

4. A clamping circuit, comprising:

the first detection circuit is used for detecting the input voltage of the clamping circuit and is switched on when the input voltage of the clamping circuit is higher than a first preset value;

the second detection circuit is used for detecting the input voltage of the clamping circuit and conducting when the input voltage of the clamping circuit is higher than a first preset value;

and the input end of the pulse delay circuit is coupled with the second detection circuit, the output end of the pulse delay circuit is coupled with the discharge circuit, and the output end of the pulse delay circuit delays and outputs the first pulse signal after the input end of the pulse delay circuit receives a rising edge signal from the second detection circuit.

5. The clamp circuit of claim 4, wherein: the first detection circuit comprises a first comparison circuit, wherein the first comparison circuit is provided with a first input end, a second input end and an output end, the first input end of the first comparison circuit is coupled with the input voltage of the clamping circuit, the second input end of the first comparison circuit is coupled with a first reference voltage, the output end of the first comparison circuit is coupled with the control end of the first switch tube, and the first reference voltage reflects the first preset value.

6. The clamping circuit of claim 4, wherein: the first detection circuit comprises a second switch tube, the second switch tube is provided with a first end, a second end and a control end, the first end of the second switch tube is coupled with the input voltage of the clamping circuit, the second end of the second switch tube is coupled with the control end of the first switch tube, the control end of the second switch tube is coupled with a second reference voltage, and the sum of the second reference voltage and the switching threshold value of the second switch tube reflects the first preset value.

7. The clamping circuit of claim 6, wherein: the discharge circuit comprises a third switching tube, wherein the third switching tube is provided with a first end, a second end and a control end, the first end of the third switching tube is coupled with the control end of the first switching tube, the second end of the third switching tube is coupled with a reference ground, the control end of the third switching tube is coupled with a first pulse signal, and the first pulse signal outputs high level after the first switching tube is conducted for a period of time.

8. The clamping circuit of claim 7, wherein: the second detection circuit comprises a fourth switch tube, the fourth switch tube is provided with a first end, a second end and a control end, the first end of the fourth switch tube is coupled with the input voltage of the clamping circuit, the second end of the fourth switch tube is coupled with the input end of the pulse delay circuit, the control end of the fourth switch tube is coupled with a second reference voltage, and the sum of the second reference voltage and the switching threshold value of the second switch tube reflects the first preset value.

9. The clamping circuit of claim 8, wherein: the size of the fourth switching tube is far smaller than that of the second switching tube.

10. The clamp circuit of claim 9, wherein: the ESD protection circuit is coupled between the third switching tube and the reference ground, is normally turned on, and is turned off when an ESD event occurs.

11. The clamping circuit of claim 10, wherein: the electrostatic protection circuit comprises a fifth switching tube, wherein the fifth switching tube is provided with a first end, a second end and a control end, the first end of the fifth switching tube is coupled with the second end of the third switching tube, the second end of the fifth switching tube is coupled with the reference ground, the control end of the fifth switching tube is coupled with a second pulse signal, the second pulse signal outputs a high level under a normal state, and when an ESD event occurs, the control end of the fifth switching tube outputs a low level.

12. The clamping circuit of claim 11, wherein: the first switch tube, the second switch tube, the third switch tube, the fourth switch tube and the fifth switch tube are MOS tubes, wherein the first switch tube, the third switch tube and the fifth switch tube are NMOS tubes, and the second switch tube and the fourth switch tube are PMOS tubes.

13. The clamping circuit of claim 12, wherein: the pulse delay circuit further comprises a first voltage stabilizing diode and a second voltage stabilizing diode, wherein two ends of the first voltage stabilizing diode are respectively coupled with the control end of the first switch tube and the reference ground, and two ends of the second voltage stabilizing diode are respectively coupled with the input end of the pulse delay circuit and the reference ground.

14. The clamping circuit of claim 13, wherein: the pulse delay circuit further comprises a first capacitor, a second capacitor and a third capacitor, wherein two ends of the first capacitor are respectively coupled to the control end of the first switch tube and the input voltage of the clamping circuit, two ends of the second capacitor are respectively coupled to the input end of the pulse delay circuit and the input voltage of the clamping circuit, and two ends of the third capacitor are respectively coupled to the control end of the fifth switch tube and the reference ground.

15. The clamping circuit of claim 14, wherein: the pulse delay circuit further comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor, wherein two ends of the first resistor are respectively coupled to the control end of the first switching tube and the reference ground, two ends of the second resistor are respectively coupled to the first end of the second switching tube and the input voltage of the clamping circuit, two ends of the third resistor are respectively coupled to the first end of the fourth switching tube and the input voltage of the clamping circuit, two ends of the fourth resistor are respectively coupled to the input end of the pulse delay circuit and the reference ground, and two ends of the fifth resistor are respectively coupled to the control end of the fifth switching tube and the second pulse signal.