CN110208673A - A kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter - Google Patents
A kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter Download PDFInfo
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- CN110208673A CN110208673A CN201910504709.8A CN201910504709A CN110208673A CN 110208673 A CN110208673 A CN 110208673A CN 201910504709 A CN201910504709 A CN 201910504709A CN 110208673 A CN110208673 A CN 110208673A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
- G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
- G01R19/16557—Logic probes, i.e. circuits indicating logic state (high, low, O)
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/1213—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for DC-DC converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
Abstract
A kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter, including voltage sample module, time reference generation module and logical operation module, voltage sample module is used for the grid signal of sampled power pipe and exports sampled signal, and the delay time of the grid signal of sampled signal and power tube is T1；Time reference generation module generates narrow pulse signal after being used to carry out the control signal of power tube the delay that delay time is T2, and narrow pulse signal is as time reference signal, the same phase of grid signal of the control signal and power tube of power tube；Logical operation module generates under-voltage signal when T1 is greater than T2 for comparing sampled signal and time reference signal.The present invention is compared using time reference signal with the sampled voltage of power tube, whether the high side power pipe and lowside power pipe being able to detect in DC-DC converter are under-voltage, have the characteristics that quick and accurate, under-voltage signal returns to the stability and efficiency that control power tube is able to ascend DC-DC converter.
Description
Technical field
The invention belongs to electronic circuit technology fields, are related to a kind of for detecting power tube grid source electricity in DC-DC converter
Pressure whether under-voltage undervoltage detection circuit, be able to detect the high side power pipe and lowside power pipe of DC-DC converter.
Background technique
Efficiency be measure DC-DC converter performance one of important indicator, the index can with converter output power with
The ratio of input power is measured.By taking Buck converter as an example, many because being known as of Buck transducer effciency are influenced, such as power tube
The core loss of the conduction loss, inductance that are generated in the switching loss that generates during opening and shutting off, power tube turn on process,
Quiescent dissipation of internal circuit etc..As shown in Figure 1, Buck converter working efficiency highest in medium load, light
Efficiency can be decayed under load and case of heavy load.Light-load efficiency decaying is mainly caused by switching loss；Heavily loaded efficiency decaying master
To be caused by conduction loss.
Conduction loss PconIt can be calculate by the following formula and obtain:
Wherein, IrmsIt is the virtual value of inductive current, Rds(on)It is power tube conducting resistance.Since power tube works linear
The expression formula in area, conducting resistance is as follows:
It wherein, is the product of electron mobility and unit area gate oxide capacitance for N-type power tube k, Vth is power
The threshold voltage of pipe,For the breadth length ratio of power tube, k, Vth are the technological parameters of power tube itself, and W, L are in design circuit
When selected, therefore determine that the parameter of power tube conduction impedance only has the gate source voltage V of power tubeGS。
Traditional Buck converter using N-type transistor as power tube, when opening high side power pipe, grid voltage
It is generally necessary to be lifted to the value higher than converter input voltage by bootstrap technique, and exist in frequency applications or converter work
In the case where discontinuous conduction mode, it is possible that the problem of not enough power supply, this allows for high side power pipe and exists bootstrap capacitor
Gate source voltage is lower than target value to attenuation factor efficiency in opening process.
Detection that traditional high side power pipe gate source voltage is under-voltage is usually to generate benchmark between floating power supply rail SW and BST
Voltage, then by high side power pipe gate source voltage compared with reference voltage.Reference generating circuit is located at floating power supply in this design
Rail, reference voltage value is to change with switching frequency relative to signal ground, so for high frequency, high-voltage applications often speed and essence
Degree will receive limitation.
Summary of the invention
It is led for above-mentioned Buck converter is that may be present during the work time since high side power pipe gate source voltage is under-voltage
Generating reference voltage in the efficiency attenuation problem of cause, and the under-voltage detection method of tradition in floating power supply rail leads to high frequency, height
The limited problem of speed and precision, the present invention propose a kind of undervoltage detection circuit in pressure application, using time reference detection mode,
High side power pipe or low is detected compared with time reference signal by sampling high side power pipe or lowside power tube grid signal
Whether the gate source voltage of side power tube is under-voltage, is suitable for DC-DC converter；It is examined using undervoltage detection circuit proposed by the present invention
When generation that survey high side power pipe is under-voltage, high side power pipe is turned off until under-voltage end, energy as enable signal by under-voltage signal
Enough avoid unnecessary conduction loss.
The technical solution of the present invention is as follows:
A kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter, the undervoltage detection circuit packet
Voltage sample module, time reference generation module and logical operation module are included,
The voltage sample module is used to sample the grid signal of the power tube and exports sampled signal, the sampling letter
It number is T1 with the delay time of the grid signal of the power tube；
The time reference generation module is used to the control signal of the power tube carrying out the delay that delay time is T2
After generate narrow pulse signal, the narrow pulse signal is as time reference signal, the control signal and the function of the power tube
The same phase of the grid signal of rate pipe；
The logical operation module is used for the sampled signal and time reference signal, generates and owes when T1 is greater than T2
Press signal.
Specifically, the voltage sample module includes sampling unit, the sampling unit includes the first PMOS tube, second
PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the first NMOS tube, the second NMOS tube, first
Resistance and the first current source,
The grid of first PMOS tube connects the source electrode of third PMOS tube and the input terminal as the voltage sample module,
Source electrode connects the source electrode of the second PMOS tube, the 4th PMOS tube and the 6th PMOS tube and connects the opposite of the sampling unit power rail
High level, the drain electrode of drain electrode the first NMOS tube of connection and the second PMOS tube and the grid of the second NMOS tube and the 4th PMOS tube
Pole；
The grid of the grid connection third PMOS tube of first NMOS tube is with drain electrode and by connecting first after first resistor
The source electrode and the sampling unit power rail of NMOS tube and the second NMOS tube it is relatively low-level；
The grid of 5th PMOS tube connects the grid of the second PMOS tube and the grid of the 6th PMOS tube and drains and pass through
The relatively low-level of the sampling unit power rail is connected after first current source, source electrode connects the drain electrode of the 4th PMOS tube,
The drain electrode of drain electrode the second NMOS tube of connection simultaneously exports the output signal of the sampling unit, the output signal of the sampling unit with
The grid signal of the power tube changes.
Specifically, the power rail of the sampling unit is the DC-DC converter when power tube is lowside power pipe
Low side power rail, the opposite high level of the power rail of the sampling unit is low-tension supply, the power rail of the sampling unit
It is relatively low-level be ground level, the input terminal of the sampling unit connects the grid signal of the lowside power pipe, described to adopt
The output signal of sample unit is the sampled signal.
Specifically, the power rail of the sampling unit is the DC-DC converter when power tube is high side power pipe
High side power rail, the opposite high level of the power rail of the sampling unit is the floating power supply of the DC-DC converter, described
Level at the relatively low-level switching node for the DC-DC converter of the power rail of sampling unit, the sampling unit
Input terminal connects the grid signal of the high side power pipe；
The voltage sample module further includes level shift unit, and the level shift unit is used for the sampling unit
Output signal make after the low side power rail that the high side power rail of the DC-DC converter is converted to the DC-DC converter
For the sampled signal.
Specifically, the level shift unit include third NMOS tube, the 4th NMOS tube, the 7th PMOS tube, second resistance,
First resistance to piezoelectric crystal, the second resistance to piezoelectric crystal, the first phase inverter and the second phase inverter,
The grid and source electrode of grid the first resistance to piezoelectric crystal of connection of second resistance to piezoelectric crystal and the DC-DC converter
Switching node at level, source electrode connects the output signal of the sampling unit, drain electrode connection the 4th NMOS tube and the 7th
The input terminal of the drain electrode of PMOS tube and the first phase inverter；
The drain electrode of grid and drain electrode the first resistance to piezoelectric crystal of connection of third NMOS tube and the grid of the 4th NMOS tube simultaneously lead to
The grid for connecting the 7th PMOS tube and source electrode and low-tension supply are crossed after second resistance, and source electrode connects the source electrode of the 4th NMOS tube
And connect ground level；
The input terminal of second phase inverter connects the output end of the first phase inverter, and output end exports the sampled signal.
Specifically, the time reference generation module includes third phase inverter, the 4th phase inverter, the 5th phase inverter, the 6th
Phase inverter, the 7th phase inverter, the 8th phase inverter, 3rd resistor, first capacitor, the second capacitor, the 5th NMOS tube, the 8th PMOS tube
With the first NAND gate,
The input terminal of third phase inverter connects the control signal of the power tube, and output end connects the 5th NMOS tube and the
The grid of eight PMOS tube；
The source electrode of 8th PMOS tube connects low-tension supply, the drain electrode that drain electrode passes through the 5th NMOS tube of connection after 3rd resistor
Input terminal with the 4th phase inverter and source electrode and ground level by connecting the 5th NMOS tube after first capacitor；
The input terminal of 5th phase inverter connects the output end of the 4th phase inverter, and output end connects the input of hex inverter
The first input end at end and the first NAND gate；
The input terminal of 7th phase inverter connects the output end of hex inverter and by connecting ground level after the second capacitor,
Output end connects the second input terminal of the first NAND gate after passing through the 8th phase inverter；
The output end of first NAND gate exports the time reference signal.
Specifically, the logical operation module includes the first nor gate, two input terminals of the first nor gate are separately connected
The time reference signal and sampled signal, output end export the under-voltage signal.
The invention has the benefit that undervoltage detection circuit proposed by the present invention passes through generation time reference signal and power
Whether the sampled signal of pipe is compared, under-voltage for detecting power tube gate source voltage, with traditional between floating power supply rail
It generates reference voltage to compare, is improved, has the characteristics that quick and accurate in speed and precision；It is proposed by the present invention to owe
Pressure detection can be used in detecting the high side power pipe and lowside power pipe in DC-DC converter, the under-voltage signal energy detected
Control power tube is enough returned to be switched on and off, can optimization system during the work time issuable signal false triggering is asked
Topic.
Detailed description of the invention
Fig. 1 is Buck transducer effciency with output impedance variation characteristic schematic diagram.
Fig. 2 is that a kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter proposed by the present invention is used
Structural schematic diagram when detecting high side power pipe.
Fig. 3 is that a kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter proposed by the present invention is used
The circuit structure diagram of sampling unit when detecting high side power pipe.
Fig. 4 is that a kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter proposed by the present invention is used
The practical circuit diagram of level shift level-down unit when detecting high side power pipe.
Fig. 5 is that a kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter proposed by the present invention is used
The practical circuit diagram of time reference generation module and logical operation module when detecting high side power pipe.
Fig. 6 is that a kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter proposed by the present invention is used
Timing diagram when detecting high side power pipe.
Specific embodiment
The invention will be further elaborated with specific embodiment with reference to the accompanying drawing.
Undervoltage detection circuit proposed by the present invention by using time reference detect DC-DC converter in power tube whether mistake
Pressure, including voltage sample module, time reference generation module and logical operation module, voltage sample module are used for sampled power pipe
Grid signal and generate sampled signal, time reference generation module for generating narrow pulse signal as time reference signal,
Sampled signal is compared to obtain under-voltage signal with time reference signal, the present invention can be suitable for the height of DC-DC converter
Side power tube and lowside power pipe.The course of work and work that the present invention will be described in detail for detecting high side power pipe below are former
Reason.
It is structural schematic diagram when undervoltage detection circuit proposed by the present invention is used to detect high side power pipe as shown in Figure 2,
Including voltage sample module, time reference generation module and logical operation module.Wherein voltage sample module includes for sampling
The sampling unit of high side power pipe gate source voltage, is illustrated in figure 3 a kind of realization circuit of sampling unit, and sampling unit includes the
One PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS
Pipe MP6, the first NMOS tube MN1, the second NMOS tube MN2, first resistor R1 and the first current source, the grid of the first PMOS tube MP1
Connect the source electrode of third PMOS tube MP3 and the grid signal as the input terminal of voltage sample module connection high side power pipe
DRVH, source electrode connect the source electrode of the second PMOS tube MP2, the 4th PMOS tube MP4 and the 6th PMOS tube MP6 and connect sampling unit
The opposite high level of power rail, the drain electrode and the second NMOS tube of drain electrode connection the first NMOS tube MN1 and the second PMOS tube MP2
The grid of MN2 and the 4th PMOS tube MP4；The grid of the grid connection third PMOS tube MP3 of first NMOS tube MN1 and drain electrode are simultaneously led to
The opposite of the source electrode and sampling unit power rail for connecting the first NMOS tube MN1 and the second NMOS tube MN2 is crossed after first resistor R1
Low level；The grid of 5th PMOS tube MP5 connects grid and the leakage of the grid and the 6th PMOS tube MP6 of the second PMOS tube MP2
Pole and by connecting the relatively low-level of sampling unit power rail after the first current source, source electrode connects the 4th PMOS tube MP4's
Drain electrode, the drain electrode of the second NMOS tube MN2 of drain electrode connection simultaneously export the output signal DRVH ' of sampling unit, sampling unit it is defeated
Signal changes with the grid signal of power tube out.
For Buck converter using N-type transistor as power tube, switching node SW is the source electrode of high side power pipe, when
When Buck converter lowside power pipe is opened, SW level is approximately chip low level；When Buck converter high side power pipe is opened
When, SW level is approximately chip input voltage.Pressure difference between BST and SW is the pressure difference at bootstrap capacitor both ends, can approximation recognize
To be a fixed value.In high side power pipe opening process, the grid signal DRVH level of high side power pipe is relative to SW level
Gradually raise.When the grid signal DRVH voltage of high side power pipe is raised to unlatching third PMOS tube MP3, A point i.e. the 3rd PMOS
Pipe MP3 drain terminal level is established, A point voltage value VAIt can be determined by following equation:
Wherein, KMP3It is the technological parameter of third PMOS tube MP3 and the product of breadth length ratio, Vth,MP3For third PMOS tube MP3
Threshold voltage.With the lifting of the grid signal DRVH level of high side power pipe, A level point is constantly lifted, when A level point is lifted
Rise to the electric current foundation that the first NMOS tube MN1 is flowed through when opening the first NMOS tube MN1.First current source I1 is fixed bias electricity
Stream, passes through the 6th PMOS tube MP6 mirror image to the second PMOS tube MP2.When the grid signal DRVH level of high side power pipe is raised to
The electric current for flowing through the first NMOS tube MN1 is more than B point when flowing through the electric current of the first PMOS tube MP1 to add the electric current I1 of the first current source
I.e. the first NMOS tube MN1 drain terminal level is gradually pulled low.When B level point is reduced to the 4th PMOS tube MP4 and the 5th PMOS tube MP5
When unlatching, the output signal DRVH ' level of sampling unit is lifted, therefore the lift of the grid signal DRVH level of high side power pipe
Rising finally is lifted the output signal DRVH ' level of sampling unit.Since the grid signal DRVH level of high side power pipe
Be raised to sampling unit output signal DRVH ' signal be raised to next stage circuit (detection high side power pipe when next stage circuit
For level displacement circuit, next stage circuit is by logical operation module when detecting lowside power pipe) level that is able to detect that passes through
The time gone through is denoted as t1.It is transistor that the raising and reduction of A level point, which can be regarded as third PMOS tube MP3 and first resistor R1,
Parasitic gate capacitor charge and discharge as a result, B level point raising and reduction can be regarded as the first NMOS tube MN1, the first PMOS
Pipe MP1 and the second PMOS tube MP2 is the charge and discharge of transistor gate parasitic capacitance as a result, the output signal DRVH ' of sampling unit
It is transistor that the raising and reduction of level, which can be regarded as the 4th PMOS tube MP4, the 5th PMOS tube MP5 and the second NMOS tube MN2,
The result of parasitic gate capacitor charge and discharge.According to capacitance characteristic expression formula:
It is found that for a certain size capacitor charge and discharge to the time needed for fixed voltage with charging and discharging currents size at anti-
Than.Therefore when DRVH level is lower relative to SW level, A point, B point, DRVH ' level change are slower, t1 longer.Can specifically it pass through
Simultaneous following equations obtain the relationship between DRVH level and t1:
Wherein, KMP3、KMN1、KMP4The technique ginseng of corresponding third PMOS tube MP3, the first NMOS tube MN1, the 4th PMOS tube MP4
Several products with breadth length ratio；A level point VA, B level point VB, DRVH ' level VDRVH’Respectively determine related knot under DRVH voltage
Voltage value when point stable state；CB、CDRVH’The parasitic capacitance value of respectively B point, DRVH ' point, Vth,MN1、Vth,MP4Respectively first
The threshold voltage of NMOS tube MN1, the 4th PMOS tube MP4, t1 ' indicate that DRVH high reached steady-state value to B node and taken by low turn over
Between, t1 " indicates to enter the time needed for stable state enters stable state to DRVH ' from the overturning of B point.If each node parasitic capacitance known is big
It is small, then the size of t1, value t1=t1 '+t1 can be calculated by above-mentioned expression formula ".
Since sampling unit is for detecting high side power pipe, because of the grid of the input terminal connection high side power pipe of sampling unit
Pole signal DRVH, the power rail of sampling unit are the high side floating power supply rail (SW-BST) of DC-DC converter, i.e., sampling is single at this time
The opposite high level of first power rail is the floating power supply BST of DC-DC converter, and the relatively low-level of sampling unit power rail is
Level at the switching node SW of DC-DC converter, the grid signal DRVH of high side power pipe is through over-sampling high side power pipe grid source
The output signal DRVH ' of sampling unit, the power rail of the output signal DRVH ' of sampling unit are converted to after the sampling unit of voltage
Also it is the high side floating power supply rail of DC-DC converter, is electricity at floating ground, that is, DC-DC converter switching node SW with reference to ground
It is flat.The power rail of logical operation module and time reference generation module is low side power rail, is earth signal for chip with reference to ground,
Therefore need a level shift level-down unit will be positioned at the sampling unit of high side power rail when detecting high side power pipe
Output signal DRVH ' is converted into the sampled signal of the high side power pipe positioned at low side power rail identified for logical operation module
DRVH_Down。
It is a kind of realization structural schematic diagram of level shift unit, including third NMOS tube MN3, the 4th as shown in Figure 4
NMOS tube MN4, the 7th PMOS tube MP7, second resistance R2, the first MPH1 of resistance to piezoelectric crystal, the second MPH2 of resistance to piezoelectric crystal, first
The grid of phase inverter INV1 and the second phase inverter INV2, the second MPH2 of resistance to piezoelectric crystal connect the grid of the first MPH1 of resistance to piezoelectric crystal
Level at pole and source electrode and the switching node SW of DC-DC converter, source electrode connect the output signal DRVH ' of sampling unit,
The drain electrode of its connection the 4th NMOS tube MN4 and the 7th PMOS tube MP7 that drains and the input terminal of the first phase inverter INV1；Third
The drain electrode of the first MPH1 of resistance to piezoelectric crystal of grid and drain electrode connection of NMOS tube MN3 and the grid of the 4th NMOS tube MN4 simultaneously pass through
The grid of the 7th PMOS tube MP7 of connection and source electrode and low-tension supply VCC, source electrode connect the 4th NMOS tube after second resistance R2
The source electrode of MN4 simultaneously connects ground level；The input terminal of second phase inverter INV2 connects the output end of the first phase inverter INV1, output
The sampled signal DRVH_Down of end output high side power pipe.
When the output signal DRVH ' level of sampling unit, which is raised to the second MPH2 of resistance to piezoelectric crystal, to be opened, one electric current
C node i.e. the second MPH2 of resistance to piezoelectric crystal drain terminal, which will be injected, is lifted C level point.Because of the clamper of the 7th PMOS tube MP7
Effect, C point voltage are at most lifted to VCC+VBE, and wherein VBE is the conduction voltage drop of the 7th PMOS tube MP7 parasitic body diode D1.
Second resistance R2 and third NMOS tube MN3 has determined that one lesser bias current I2, this strand of bias current are mirrored to the 4th
NMOS tube MN4, for maintaining C point when the output signal DRVH ' of sampling unit is not turned on the second MPH2 of resistance to piezoelectric crystal
Low level.Cause in SW level point uphill process in the unlatching of high side power pipe, one electric current I3 can pass through the first resistance to piezoelectric crystal
The parasitic capacitance C of MPH1 grid and drain electrodeGDCoupling is got off, and I2 and I3 collective effect prevent in high side power pipe opening process at this time
C level point caused by sensitive node disturbs accidentally is overturn, and effectively avoids false triggering bring detection mistake.Through the first phase inverter
The sampled signal DRVH_Down of final output high side power pipe after INV1 and the second phase inverter INV2 shaping, obtained sampling letter
The reference ground level of number DRVH_Down is chip.The defeated of sampling unit is detected from level shift level-down unit
Signal DRVH ' is lifted to output effective sampled signal DRVH_Down time experienced and is denoted as t2 out, which is considered as
The time required to charging to VCC+VBE for C node parasitic capacitance.
When detecting high side power pipe, the delay that sampling unit generates is t1, and the delay that level shift unit generates is t2, is adopted
The delay time T1=t1+t2 of the grid signal of sample signal and power tube.
Clock reference is introduced under-voltage detection by the present invention, using time reference generation module generate a burst pulse as when
Between reference signal T, give a kind of realization circuit of time reference generation module as shown in Figure 5, including third phase inverter INV3,
4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the 7th phase inverter INV7, the 8th phase inverter INV8,
Three resistance R3, first capacitor C1, the second capacitor C2, the 5th NMOS tube MN5, the 8th PMOS tube MP8 and the first NAND gate NAND1,
The control signal TG_ctr1 of the input terminal connection high side power pipe of third phase inverter INV3, output end connect the 5th NMOS tube
The grid of MN5 and the 8th PMOS tube MP8；The source electrode of 8th PMOS tube MP8 connects low-tension supply VCC, and drain electrode passes through third electricity
The drain electrode of the 5th NMOS tube MN5 and the input terminal of the 4th phase inverter INV4 are connected after resistance R3 and by connecting the after first capacitor C1
The source electrode and ground level of five NMOS tube MN5；The input terminal of 5th phase inverter INV5 connects the output end of the 4th phase inverter INV4,
Output end connects the input terminal of hex inverter INV6 and the first input end of the first NAND gate NAND1；7th phase inverter INV7
Input terminal connection hex inverter INV6 output end and by connecting ground level after the second capacitor C2, output end passes through the
The second input terminal of the first NAND gate NAND1 is connected after eight phase inverter INV8；The output end of first NAND gate NAND1 exports the time
Reference signal T.
When detecting high side power pipe, time reference generation module is produced using the control signal TG_ctr1 of high side power pipe
Raw burst pulse, TG_ctr1 signal are the control signal for controlling high side power pipe and opening and shutting off, and are a periodic square wave, high side
The same phase of grid signal DRVH of control the signal TG_ctr1 and high side power pipe of power tube, the grid signal of high side power pipe
DRVH turns over high to control being switched on and off for high side power pipe with the turning over high of control signal TG_ctr1 of high side power pipe,
When the square-wave signal is in the high level stage, high side power pipe is opened.Delay caused by 3rd resistor R3 and first capacitor C1
It is denoted as t3, t3 is the delay T2 of the control signal TG_ctr1 of time reference signal T and high side power pipe.Second capacitor C2 institute
Bring delay determines the narrow pulse width of time reference signal T, and the 4th phase inverter INV4, the 5th phase inverter INV5, the 7th are instead
For the waveform after shaping experience delay, the first NAND gate NAND1 is one narrow for generating by phase device INV7, the 8th phase inverter INV8
Pulse signal, the burst pulse are the time reference signal T generated in the present embodiment.
Logical operation module is for patrolling the sampled signal DRVH_Down of high side power pipe and time reference signal T
It collects operation and generates under-voltage signal TG_ctr2, under-voltage signal TG_ctr2 is high side power pipe gate source voltage testing result, under-voltage
Signal TG_ctr2 can be returned to for controlling opening and shutting off for high side power pipe.As shown in figure 5, being utilized in the present embodiment
First nor gate NOR1 carries out logical operation, when the sampled signal DRVH_Down and time reference signal T of high side power pipe are
The under-voltage signal TG_ctr2 of high level is generated when low level.The present embodiment is by taking or logic as an example, but remaining structure and logic
Logical operation module can be equally used for comparing sampled signal and time reference logical signal T to generate corresponding under-voltage letter
Number.
It is illustrated in figure 6 the timing diagram that high side power pipe is detected in the present embodiment, be delayed pole as brought by phase inverter
It is short to be ignored herein.Dash area is waveform when triggering high side power pipe is under-voltage, the grid of high side power pipe in figure
Signal DRVH manages the turning over high of signal TG_ctr1 processed with high side power and turns over height, undergoes the sampling of high side power pipe gate source voltage
The delay of t1 brought by unit, the output signal DRVH ' of sampling unit turns over height, then undergoes level shift level-down unit institute
Bring t2 delay, sampled signal DRVH_Down turn over height.When do not occur high side power pipe gate source voltage it is under-voltage when, t1+t2 is little
In t3, under-voltage signal TG_ctr2 is low level, and high side power pipe can be normally-open；When high side power pipe gate source voltage is under-voltage
When, t1+t2 is greater than t3, and under-voltage signal TG_ctr2 can be low electricity in sampled signal DRVH_Down and time reference signal T simultaneously
Usually become high level, the under-voltage signal TG_ctr2 of the high level can be used to shield high side power pipe open signal, make high side function
Rate pipe close, until it is under-voltage end be again turned on high side power pipe, avoid high side power pipe gate source voltage it is too low caused by
Conduction loss is excessive.
Similarly, when undervoltage detection circuit proposed by the present invention being used for lowside power pipe, undervoltage detection circuit includes voltage
Sampling module, time reference generation module and logical operation module, wherein voltage sample module is for sampling lowside power pipe
Grid signal does not need setting level due to the low side power rail that the power rail of sampling unit at this time is DC-DC converter
Displacement unit, directly using the output signal of sampling unit as sampled signal, T1 only has the delay t1 of sampling unit generation；
The control signal of lowside power pipe is generated burst pulse as time reference signal by time reference generation module after the T2 that is delayed,
T2 is the delay t3 of the control signal of time reference signal and lowside power pipe, in the present embodiment equally can by 3rd resistor R3 and
First capacitor C1 is determined；T1 is compared with t3 by logical operation module again, lowside power pipe can be just when t1 is not more than t3
Normally open, t1 generates the open signal of under-voltage signal shielding lowside power pipe when being greater than t3, closes lowside power pipe.This implementation
Though being equally applicable to the DC-DC converter of other modes by taking Buck converter as an example in example.
Above example is only used to illustrate the technical scheme of the present invention, those skilled in the art should understand that, it can be with
Modification and variation combination is made to the present invention, but in the range for the spirit for not departing from this programme, should all be covered of the invention
Within rights protection scope.
Claims (7)
1. a kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter, which is characterized in that the under-voltage inspection
Slowdown monitoring circuit includes voltage sample module, time reference generation module and logical operation module,
The voltage sample module be used for sample the power tube grid signal and export sampled signal, the sampled signal with
The delay time of the grid signal of the power tube is T1；
The time reference generation module is used to after the control signal of the power tube is carried out the delay that delay time is T2 produce
Raw narrow pulse signal, the narrow pulse signal is as time reference signal, the control signal and the power tube of the power tube
The same phase of grid signal；
The logical operation module is used for the sampled signal and time reference signal, generates under-voltage letter when T1 is greater than T2
Number.
2. the power tube gate source voltage undervoltage detection circuit according to claim 1 suitable for DC-DC converter, feature
It is, the voltage sample module includes sampling unit, and the sampling unit includes the first PMOS tube, the second PMOS tube, third
PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the first NMOS tube, the second NMOS tube, first resistor and first
Current source,
The grid of first PMOS tube connects the source electrode of third PMOS tube and the input terminal as the voltage sample module, source electrode
Connect the second PMOS tube, the 4th PMOS tube and the 6th PMOS tube source electrode and connect the relatively high electricity of the sampling unit power rail
It is flat, the drain electrode of drain electrode the first NMOS tube of connection and the second PMOS tube and the grid of the second NMOS tube and the 4th PMOS tube；
The grid of the grid connection third PMOS tube of first NMOS tube is with drain electrode and by connecting the first NMOS tube after first resistor
It is relatively low-level with the source electrode of the second NMOS tube and the sampling unit power rail；
The grid of 5th PMOS tube connects the grid of the second PMOS tube and the grid of the 6th PMOS tube and drains and pass through first
The relatively low-level of the sampling unit power rail is connected after current source, source electrode connects the drain electrode of the 4th PMOS tube, drain electrode
It connects the drain electrode of the second NMOS tube and exports the output signal of the sampling unit, the output signal of the sampling unit is with described
The grid signal of power tube changes.
3. the power tube gate source voltage undervoltage detection circuit according to claim 2 suitable for DC-DC converter, feature
It is, when the power tube is lowside power pipe, the power rail of the sampling unit is the low side power of the DC-DC converter
Rail, the opposite high level of the power rail of the sampling unit are low-tension supply, the relatively low electricity of the power rail of the sampling unit
Put down as ground level, the input terminal of the sampling unit connects the grid signal of the lowside power pipe, the sampling unit it is defeated
Signal is the sampled signal out.
4. the power tube gate source voltage undervoltage detection circuit according to claim 2 suitable for DC-DC converter, feature
It is, when the power tube is high side power pipe, the power rail of the sampling unit is the high side power supply of the DC-DC converter
Rail, the opposite high level of the power rail of the sampling unit are the floating power supply of the DC-DC converter, the sampling unit
Level at the relatively low-level switching node for the DC-DC converter of power rail, the input terminal connection of the sampling unit
The grid signal of the high side power pipe；
The voltage sample module further includes level shift unit, and the level shift unit is used for the defeated of the sampling unit
Signal is used as institute after the low side power rail that the high side power rail of the DC-DC converter is converted to the DC-DC converter out
State sampled signal.
5. the power tube gate source voltage undervoltage detection circuit according to claim 4 suitable for DC-DC converter, feature
It is, the level shift unit includes third NMOS tube, the 4th NMOS tube, the 7th PMOS tube, second resistance, the first resistance to piezocrystal
Body pipe, the second resistance to piezoelectric crystal, the first phase inverter and the second phase inverter,
The grid and source electrode of grid the first resistance to piezoelectric crystal of connection of second resistance to piezoelectric crystal and opening for the DC-DC converter
Level at artis, source electrode connect the output signal of the sampling unit, drain electrode the 4th NMOS tube of connection and the 7th PMOS
The input terminal of the drain electrode of pipe and the first phase inverter；
The drain electrode of the grid of third NMOS tube and drain electrode the first resistance to piezoelectric crystal of connection and the grid of the 4th NMOS tube simultaneously pass through the
The grid and source electrode and low-tension supply, source electrode of the 7th PMOS tube of connection connect the source electrode of the 4th NMOS tube and company after two resistance
Earth level；
The input terminal of second phase inverter connects the output end of the first phase inverter, and output end exports the sampled signal.
6. detection that the power tube gate source voltage according to any one of claims 1 to 5 suitable for DC-DC converter is under-voltage is electric
Road, which is characterized in that the time reference generation module includes third phase inverter, the 4th phase inverter, the 5th phase inverter, the 6th anti-
Phase device, the 7th phase inverter, the 8th phase inverter, 3rd resistor, first capacitor, the second capacitor, the 5th NMOS tube, the 8th PMOS tube and
First NAND gate,
The input terminal of third phase inverter connects the control signal of the power tube, and output end connects the 5th NMOS tube and the 8th
The grid of PMOS tube；
The source electrode of 8th PMOS tube connects low-tension supply, and drain electrode is by connecting the drain electrode and the of the 5th NMOS tube after 3rd resistor
The input terminal of four phase inverters and source electrode and ground level by connecting the 5th NMOS tube after first capacitor；
The input terminal of 5th phase inverter connects the output end of the 4th phase inverter, output end connect hex inverter input terminal and
The first input end of first NAND gate；
The input terminal of 7th phase inverter connects the output end of hex inverter and by connecting ground level after the second capacitor, exports
Hold the second input terminal by connecting the first NAND gate after the 8th phase inverter；
The output end of first NAND gate exports the time reference signal.
7. the power tube gate source voltage undervoltage detection circuit according to claim 6 suitable for DC-DC converter, feature
It is, the logical operation module includes the first nor gate, and two input terminals of the first nor gate are separately connected the time base
Calibration signal and sampled signal, output end export the under-voltage signal.
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| CN201910504709.8A CN110208673B (en) | 2019-06-12 | 2019-06-12 | Power tube grid source voltage under-voltage detection circuit suitable for DC-DC converter |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111313366A (en) * | 2020-03-31 | 2020-06-19 | 西安微电子技术研究所 | Undervoltage self-turn-off output stage circuit |
| CN111398764A (en) * | 2020-03-31 | 2020-07-10 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Power tube voltage testing method, device and circuit |
| CN112630513A (en) * | 2020-12-09 | 2021-04-09 | 北方工业大学 | Boost capacitor voltage detection circuit |
| CN113206494A (en) * | 2021-03-19 | 2021-08-03 | 成都市菱奇半导体有限公司 | Input voltage's detection circuitry and charger |
| CN113655844A (en) * | 2021-10-20 | 2021-11-16 | 浙江地芯引力科技有限公司 | Overcurrent protection circuit and method and electronic equipment |
| CN113922340A (en) * | 2021-10-19 | 2022-01-11 | 中国电子科技集团公司第五十八研究所 | Short-circuit protection circuit for high-side power tube in driving chip |
| CN116027097A (en) * | 2022-12-16 | 2023-04-28 | 无锡中微爱芯电子有限公司 | Overcurrent detection circuit for gate drive |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040190211A1 (en) * | 2003-02-26 | 2004-09-30 | Ockert William R. | Load control receiver with line under voltage and line under frequency detection and load shedding |
| CN104201877A (en) * | 2014-09-10 | 2014-12-10 | 广州金升阳科技有限公司 | Delay method and delay circuit for input under-voltage protection circuit |
| CN204044330U (en) * | 2014-07-18 | 2014-12-24 | 郑州众智科技股份有限公司 | Storage battery under-voltage delayed alarm circuit |
| CN205104890U (en) * | 2015-09-06 | 2016-03-23 | 浙江正泰电器股份有限公司 | Undervoltage protection circuit excessively of circuit breaker |
| US20180003758A1 (en) * | 2016-06-30 | 2018-01-04 | Palacky University Olomouc | Method for measuring quick changes in low surface conductivity of dielectrics under electromagnetic interference of line voltage and equipment to perform this type of measurement |
| CN109039029A (en) * | 2018-08-15 | 2018-12-18 | 电子科技大学 | A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit |
| CN109739710A (en) * | 2019-01-04 | 2019-05-10 | 华大半导体有限公司 | A kind of method that undervoltage detection circuit is under-voltage with detection |
| CN109756211A (en) * | 2019-02-21 | 2019-05-14 | 电子科技大学 | A kind of burst pulse delay circuit |
| CN109861379A (en) * | 2019-02-27 | 2019-06-07 | 深圳市汇川技术股份有限公司 | Under-voltage detection method, circuit, equipment and computer readable storage medium |
-
2019
- 2019-06-12 CN CN201910504709.8A patent/CN110208673B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040190211A1 (en) * | 2003-02-26 | 2004-09-30 | Ockert William R. | Load control receiver with line under voltage and line under frequency detection and load shedding |
| CN204044330U (en) * | 2014-07-18 | 2014-12-24 | 郑州众智科技股份有限公司 | Storage battery under-voltage delayed alarm circuit |
| CN104201877A (en) * | 2014-09-10 | 2014-12-10 | 广州金升阳科技有限公司 | Delay method and delay circuit for input under-voltage protection circuit |
| CN205104890U (en) * | 2015-09-06 | 2016-03-23 | 浙江正泰电器股份有限公司 | Undervoltage protection circuit excessively of circuit breaker |
| US20180003758A1 (en) * | 2016-06-30 | 2018-01-04 | Palacky University Olomouc | Method for measuring quick changes in low surface conductivity of dielectrics under electromagnetic interference of line voltage and equipment to perform this type of measurement |
| CN109039029A (en) * | 2018-08-15 | 2018-12-18 | 电子科技大学 | A kind of bootstrap charge circuit circuit suitable for GaN power device gate drive circuit |
| CN109739710A (en) * | 2019-01-04 | 2019-05-10 | 华大半导体有限公司 | A kind of method that undervoltage detection circuit is under-voltage with detection |
| CN109756211A (en) * | 2019-02-21 | 2019-05-14 | 电子科技大学 | A kind of burst pulse delay circuit |
| CN109861379A (en) * | 2019-02-27 | 2019-06-07 | 深圳市汇川技术股份有限公司 | Under-voltage detection method, circuit, equipment and computer readable storage medium |
Non-Patent Citations (2)
| Title |
|---|
| 徐一 等: "一种应用开关电容分压的电源电压检测电路", 《电子器件》 * |
| 谭林 等: "一种高速低功耗的欠压锁定电路", 《微电子学》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111313366A (en) * | 2020-03-31 | 2020-06-19 | 西安微电子技术研究所 | Undervoltage self-turn-off output stage circuit |
| CN111398764A (en) * | 2020-03-31 | 2020-07-10 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Power tube voltage testing method, device and circuit |
| CN111398764B (en) * | 2020-03-31 | 2022-06-14 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Power tube voltage testing method, device and circuit |
| CN112630513A (en) * | 2020-12-09 | 2021-04-09 | 北方工业大学 | Boost capacitor voltage detection circuit |
| CN112630513B (en) * | 2020-12-09 | 2023-10-27 | 北方工业大学 | Boost capacitor voltage detection circuit |
| CN113206494A (en) * | 2021-03-19 | 2021-08-03 | 成都市菱奇半导体有限公司 | Input voltage's detection circuitry and charger |
| CN113922340A (en) * | 2021-10-19 | 2022-01-11 | 中国电子科技集团公司第五十八研究所 | Short-circuit protection circuit for high-side power tube in driving chip |
| CN113922340B (en) * | 2021-10-19 | 2024-01-23 | 中国电子科技集团公司第五十八研究所 | Short-circuit protection circuit for driving high-side power tube in chip |
| CN113655844A (en) * | 2021-10-20 | 2021-11-16 | 浙江地芯引力科技有限公司 | Overcurrent protection circuit and method and electronic equipment |
| CN116027097A (en) * | 2022-12-16 | 2023-04-28 | 无锡中微爱芯电子有限公司 | Overcurrent detection circuit for gate drive |
| CN116027097B (en) * | 2022-12-16 | 2024-04-05 | 无锡中微爱芯电子有限公司 | Overcurrent detection circuit for gate drive |
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