CN112630513B - Boost capacitor voltage detection circuit - Google Patents
Boost capacitor voltage detection circuit Download PDFInfo
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- CN112630513B CN112630513B CN202011432770.5A CN202011432770A CN112630513B CN 112630513 B CN112630513 B CN 112630513B CN 202011432770 A CN202011432770 A CN 202011432770A CN 112630513 B CN112630513 B CN 112630513B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 78
- 238000001514 detection method Methods 0.000 title claims abstract description 19
- 238000010586 diagram Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
- G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
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- General Physics & Mathematics (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
The application provides a Boost capacitor voltage detection circuit, which comprises a Boost capacitor voltage judgment circuit and an inverter amplifying circuit; the Boost capacitor voltage judging circuit comprises a MOS tube M1 and a MOS tube M0, wherein the MOS tube M1 is used as an input end for judging the Boost capacitor voltage; the MOS tube M0 is used for providing bias current for the Boost capacitor voltage judging circuit; if the Boost capacitor voltage is smaller than the threshold voltage of the MOS transistor M1, the input voltage of the inverter amplifying circuit is reduced, and the inverter amplifying circuit outputs the Boost capacitor voltage state as an under-voltage state. The Boost capacitor voltage is judged through the threshold voltage of the MOS tube M1, the source electrode and the grid electrode of the MOS tube M1 are respectively connected to two ends of the Boost capacitor, if the Boost capacitor voltage is reduced to the threshold voltage of the MOS tube M1, the input voltage of the inverter amplifying circuit is reduced, and the inverter amplifying circuit is used as a rough comparator in the embodiment of the application, so that the Boost capacitor voltage state is output as an under-voltage state.
Description
Technical Field
The application belongs to the field of integrated circuit design, and particularly relates to a Boost capacitor voltage detection circuit.
Background
With the development of integrated circuits, the integration level of DC-DC, which is a device for converting electric energy of one voltage value into electric energy of another voltage value in a direct current circuit, is increasing, and many switching power supply chips have integrated MOS transistors (Metal Oxide Semiconductor, metal oxide semiconductor field effect transistors) inside the chips. Because the on-resistance of the NMOS tube with the same area is smaller than that of the PMOS tube, the NMOS tube is used for replacing the PMOS tube in the integration of a plurality of chips, thereby achieving the purposes of reducing the area of the chips and improving the efficiency.
Because of the characteristics of the NMOS transistor itself, a higher gate voltage is required to drive the NMOS transistor in order to make the drain voltage and the source voltage of the NMOS transistor coincide, so that a boost circuit (i.e., a bootstrap circuit) is widely used.
However, due to leakage of the capacitor in the Boost circuit, when the capacitor voltage is too small, the driven NMOS transistor cannot be normally turned on, so that a circuit is required to determine the voltage across the capacitor in the Boost circuit, i.e., a Boost capacitor voltage detection circuit for determining the voltage across the capacitor in the Boost circuit is required.
Disclosure of Invention
In order to solve the technical problems in the prior art, the application provides a Boost capacitor voltage detection circuit.
The application provides a Boost capacitor voltage detection circuit, which comprises a Boost capacitor voltage judgment circuit and an inverter amplifying circuit;
the Boost capacitor voltage judging circuit comprises an MOS tube M1 and an MOS tube M0, wherein the MOS tube M1 is used as an input end for judging the Boost capacitor voltage; the sum MOS tube M0 is used for providing bias current for the Boost capacitor voltage judging circuit;
if the Boost capacitor voltage is smaller than the threshold voltage of the MOS transistor M1, the input voltage of the inverter amplifying circuit is reduced, and the inverter amplifying circuit outputs the Boost capacitor voltage state as an under-voltage state.
Further, the inverter amplifying circuit comprises a MOS tube M2 and a MOS tube M3; the MOS tube M2 is a PMOS tube, and the MOS tube M3 is an NMOS tube; or, the MOS tube M2 is an NMOS tube, and the MOS tube M3 is a PMOS tube.
Further, the width-to-length ratio of the MOS tube M2 and the MOS tube M3 is adjusted, and the overturning voltage of the inverter is controlled, so that the output voltage of the Boost capacitor voltage judging circuit is changed into a high level or a low level;
and outputting the undervoltage state or the high voltage state of the Boost capacitor according to the output high level or low level.
Further, the source electrode of the MOS tube M2 is connected with the source electrode of the MOS tube M0, the grid electrode of the MOS tube M2 is connected with the grid electrode of the MOS tube M3, and the drain electrode of the MOS tube M2 is connected with the drain electrode of the MOS tube M3;
the source electrode of the MOS tube M3 is connected with the power supply voltage Vdd, and the drain electrode of the MOS tube M3 is an output end.
Further, the source electrode and the grid electrode of the MOS tube M1 are respectively connected to two ends of the Boost capacitor, and the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M0;
and the grid electrode of the MOS tube M0 is connected with the paranoid voltage.
Further, the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M0, the drain electrode of the MOS tube M2 and the drain electrode of the MOS tube M3 at the same time.
Further, the source of the MOS transistor M0 is connected to the ground gnd.
Further, the MOS tube M1 is a PMOS tube.
According to the Boost capacitor voltage detection circuit provided by the application, the source electrode of the MOS tube M1 is connected with one end of a Boost capacitor, the grid electrode of the MOS tube M1 is connected with the other end of the Boost capacitor, the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M0, the grid electrode of the MOS tube M0 is connected with bias voltage, the MOS tube M1 is used as the Boost capacitor voltage to be input into the MOS tube, and the MOS tube M0 is used as a bias circuit; the inverter circuit is used as a rough comparator to change the output voltage of the boost capacitor voltage judging circuit into a high-low level so as to output the undervoltage state or the high-voltage state of the boost capacitor.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a Boost capacitor voltage detection circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of an output signal according to a Boost capacitor voltage according to an embodiment of the present application.
Detailed Description
In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
Fig. 1 is a circuit diagram of a Boost capacitor voltage detection circuit according to an embodiment of the present application. As shown in FIG. 1, the Boost capacitor voltage detection circuit provided by the application comprises a Boost capacitor voltage judgment circuit and an inverter amplifying circuit; the Boost capacitor voltage judging circuit comprises an MOS tube M1 and an MOS tube M0, wherein the MOS tube M1 is used as an input end for judging the Boost capacitor voltage; the MOS tube M0 is used for providing bias current for the Boost capacitor voltage judging circuit; if the Boost capacitor voltage is smaller than the threshold voltage of the MOS transistor M1, the input voltage of the inverter amplifying circuit is reduced, and the inverter amplifying circuit outputs the Boost capacitor voltage state as an under-voltage state.
According to the Boost capacitance detection circuit provided by the embodiment of the application, the Boost capacitance voltage is judged through the threshold voltage of the MOS tube M1, the source electrode and the grid electrode of the MOS tube M1 are respectively connected to the two ends of the Boost capacitance (BC 1 and BC2 in FIG. 1 are respectively the two ends of the Boost capacitance), if the Boost capacitance voltage is reduced to the threshold voltage of the MOS tube M1, the input voltage of the inverter amplifying circuit is reduced, and the inverter amplifying circuit is used as a rough comparator in the embodiment of the application, so that the Boost capacitance voltage state is output as an under-voltage state. Wherein, MOS pipe M1 is the PMOS pipe.
The inverter amplifying circuit comprises an MOS tube M2 and an MOS tube M3, one of the MOS tube M2 and the MOS tube M3 is a PMOS tube, the other is an NMOS tube, and the MOS tube M2 and the MOS tube M3 are connected into an inverter. Controlling the overturning voltage of the inverter by adjusting the width-to-length ratio of the MOS tube M2 and the MOS tube M3 so that the output voltage of the Boost capacitor voltage judging circuit is changed into a high level or a low level; and outputting the undervoltage state or the high voltage state of the Boost capacitor according to the output high level or low level.
A source electrode of the MOS tube M2 in the inverter amplifying circuit is connected with a source electrode of the MOS tube M0, a grid electrode of the MOS tube M2 is connected with a grid electrode of the MOS tube M3, and a drain electrode of the MOS tube M2 is connected with a drain electrode of the MOS tube M3; the source electrode of the MOS tube M3 is connected with the power supply voltage Vdd, and the drain electrode of the MOS tube M3 is an output end.
In the inverter amplifying circuit, the grid electrodes of the MOS tube M2 and the MOS tube M3 are connected with the grid electrode, the drain electrode is connected with the drain electrode to form an inverter circuit, and if the MOS tube M2 and the MOS tube M3 input low level, the MOS tube M2 and the MOS tube M3 output high level; conversely, if MOS transistor M2 and MOS transistor M3 input a high level, MOS transistor M2 and MOS transistor M3 output a low level.
According to the embodiment of the application, the width-to-length ratio of the MOS tube M2 and the MOS tube M3 can be adjusted, the overturning voltage of the inverter can be adjusted, and the inverter amplifying circuit is used for being equivalent to a rough comparator, so that the Boost capacitor is output in an under-voltage state or an under-voltage state.
In a specific embodiment, the Boost capacitor voltage detection circuit in the embodiment of the application comprises a Boost capacitor voltage judgment circuit and an inverter amplification circuit. The Boost capacitor voltage judging circuit comprises an MOS tube M1 and an MOS tube M0, wherein a source electrode of the MOS tube M1 is connected with a BC2 end of the Boost capacitor, a grid electrode of the MOS tube M1 is connected with a BC1 end of the Boost capacitor, a drain electrode of the MOS tube M1 is connected with a drain electrode of the MOS tube M0, a grid electrode of the MOS tube M0 is connected with a bias voltage, and a source electrode of the MOS tube M0 is connected with a ground wire gnd. The inverter amplifying circuit comprises an MOS tube M2 and an MOS tube M3, wherein a source electrode of the MOS tube M2 is connected with a source electrode of the MOS tube M0, a grid electrode of the MOS tube M2 is connected with a grid electrode of the MOS tube M3, a drain electrode of the MOS tube M2 is connected with a drain electrode of the MOS tube M3, and a source electrode of the MOS tube M3 is connected with a power supply voltage Vdd. The drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M0, the drain electrode of the MOS tube M2 and the drain electrode of the MOS tube M3 at the same time, and the drain electrode of the MOS tube M3 is an output end.
As shown in fig. 2, when the Boost capacitor voltage changes, the output voltage changes according to the change of the input Boost capacitor voltage, and when the Boost capacitor voltage is too low, the output voltage turns over, so as to control other circuits to protect the chip.
In the embodiment of the application, the MOS tube M0 is used for providing bias current for the Boost capacitor voltage judging circuit, the source electrode and the grid electrode of the MOS tube M1 are respectively connected with two ends of the Boost capacitor, and the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M0; the grid electrode of the MOS tube M0 is connected with a paranoid voltage; the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M0, the drain electrode of the MOS tube M2 and the drain electrode of the MOS tube M3 at the same time.
Wherein, the paranoid current calculation formula is as follows formula (1), wherein, V GS For Boost capacitor voltage, V TH Is the threshold voltage of the MOS transistor M1.
When in the formula (1)When the voltage of the Boost capacitor is lower than the preset voltage, the Boost capacitor voltage judging circuit outputs a low level; when->And when the voltage of the Boost capacitor is higher than the preset voltage, the Boost capacitor voltage judging circuit outputs a high level.
It can be seen that, in summary, in the Boost capacitance detection circuit provided by the embodiment of the application, the source electrode of the MOS transistor M1 is connected to one end of the Boost capacitance, the gate electrode of the MOS transistor M1 is connected to the other end of the Boost capacitance, the drain electrode of the MOS transistor M1 is connected to the drain electrode of the MOS transistor M0, the gate electrode of the MOS transistor M0 is connected to the bias voltage, the MOS transistor M1 is used as the Boost capacitance voltage input MOS transistor, and the MOS transistor M0 is used as the bias circuit; the inverter circuit is used as a rough comparator to change the output voltage of the boost capacitor voltage judging circuit into a high-low level so as to output the undervoltage state or the high-voltage state of the boost capacitor.
Since the foregoing embodiments are all described in other modes by reference to the above, the same parts are provided between different embodiments, and the same and similar parts are provided between the embodiments in the present specification. And will not be described in detail herein.
It should be noted that in this specification, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a circuit structure, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such circuit structure, article, or apparatus. Without further limitation, the statement "comprises" or "comprising" a … … "does not exclude that an additional identical element is present in a circuit structure, article or apparatus that comprises the element.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure of the application herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims. The embodiments of the present application described above do not limit the scope of the present application.
Claims (5)
1. The Boost capacitor voltage detection circuit is characterized by comprising a Boost capacitor voltage judgment circuit and an inverter amplifying circuit;
the Boost capacitor voltage judging circuit comprises a MOS tube M1 and a MOS tube M0, wherein a source electrode and a grid electrode of the MOS tube M1 are respectively connected to two ends of the Boost capacitor, a drain electrode of the MOS tube M1 is connected with a drain electrode of the MOS tube M0, a grid electrode of the MOS tube M0 is connected with a bias voltage, the MOS tube M0 is used for providing bias current for the Boost capacitor voltage judging circuit, and the MOS tube M1 is used for judging Boost capacitor voltage;
the inverter amplifying circuit comprises a MOS tube M2 and a MOS tube M3; the MOS tube M2 is a PMOS tube, and the MOS tube M3 is an NMOS tube; or, the MOS tube M2 is an NMOS tube, and the MOS tube M3 is a PMOS tube; the source electrode of the MOS tube M2 is connected with the source electrode of the MOS tube M0, the grid electrode of the MOS tube M2 is connected with the grid electrode of the MOS tube M3, and the drain electrode of the MOS tube M2 is connected with the drain electrode of the MOS tube M3;
the inversion voltage of the inverter amplifying circuit is controlled by adjusting the width-to-length ratio of the MOS tube M2 and the MOS tube M3, so that the output voltage of the Boost capacitor voltage judging circuit is changed into a high level or a low level;
and outputting the Boost capacitor voltage state to be an under-voltage state or a high-voltage state according to the output high level or low level.
2. The Boost capacitor voltage detection circuit according to claim 1, wherein a source of the MOS transistor M3 is connected to a power supply voltage Vdd, and a drain of the MOS transistor M3 is an output terminal.
3. The Boost capacitor voltage detection circuit of claim 1, wherein the drain of the MOS transistor M1 is connected to the drain of the MOS transistor M0, the gate of the MOS transistor M2, and the gate of the MOS transistor M3 at the same time.
4. The Boost capacitor voltage detection circuit of claim 3, wherein a source of the MOS transistor M0 is connected to ground gnd.
5. The Boost capacitor voltage detection circuit of claim 1, wherein the MOS transistor M1 is a PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011432770.5A CN112630513B (en) | 2020-12-09 | 2020-12-09 | Boost capacitor voltage detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011432770.5A CN112630513B (en) | 2020-12-09 | 2020-12-09 | Boost capacitor voltage detection circuit |
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| Publication Number | Publication Date |
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| CN112630513A CN112630513A (en) | 2021-04-09 |
| CN112630513B true CN112630513B (en) | 2023-10-27 |
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| CN202011432770.5A Active CN112630513B (en) | 2020-12-09 | 2020-12-09 | Boost capacitor voltage detection circuit |
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| CN103915990A (en) * | 2014-04-18 | 2014-07-09 | 电子科技大学 | Drive circuit for GaN power devices |
| WO2018103574A1 (en) * | 2016-12-08 | 2018-06-14 | 深圳创维数字技术有限公司 | Over and under voltage protection circuit and set-top box |
| CN109975600A (en) * | 2019-04-29 | 2019-07-05 | 南京芯耐特半导体有限公司 | A kind of undervoltage detection circuit of zero quiescent dissipation |
| CN110148883A (en) * | 2019-04-22 | 2019-08-20 | 淮阴工学院 | Semiconductor laser circuit and calculation method with charge compensation and dynamic bias |
| CN110208673A (en) * | 2019-06-12 | 2019-09-06 | 电子科技大学 | A kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter |
| CN111711172A (en) * | 2020-06-22 | 2020-09-25 | 电子科技大学 | Undervoltage protection circuit with ultralow power consumption |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012165328A1 (en) * | 2011-05-27 | 2012-12-06 | ローム株式会社 | Load driving device and electronic device using same |
| CN102769275B (en) * | 2012-07-13 | 2015-01-21 | 深圳市富满电子有限公司 | Over-discharge protection circuit for rechargeable battery |
| CN102904220B (en) * | 2012-11-07 | 2015-05-06 | 东南大学 | Under-voltage protection method of high-voltage half-bridge driving chip and high-voltage half-bridge circuit |
| CN203838590U (en) * | 2014-04-08 | 2014-09-17 | 浙江商业职业技术学院 | Under-voltage detection device |
| CN109951178B (en) * | 2019-04-03 | 2020-07-31 | 电子科技大学 | System protection method of GaN gate drive circuit |
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2020
- 2020-12-09 CN CN202011432770.5A patent/CN112630513B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103915990A (en) * | 2014-04-18 | 2014-07-09 | 电子科技大学 | Drive circuit for GaN power devices |
| WO2018103574A1 (en) * | 2016-12-08 | 2018-06-14 | 深圳创维数字技术有限公司 | Over and under voltage protection circuit and set-top box |
| CN110148883A (en) * | 2019-04-22 | 2019-08-20 | 淮阴工学院 | Semiconductor laser circuit and calculation method with charge compensation and dynamic bias |
| CN109975600A (en) * | 2019-04-29 | 2019-07-05 | 南京芯耐特半导体有限公司 | A kind of undervoltage detection circuit of zero quiescent dissipation |
| CN110208673A (en) * | 2019-06-12 | 2019-09-06 | 电子科技大学 | A kind of power tube gate source voltage undervoltage detection circuit suitable for DC-DC converter |
| CN111711172A (en) * | 2020-06-22 | 2020-09-25 | 电子科技大学 | Undervoltage protection circuit with ultralow power consumption |
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