CN115459578A - Output clamping protection module, method, chip and drive protection system - Google Patents

Output clamping protection module, method, chip and drive protection system Download PDF

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Publication number
CN115459578A
CN115459578A CN202211138899.4A CN202211138899A CN115459578A CN 115459578 A CN115459578 A CN 115459578A CN 202211138899 A CN202211138899 A CN 202211138899A CN 115459578 A CN115459578 A CN 115459578A
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tube
nmos tube
nmos
voltage
output
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CN202211138899.4A
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CN115459578B (en
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王青松
李妍
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Yaoxin Microelectronics Technology Shanghai Co ltd
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Yaoxin Microelectronics Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention provides an output clamping protection module, a method, a chip and a drive protection system, which comprise: the first NMOS tube and the second NMOS tube are connected in series; the first resistor is connected between the output end and the grid electrode of the second NMOS tube; the first PMOS tube and the current-limiting anti-reverse unit are connected in series between the output end and the grid electrode of the second NMOS tube; and the clamping control unit generates a control signal of the first PMOS tube based on the voltage detection signal, switches on the first PMOS tube when the power supply voltage is powered down or is under-voltage, and switches off the first PMOS tube when the power supply voltage is normal. When the power supply is under-voltage, the gate potential of the second NMOS tube is quickly pulled up by the path, so that the drain-source of the second NMOS tube is conducted, the gate potential of the sixth NMOS tube is pulled down, and the sixth NMOS tube cannot be conducted to form a short-circuit path from the bus voltage to the ground; and meanwhile, the circuit quits working after the power supply voltage recovers to be normal, and the normal working of the circuit is not influenced.

Description

Output clamping protection module, method, chip and drive protection system
Technical Field
The invention relates to the field of integrated circuit design, in particular to an output clamping protection module, an output clamping protection method, a chip and a drive protection system.
Background
Fig. 1 shows a conventional circuit for driving and controlling a MOS transistor by a driver chip, which includes a driver chip 1 and external power NMOS transistors (Q1 and Q2). When the grid-source voltage of the external power NMOS tube Q2 is larger than the threshold voltage, the conduction condition of the MOS tube is achieved, and the drain source of the external power NMOS tube Q2 is conducted. The drain electrode of the external power NMOS tube Q1 is connected with a bus voltage VBUS (generally about 600V), the grid electrode of the external power NMOS tube Q1 is connected with a grid control signal G1, the source electrode of the external power NMOS tube Q1 is connected with the drain electrode of the external power NMOS tube Q2, and the connection point is a switch node E; the output end of the driving chip 1 is connected with the grid of the external power NMOS tube Q2 and drives the grid of the external power NMOS tube Q2. When the external power NMOS Q1 is just driven on, the voltage at the switching node E starts to increase rapidly from 0V. When the driving chip 1 is not powered on, due to the parasitic capacitance Cgd existing between the gate and the drain of the external power NMOS transistor Q2, the voltage rapidly rising at the switching node E charges the gate of the external power NMOS transistor Q2 through the parasitic capacitance Cgd, so that the gate-source voltage of the external power NMOS transistor Q2 is greater than the threshold voltage thereof, the drain-source of the external power NMOS transistor Q2 is conducted, a short-circuit path from the bus voltage VBUS to the ground is formed, and if the limitation is not imposed, the external power NMOS transistor Q2 is overheated and even explodes.
Therefore, how to clamp the gate of the external power NMOS transistor Q2 and improve the safety of the circuit has become one of the technical problems to be solved by those skilled in the art.
It should be noted that the above background description is provided only for the sake of clarity and complete description of the technical solutions of the present application, and for the sake of understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an output clamp protection module, method, chip and driving protection system, which are used to solve the problems of overheat damage and even machine explosion caused by the simultaneous conduction of power NMOS transistors when the driving chip is not powered in the prior art.
In order to achieve the above and other related objects, the present invention provides an output clamp protection module, applied in a driving circuit, comprising:
the current limiting and reverse preventing circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first resistor, a first PMOS (P-channel metal oxide semiconductor) tube, a current limiting and reverse preventing unit and a clamping control unit;
the drain electrode of the first NMOS tube is connected with a power supply voltage, the grid electrode of the first NMOS tube receives a first control signal, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and is used as the output end of the output clamping protection module to output a driving signal;
the grid electrode of the second NMOS tube receives a second control signal, and the source electrode of the second NMOS tube is grounded;
one end of the first resistor is connected with the output end of the output clamping protection module, and the other end of the first resistor is connected with the grid electrode of the second NMOS tube;
the source electrode of the first PMOS tube is connected with the output end of the output clamping protection module, and the drain electrode of the first PMOS tube is connected with the first end of the current-limiting anti-reverse unit;
the second end of the current-limiting anti-reverse unit is connected with the grid electrode of the second NMOS tube and is used for limiting the current flowing into the grid electrode of the second NMOS tube and preventing the current from flowing from the grid electrode of the second NMOS tube to the output end of the output clamping protection module through the first PMOS tube;
the clamping control unit receives a voltage detection signal, generates a control signal of the first PMOS tube based on the voltage detection signal, switches on the first PMOS tube when the power supply voltage is powered down or is under-voltage, and switches off the first PMOS tube when the power supply voltage is normal.
Optionally, the current-limiting anti-reverse unit includes a diode and a second resistor connected in series, and the second resistor is used for current-limiting protection of the diode.
Optionally, the output clamp protection module further includes a first voltage regulator tube, an anode of the first voltage regulator tube is connected to a gate of the first PMOS tube, and a cathode of the first voltage regulator tube is connected to a source of the first PMOS tube.
Optionally, the clamp control unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second PMOS transistor, a third resistor, and a fourth resistor;
the source electrode of the third NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with the voltage detection signal, and the drain electrode of the third NMOS tube is connected with the source electrode of the first PMOS tube through the third resistor;
the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the voltage detection signal, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the first PMOS tube through the fourth resistor;
the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the second PMOS tube and outputs a control signal of the first PMOS tube;
the grid electrode of the second PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube.
More optionally, the clamping control unit further includes a fifth resistor and a sixth resistor;
the fifth resistor is connected between the drain electrode of the fourth NMOS tube and the grid electrode of the second PMOS tube, the sixth resistor is connected between the drain electrode of the fifth NMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the second PMOS tube outputs the control signal of the first PMOS tube.
More optionally, the clamping control unit further includes a second voltage regulator tube and a third voltage regulator tube;
the anode of the second voltage-regulator tube is grounded, and the cathode of the second voltage-regulator tube is connected with the grid of the fifth NMOS tube; and the anode of the third voltage-stabilizing tube is connected with the grid electrode of the second PMOS tube, and the cathode of the third voltage-stabilizing tube is connected with the source electrode of the second PMOS tube.
Optionally, the first resistance is set to 500k ohms or higher.
To achieve the above and other related objects, the present invention provides a chip, which at least includes the above output clamp protection module.
To achieve the above and other related objects, the present invention provides a drive protection system, including at least:
a drive circuit and a half-bridge circuit;
the driving circuit comprises a driving control module and the output clamping protection module, and is used for providing a driving signal with clamping characteristics; the drive control module provides a control signal for the output clamping protection module;
the half-bridge circuit is connected to the output end of the driving circuit and works based on a driving signal provided by the driving circuit; the half-bridge circuit comprises a sixth NMOS transistor and a seventh NMOS transistor; the source electrode of the sixth NMOS tube is grounded, the grid electrode of the sixth NMOS tube is connected with the output end of the driving circuit, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube; the grid electrode of the seventh NMOS tube is connected with a third control signal, and the drain electrode of the seventh NMOS tube is connected with the bus voltage; wherein the bus voltage is greater than a supply voltage of the output clamp protection module.
In order to achieve the above objects and other related objects, the present invention provides an output clamp protection method, which is implemented based on the above driving protection system, and the output clamp protection method at least includes:
under the condition that a seventh NMOS tube is conducted and the power supply voltage of the output clamping protection module is in power failure or under voltage, the first PMOS tube is conducted, the grid potential of a second NMOS tube is pulled up by a path where the first PMOS tube and the current-limiting anti-reverse unit are located and a path where the first resistor is located, the second NMOS tube is conducted and provides a pull-down channel for the grid of a sixth NMOS tube, and the sixth NMOS tube is turned off;
and under the condition that the power supply voltage of the output clamping protection module is normal, the first PMOS tube and a passage where the current-limiting anti-reverse unit is located are switched off.
Optionally, the current-limiting anti-reverse unit includes a diode and a second resistor connected in series, and when the seventh NMOS transistor is turned on and the power supply voltage of the output clamp protection module is powered down or under-voltage, and when a difference between a gate potential of the sixth NMOS transistor and a gate potential of the second NMOS transistor is greater than or equal to a start-up voltage of the diode, a gate potential of the second NMOS transistor is pulled up by a path where the first PMOS transistor and the current-limiting anti-reverse unit are located; when the difference value between the grid potential of the sixth NMOS tube and the grid potential of the second NMOS tube is smaller than the starting voltage of the diode, the first PMOS tube and the path where the current-limiting anti-reverse unit is located are not conducted, and the grid potential of the second NMOS tube is pulled up by the path where the first resistor is located.
As described above, the output clamp protection module, method, chip and driving protection system of the present invention have the following advantages:
the output clamping protection module, the method, the chip and the drive protection system of the invention provide a path to quickly pull up the grid potential of the second NMOS tube when the power supply is under-voltage, so that the drain-source of the second NMOS tube is conducted, the grid potential of the sixth NMOS tube is pulled down, and the sixth NMOS tube cannot be conducted to form a short-circuit path from the bus voltage to the ground; and meanwhile, the circuit quits working after the power supply voltage recovers to be normal, and the normal working of the circuit is not influenced.
The output clamping protection module has the advantages of simple structure, easy realization and high safety performance.
Drawings
Fig. 1 is a schematic circuit diagram of a driving control MOS transistor of a driving chip in the prior art.
Fig. 2 is a schematic circuit diagram of a driving chip driving control MOS transistor with a pull-down protection function.
Fig. 3 is a schematic structural diagram of an output clamp protection module according to the present invention.
Fig. 4 is a schematic structural diagram of the drive protection system of the present invention.
Description of the element reference numerals
1. Driving chip
2. Output clamp protection module
21. Current-limiting anti-reverse unit
22. Clamping control unit
3. Driving circuit
4. Half-bridge circuit
5. Drive control module
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2-4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In order to solve the problem that the power NMOS tubes are conducted simultaneously, a resistor Ra is arranged in the driving chip 1 to raise the grid potential of the lower tube, and then the output potential is pulled down. As shown in fig. 2, the driving chip 1 mainly includes a power terminal VCC, a ground terminal VSS, NMOS transistors Q3 and Q4, and a resistor Ra. The drain electrode of the NMOS tube Q3 is connected with a power supply end VCC, the grid electrode is connected with a grid control signal G2, and the source electrode is connected with the drain electrode of the NMOS tube Q4 and serves as the output end OUT of the driving chip 1; the grid electrode of the NMOS tube Q4 is connected with a grid control signal G3, and the source electrode is grounded; one end of the resistor Ra is connected with the output end OUT, and the other end of the resistor Ra is connected with the grid electrode of the NMOS tube Q4. When the external power NMOS tube Q1 is just driven to be conducted, the rapidly-rising voltage of the switch node E charges the grid electrode of the external power NMOS tube Q2 through the parasitic capacitor Cgd, the grid electrode potential of the external power NMOS tube Q2 is pulled high (namely the output end OUT potential of the driving chip 1 is pulled high), the grid electrode potential of the NMOS tube Q4 is pulled high through the resistor Ra, the grid source voltage of the NMOS tube Q4 is larger than the threshold voltage of the NMOS tube Q4, the drain source of the NMOS tube Q4 is conducted, a path from the output end OUT of the driving chip 1 to the ground VSS is formed, the grid electrode potential of the external power NMOS tube Q2 is pulled to be lower than the threshold voltage, the external power NMOS tube Q2 is turned off, and therefore the problem of a short-circuit path from the bus voltage to the ground formed by the drain source conduction of the external power NMOS tube Q2 is solved.
As shown in fig. 2, if the resistor Ra is implemented by a small resistor, although the pull-down speed is increased, when a preceding circuit (driving control circuit) inside the driving chip 1 drives the gate of the NMOS transistor Q4, a generated current flows from the gate of the NMOS transistor Q4 to the output terminal OUT of the driving chip 1, and there is energy exchange between the OUT terminal and the gate of the NMOS transistor Q4, thereby increasing the power consumption of the driving chip 1. Therefore, the resistor Ra is generally implemented by a large resistor (for example, the resistance value of the resistor Ra is greater than or equal to 500k ohms), but the speed of pulling down the potential of the large resistor is correspondingly slow, and the time of pulling down the required potential is too long, so that the drain-source conduction time of the external power NMOS transistor Q2 is still long, and is usually greater than 10us; during this time, the inrush current may still burn out subsequent circuits.
Based on the reasons, the invention provides an output clamping protection module, an output clamping protection method, a chip and a drive protection system, and further improves the safety.
As shown in fig. 3, the present invention provides an output clamp protection module 2, where the output clamp protection module 2 includes:
the circuit comprises a first NMOS tube NM1, a second NMOS tube NM2, a first resistor R1, a first PMOS tube PM1, a current-limiting anti-reverse unit 21 and a clamping control unit 22.
As shown in fig. 3, the drain of the first NMOS transistor NM1 is connected to a power supply voltage VCC, the gate receives a first control signal CTL1, and the source is connected to the drain of the second NMOS transistor NM 2; the grid electrode of the second NMOS tube NM2 receives a second control signal CTL2, and the source electrode is grounded VSS; the source electrode of the first NMOS tube NM1 and the drain electrode of the second NMOS tube NM2 are used as the output end OUT of the output clamping protection module 2 to output the driving signal of an external power tube.
Specifically, in this embodiment, the working states of the first NMOS transistor NM1 and the second NMOS transistor NM2 are opposite; when the first NMOS tube NM1 is conducted, the second NMOS tube NM2 is cut off, and therefore a high-level driving signal is obtained; when the first NMOS tube NM1 is cut off, the second NMOS tube NM2 is switched on, so that a low-level driving signal is obtained; and the control of the first NMOS tube NM1 is realized based on the first control signal CTL1, and the control of the second NMOS tube NM2 is realized based on the second control signal CTL 2.
As shown in fig. 3, one end of the first resistor R1 is connected to the output end OUT of the output clamp protection module 2, and the other end is connected to the gate of the second NMOS transistor NM 2.
Specifically, the first resistor R1 is configured to provide a first pull-up path for the gate of the second NMOS transistor NM2, and to prevent a current from flowing from the gate of the second NMOS transistor NM2 to the output end OUT of the output clamp protection module 2; the resistance value of the first resistor R1 is set to meet the conditions; in this embodiment, the resistance of the first resistor R1 is greater than or equal to 500K ohms, including but not limited to 510K ohms, 550K ohms, 570K ohms, 600K ohms, and 700K ohms, and may be set as needed in actual use, which is not limited to this embodiment.
As shown in fig. 3, the source of the first PMOS transistor PM1 is connected to the output end OUT of the output clamp protection module 2, and the drain is connected to the first end of the current-limiting anti-reverse unit 21. The second end of the current-limiting anti-reverse unit 21 is connected to the gate of the second NMOS transistor NM2, and is configured to limit the magnitude of the current flowing into the gate of the second NMOS transistor NM2, and prevent the current from flowing from the gate of the second NMOS transistor to the output end OUT of the output clamp protection module 2 through the first PMOS transistor PM1.
Specifically, the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21 form a path, and are configured to provide a second pull-up path for the gate of the second NMOS transistor NM 2. In this embodiment, the current-limiting anti-reverse unit 21 includes a diode D and a second resistor R2 connected in series, where the diode D is used to prevent current from flowing from the gate of the second NMOS transistor NM2 to the output terminal OUT of the output clamp protection module 2 through the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21 when the gate potential of the second NMOS transistor NM2 is higher than the potential of the output terminal OUT of the output clamp protection module 2; the second resistor R2 is used for current-limiting protection of the diode D to prevent the diode D from being burned out due to excessive current, and the resistance of the second resistor R2 is based on protection of the diode D, which is not described herein in detail. As an example, the anode of the diode D is connected to the drain of the first PMOS transistor PM1, and the cathode is connected to the second resistor R2; in practical use, the positions of the diode D and the second resistor R2 may be interchanged, so that the current-limiting and reverse-preventing function of the invention may be implemented, which is not limited to this embodiment.
As shown in fig. 3, the clamp control unit 22 receives a voltage detection signal UVB, generates a control signal of the first PMOS transistor PM1 based on the voltage detection signal UVB, turns on the first PMOS transistor PM1 when the power supply voltage VCC is powered down or under-voltage, and turns off the first PMOS transistor PM1 when the power supply voltage VCC is normal.
Specifically, in this embodiment, the clamp control unit 22 includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a second PMOS transistor PM2, a third resistor R3, and a fourth resistor R4. The source of the third NMOS transistor NM3 is grounded GND, the gate is connected to the voltage detection signal UVB, and the drain is connected to the source of the first PMOS transistor PM1 (i.e., the output end OUT of the output clamp protection module 2) via the third resistor R3. The source electrode of the fourth NMOS transistor NM4 is grounded GND, the gate electrode is connected to the voltage detection signal UVB, and the drain electrode is connected to the source electrode of the first PMOS transistor PM1 via the fourth resistor R4. The source electrode of the fifth NMOS tube NM5 is grounded GND, the grid electrode of the fifth NMOS tube NM5 is connected with the drain electrode of the third NMOS tube NM3, and the drain electrode of the fifth NMOS tube NM5 is connected with the drain electrode of the second PMOS tube PM2 and outputs a control signal of the first PMOS tube PM1. The grid electrode of the second PMOS tube PM2 is connected with the drain electrode of the fourth NMOS tube NM4, and the source electrode of the second PMOS tube PM2 is connected with the source electrode of the first PMOS tube PM1.
More specifically, when the power supply voltage VCC is powered down or under-voltage, the voltage detection signal UVB is at a low level (for example, UVB = 0), gate-source voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are smaller than threshold voltages thereof, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both in a cut-off state, and currents flowing through the third resistor R3 and the fourth resistor R4 are zero, so that potentials at drains of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are equal to a potential at the output end OUT of the output clamp protection module 2; the gate-source voltage of the fifth NMOS transistor NM5 is greater than the threshold voltage thereof, so that the fifth NMOS transistor NM5 is in a conducting state; the gate-source voltage of the second PMOS transistor PM2 is greater than the threshold voltage thereof, so that the second PMOS transistor PM2 is in a cut-off state, so that the first PMOS transistor PM1 is in a conduction state, and a path is formed from the output end OUT of the output clamp protection module 2 to the gate of the second NMOS transistor NM2 through the first PMOS transistor PM1, the diode D, and the second resistor R2 in sequence. When the power supply voltage VCC is normal, the voltage detection signal UVB is at a high level (for example, UVB = 5V), the gate-source voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are greater than the threshold voltage thereof, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both in a conducting state, and the potentials at the drains of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are pulled down to a potential close to 0V; the gate-source voltage of the fifth NMOS transistor NM5 is less than the threshold voltage thereof, so that the fifth NMOS transistor NM5 is in a cut-off state; the gate-source voltage of the second PMOS transistor PM2 is smaller than the threshold voltage thereof, so that the second PMOS transistor PM2 is in a conducting state, the gate potential of the first PMOS transistor PM1 is pulled up to a potential close to the output end OUT of the output clamp protection module 2, the gate-source voltage of the first PMOS transistor PM1 is larger than the threshold voltage thereof, so that the first PMOS transistor PM1 is in a blocking state, and a path from the output end OUT of the output clamp protection module 2 to the gate of the second NMOS transistor NM2 sequentially passes through the first PMOS transistor PM1, the diode D, the second resistor R2 and is not connected.
Specifically, as another implementation manner of the present invention, the clamping control unit 22 further includes a fifth resistor R5 and a sixth resistor R6. The fifth resistor R5 is connected between the drain of the fourth NMOS transistor NM4 and the gate of the second PMOS transistor PM2, the sixth resistor R6 is connected between the drain of the fifth NMOS transistor NM5 and the drain of the second PMOS transistor PM2, and the drain of the second PMOS transistor PM2 outputs the control signal of the first PMOS transistor PM1.
It should be noted that the resistors in the clamp control unit 22 function as current limiting and level shifting.
Specifically, as another implementation manner of the present invention, the clamping control unit 22 further includes a second regulator tube Dz2 and a third regulator tube Dz3. The anode of the second voltage regulator tube Dz2 is grounded GND, and the cathode of the second voltage regulator tube Dz2 is connected with the grid of the fifth NMOS tube NM 5; the anode of the third voltage-regulator tube Dz3 is connected with the gate of the second PMOS tube PM2, and the cathode is connected with the source of the second PMOS tube PM 2. The second voltage-regulator tube Dz2 and the third voltage-regulator tube Dz3 are used for protecting the corresponding MOS tube and limiting the voltage between the grid electrode and the source electrode so as to prevent the MOS tube from being damaged due to high voltage caused by surge or other factors.
As shown in fig. 3, as an implementation manner of the present invention, the output clamp protection module 2 further includes a first voltage regulator Dz1, an anode of the first voltage regulator Dz1 is connected to a gate of the first PMOS transistor PM1, and a cathode of the first voltage regulator Dz1 is connected to a source of the first PMOS transistor PM1. The first voltage regulator tube Dz1 is used for protecting the first PMOS tube PM1 and preventing the first PMOS tube PM1 from being damaged by high voltage caused by surge or other factors.
The invention also provides a chip, which at least comprises the output clamping protection module 2, and other modules can be arranged as required, which is not repeated herein.
As shown in fig. 4, the present invention provides a drive protection system, including: a drive circuit 3 and a half-bridge circuit 4.
As shown in fig. 4, the driving circuit 3 includes a driving control module 5 and the output clamp protection module 2, and is configured to provide a driving signal with a clamp characteristic; the driving control module 3 provides a control signal for the output clamp protection module 2.
Specifically, the driving control module 5 generates control signals (CTL 1 and CTL 2) of the first NMOS transistor NM1 and the second NMOS transistor NM2, where the control signals of the first NMOS transistor NM2 and the second NMOS transistor NM2 include but are not limited to PWM signals, and are set according to actual requirements. When the power supply voltage VCC works normally, the output clamp protection module 2 generates a driving signal of the half-bridge circuit 4 based on a control signal provided by the driving control module 3; when the power supply voltage VCC is powered down or undervoltage, the output clamp protection module 2 clamps the output end OUT of the output clamp protection module 2 based on a path formed by the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21, and the first resistor R1.
As shown in fig. 4, the half-bridge circuit 4 is connected to an output terminal of the driving circuit 3 and operates based on a driving signal provided by the driving circuit 3. The half-bridge circuit 4 comprises a sixth NMOS tube NM6 and a seventh NMOS tube NM7; the source electrode of the sixth NMOS tube NM6 is grounded, the grid electrode of the sixth NMOS tube NM6 is connected with the output end of the driving circuit 3, and the drain electrode of the sixth NMOS tube NM6 is connected with the source electrode of the seventh NMOS tube NM7; the grid electrode of the seventh NMOS tube NM7 is connected with a third control signal CTL3, and the drain electrode is connected with a bus voltage VBUS; wherein the bus voltage VBUS is greater than the supply voltage VCC of the output clamp protection module 2.
Specifically, in this embodiment, the bus voltage VBUS is about 600V, the power supply voltage VCC of the output clamp protection module 2 is 8V to 24V, and values of the bus voltage VBUS and the power supply voltage VCC of the output clamp protection module 2 may be set as needed in actual use, for example, a ratio of the bus voltage VBUS to the power supply voltage VCC of the output clamp protection module 2 is greater than or equal to 20 and less than or equal to 100.
It should be noted that the third control signal CTL3 may be provided by the driving circuit 3, or may be provided by other circuits, which are not described herein. In normal operation, the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are not turned on at the same time.
The working principle of the drive protection system is as follows:
for an NMOS tube, when the voltage between a grid electrode and a source electrode, namely the grid-source voltage is larger than the threshold voltage of the NMOS tube, the drain electrode and the source electrode are conducted; the gate-source voltage and the threshold voltage of the NMOS tube are both positive.
For a PMOS tube, when the voltage between a grid electrode and a source electrode, namely the grid-source voltage is smaller than the threshold voltage of the PMOS tube, the drain electrode and the source electrode are conducted; the grid-source voltage and the threshold voltage of the PMOS tube are both negative.
1) The seventh NMOS transistor NM7 is turned on and the supply voltage VCC of the output clamp protection module 2 is powered down or under-voltage: the first PMOS tube PM1 and the current-limiting anti-reverse unit 21 are conducted on the channel, the first resistor R1 is located on the channel, the grid potential of the second NMOS tube NM2 is raised, the second NMOS tube NM2 is conducted and provides a pull-down channel for the grid of the sixth NMOS tube NM6, the sixth NMOS tube NM6 is turned off, and therefore the situation that the seventh NMOS tube NM7 and the sixth NMOS tube NM6 are conducted simultaneously is avoided.
Specifically, when the seventh NMOS transistor NM7 is just driven to turn on by the third control signal CTL3, the source voltage of the seventh NMOS transistor NM7 rises rapidly and charges the gate of the sixth NMOS transistor NM6 through the parasitic capacitance Cgd, and the gate potential of the sixth NMOS transistor NM6 is raised. The clamp control unit 22 controls the first PMOS transistor PM1 to be turned on (that is, the paths where the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21 are located are turned on), then, the current flows from the output end OUT of the output clamp protection module 2 to the gate of the second NMOS transistor NM2 through the paths where the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21 are located, the gate potential of the second NMOS transistor NM2 is pulled high rapidly, the second NMOS transistor NM2 is turned on, a pull-down path from the gate of the sixth NMOS transistor NM6 to the ground VSS is formed (the gate potential of the sixth NMOS transistor NM6 is pulled low rapidly), the gate-source voltage of the sixth NMOS transistor NM6 is smaller than the threshold voltage thereof, and the sixth NMOS transistor is turned off. With the charging, the gate potential of the sixth NMOS transistor NM6 is continuously increased, at this time, when the path where the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21 are located keeps the conducting state, and the gate potential of the second NMOS transistor NM2 is pulled up to be close to the gate potential of the sixth NMOS transistor NM6, because the diode D has the turn-on voltage, and the difference between the gate potential of the sixth NMOS transistor NM6 and the gate potential of the second NMOS transistor NM2 does not reach the turn-on voltage of the diode D, the path where the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21 are not conducting, the gate potential of the second NMOS transistor NM2 is continuously pulled up by the path where the first resistor R1 is located, so that the second NMOS transistor NM2 is conducting, and the gate potential of the sixth NMOS transistor NM6 is pulled down, so that the sixth NMOS transistor NM6 keeps the stopping state.
More specifically, in this embodiment, when the difference between the gate potential of the sixth NMOS transistor NM6 and the gate potential of the second NMOS transistor NM2 is greater than or equal to 0.7V (the turn-on voltage of the diode D), the gate potential of the second NMOS transistor NM2 is pulled up by the path where the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21 are located; when the difference between the gate potential of the sixth NMOS NM6 and the gate potential of the second NMOS NM2 is within 0.7V (the difference is smaller than 0.7V, and the conduction condition of the diode D is not met, the path where the first PMOS PM1 and the current-limiting anti-reverse unit 21 are located is not conducted), the gate potential of the second NMOS NM2 is pulled up by the path where the first resistor R1 is located. As an example, when the gate-source voltage of the sixth NMOS transistor NM6 is 2V, the drain-source starts to be turned on, and the turn-on voltage of the diode is reduced to 0.7V, so that when the gate potential of the second NMOS transistor NM2 is less than or equal to 1.3V, the gate potential of the second NMOS transistor NM2 is quickly raised through the first PMOS transistor PM1 and the path where the current-limiting anti-reverse unit 21 is located; when the grid potential of the second NMOS tube NM2 is larger than 1.3V, the grid potential of the second NMOS tube NM2 is continuously pulled up by a path where the first resistor R1 is located.
2) Under the condition that the power supply voltage VCC of the output clamping protection module 2 is normal: and the first PMOS tube PM1 and the current-limiting anti-reverse unit 21 are switched off.
Specifically, when the power supply voltage VCC of the output clamp protection module 2 is normal, the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are controlled by respective gate control signals, and the gate voltage of the sixth NMOS transistor NM6 is not pulled up to be turned on due to the parasitic capacitance Cgd (when the seventh NMOS transistor NM7 is turned on, a pull-down channel exists in the gate of the sixth NMOS transistor NM6, and the sixth NMOS transistor NM6 is not turned on). At this time, the path where the first PMOS transistor PM1 and the current-limiting anti-reverse unit 21 are located is turned off, and only the path from the output end OUT of the output clamp protection module 2 to the gate of the second NMOS transistor NM2 through the first resistor R1 exists; the second NMOS transistor NM2 is turned on or off by the second control signal CTL 2; because the resistance value of the first resistor R1 is relatively large, the output end OUT of the output clamp protection module 2 has almost no influence on the gate potential of the second NMOS transistor NM2, and can be ignored, and the output clamp protection module 2 works normally.
According to the output clamping protection module, the method, the chip and the drive protection system, when a power supply is under-voltage or power-down, the grid potential of the second NMOS tube is quickly pulled up, so that the drain-source of the second NMOS tube is conducted to form a path for quickly pulling down the OUT potential of an output end, further, the grid voltage of the sixth NMOS tube is lower than the threshold voltage and cannot be conducted, and the seventh NMOS tube and the sixth NMOS tube are prevented from being conducted simultaneously to form a short-circuit path from bus voltage to ground; the circuit is not adversely affected and the working state of the chip when the power supply voltage is normal is not affected.
In summary, the present invention provides an output clamp protection module, method, chip and driving protection system, including: the current limiting and anti-reversing circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first resistor, a first PMOS (P-channel metal oxide semiconductor) tube, a current limiting and anti-reversing unit and a clamping control unit; the drain electrode of the first NMOS tube is connected with a power supply voltage, the grid electrode of the first NMOS tube receives a first control signal, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and is used as the output end of the output clamping protection module to output a driving signal; the grid electrode of the second NMOS tube receives a second control signal, and the source electrode of the second NMOS tube is grounded; one end of the first resistor is connected with the output end of the output clamping protection module, and the other end of the first resistor is connected with the grid electrode of the second NMOS tube; the source electrode of the first PMOS tube is connected with the output end of the output clamping protection module, and the drain electrode of the first PMOS tube is connected with the first end of the current-limiting anti-reversion unit; the second end of the current-limiting anti-reverse unit is connected with the grid electrode of the second NMOS tube and is used for limiting the current flowing into the grid electrode of the second NMOS tube and preventing the current from flowing from the grid electrode of the second NMOS tube to the output end of the output clamping protection module through the first PMOS tube; the clamping control unit receives a voltage detection signal, generates a control signal of the first PMOS tube based on the voltage detection signal, switches on the first PMOS tube when the power supply voltage is powered down or is under-voltage, and switches off the first PMOS tube when the power supply voltage is normal. According to the output clamping protection module, method, chip and drive protection system, when the power supply is under-voltage, the path is provided to quickly pull up the grid potential of the second NMOS tube, so that the drain-source of the second NMOS tube is conducted, the grid potential of the sixth NMOS tube is pulled down, and the sixth NMOS tube cannot be conducted to form a short-circuit path from the bus voltage to the ground; and meanwhile, the circuit quits working after the power supply voltage recovers to be normal, and the normal working of the circuit is not influenced. The output clamping protection module has the advantages of simple structure, easy realization and high safety performance. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. An output clamp protection module applied to a driving circuit, the output clamp protection module at least comprising:
the current limiting and reverse preventing circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first resistor, a first PMOS (P-channel metal oxide semiconductor) tube, a current limiting and reverse preventing unit and a clamping control unit;
the drain electrode of the first NMOS tube is connected with a power supply voltage, the grid electrode of the first NMOS tube receives a first control signal, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and is used as the output end of the output clamping protection module to output a driving signal;
the grid electrode of the second NMOS tube receives a second control signal, and the source electrode of the second NMOS tube is grounded;
one end of the first resistor is connected with the output end of the output clamping protection module, and the other end of the first resistor is connected with the grid electrode of the second NMOS tube;
the source electrode of the first PMOS tube is connected with the output end of the output clamping protection module, and the drain electrode of the first PMOS tube is connected with the first end of the current-limiting anti-reverse unit;
the second end of the current-limiting anti-reverse unit is connected with the grid electrode of the second NMOS tube and is used for limiting the current flowing into the grid electrode of the second NMOS tube and preventing the current from flowing from the grid electrode of the second NMOS tube to the output end of the output clamping protection module through the first PMOS tube;
the clamping control unit receives a voltage detection signal, generates a control signal of the first PMOS tube based on the voltage detection signal, switches on the first PMOS tube when the power supply voltage is in power failure or under-voltage, and switches off the first PMOS tube when the power supply voltage is normal.
2. The output clamp protection module of claim 1, wherein: the current-limiting anti-reverse unit comprises a diode and a second resistor which are connected in series, and the second resistor is used for carrying out current-limiting protection on the diode.
3. The output clamp protection module of claim 1, wherein: the output clamping protection module further comprises a first voltage-stabilizing tube, wherein the anode of the first voltage-stabilizing tube is connected with the grid electrode of the first PMOS tube, and the cathode of the first voltage-stabilizing tube is connected with the source electrode of the first PMOS tube.
4. The output clamp protection module of claim 1, wherein: the clamping control unit comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second PMOS tube, a third resistor and a fourth resistor;
the source electrode of the third NMOS tube is grounded, the grid electrode of the third NMOS tube is connected with the voltage detection signal, and the drain electrode of the third NMOS tube is connected with the source electrode of the first PMOS tube through the third resistor;
the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the voltage detection signal, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the first PMOS tube through the fourth resistor;
the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the second PMOS tube and outputs a control signal of the first PMOS tube;
the grid electrode of the second PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube.
5. The output clamp protection module of claim 4, wherein: the clamping control unit further comprises a fifth resistor and a sixth resistor;
the fifth resistor is connected between the drain electrode of the fourth NMOS tube and the grid electrode of the second PMOS tube, the sixth resistor is connected between the drain electrode of the fifth NMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the second PMOS tube outputs the control signal of the first PMOS tube.
6. The output clamp protection module of claim 4 or 5, wherein: the clamping control unit further comprises a second voltage-stabilizing tube and a third voltage-stabilizing tube;
the anode of the second voltage-stabilizing tube is grounded, and the cathode of the second voltage-stabilizing tube is connected with the grid electrode of the fifth NMOS tube; and the anode of the third voltage-stabilizing tube is connected with the grid electrode of the second PMOS tube, and the cathode of the third voltage-stabilizing tube is connected with the source electrode of the second PMOS tube.
7. The output clamp protection module of claim 1, wherein: the first resistance is set to 500k ohms or higher.
8. A chip comprising at least the output clamp protection module of any one of claims 1-7.
9. A drive protection system, characterized in that the drive protection system comprises at least:
a drive circuit and a half-bridge circuit;
the driving circuit comprises a driving control module and an output clamping protection module according to any one of claims 1-7, and is used for providing a driving signal with clamping characteristics; the drive control module provides a control signal for the output clamping protection module;
the half-bridge circuit is connected to the output end of the driving circuit and works based on a driving signal provided by the driving circuit; the half-bridge circuit comprises a sixth NMOS transistor and a seventh NMOS transistor; the source electrode of the sixth NMOS tube is grounded, the grid electrode of the sixth NMOS tube is connected with the output end of the driving circuit, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube; the grid electrode of the seventh NMOS tube is connected with a third control signal, and the drain electrode of the seventh NMOS tube is connected with the bus voltage; wherein the bus voltage is greater than a supply voltage of the output clamp protection module.
10. An output clamp protection method implemented based on the driving protection system according to claim 9, wherein the output clamp protection method at least comprises:
under the condition that a seventh NMOS tube is conducted and the power supply voltage of the output clamping protection module is in power failure or under voltage, the first PMOS tube is conducted, the grid potential of a second NMOS tube is pulled up by a path where the first PMOS tube and the current-limiting anti-reverse unit are located and a path where the first resistor is located, the second NMOS tube is conducted and provides a pull-down channel for the grid of a sixth NMOS tube, and the sixth NMOS tube is turned off;
and under the condition that the power supply voltage of the output clamping protection module is normal, the first PMOS tube and a passage where the current-limiting anti-reverse unit is located are switched off.
11. The output clamp protection method of claim 10, wherein: the current-limiting anti-reverse unit comprises a diode and a second resistor which are connected in series, and when the seventh NMOS tube is conducted and the power supply voltage of the output clamping protection module is in power failure or under voltage, and the difference value between the grid potential of the sixth NMOS tube and the grid potential of the second NMOS tube is larger than or equal to the starting voltage of the diode, the grid potential of the second NMOS tube is pulled up by a path where the first PMOS tube and the current-limiting anti-reverse unit are located; when the difference value between the grid potential of the sixth NMOS tube and the grid potential of the second NMOS tube is smaller than the starting voltage of the diode, the channel where the first PMOS tube and the current-limiting anti-reverse unit are located is not conducted, and the grid potential of the second NMOS tube is pulled up by the channel where the first resistor is located.
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