CN116544904A - Low-voltage difference detection anti-reverse-filling protection circuit, load switch chip and power supply system - Google Patents

Abstract

The invention provides a low-voltage difference detection anti-reverse-filling protection circuit, a load switch chip and a power supply system, wherein the low-voltage difference detection anti-reverse-filling protection circuit comprises: the device comprises a first PMOS tube, a second PMOS tube, a pressure difference detection module and a protection control module; the first PMOS tube and the second PMOS tube are connected in series between the input voltage and the output voltage; the voltage difference detection module is used for detecting low voltage difference between output voltage and input voltage based on a third PMOS tube with a low threshold value, and triggering the protection control module to turn off the first PMOS tube and the second PMOS tube to prevent current reverse-filling when the output voltage is larger than the input voltage and the voltage difference value between the output voltage and the input voltage is larger than the threshold voltage absolute value of the third PMOS tube, and meanwhile, voltage clamping is carried out on the third PMOS tube. The invention solves the problems that two power rails are needed, reverse filling protection cannot be carried out under low pressure difference and the like in the prior art.

Description

Low-voltage difference detection anti-reverse-filling protection circuit, load switch chip and power supply system

Technical Field

The invention relates to the technical field of power management, in particular to a low-voltage difference detection anti-reverse-filling protection circuit, a load switch chip and a power system.

Background

Nowadays, load switch chips play an increasingly important role in power management; the load switch chip realizes the communication and disconnection between the power supply and the load by controlling the working state of the power tube, and has the protection functions of anti-reverse filling, anti-surge current, overvoltage protection, overcurrent protection and the like which are integrated inside, so that the power supply safety of the load is greatly improved, and ultra-stable device and system level protection are realized.

In high reliability load application scenarios, power supply multiplexing redundancy designs are very common. In order to prevent the reverse current flowing between the main power supply and the auxiliary power supply in the power supply redundancy design, a load switch chip with a reverse current flowing preventing function is needed to realize the isolation between the main power supply and the auxiliary power supply. The main path power supply and the auxiliary path power supply are short-circuited to supply power to the load after passing through the load switch chip, so that the damage to the prior power supply caused by reverse current filling of the main path and the auxiliary path can be effectively avoided.

In the design of the high-reliability redundant power supply, the power supply 1 and the power supply 2 are mutually standby. When both power supplies are normal, the power supply 1 and the power supply 2 are connected together through the load switch chip 1 and the load switch chip 2 respectively to provide the required power supply voltage for the load. When one of the power supplies is abnormal, taking the power supply 1 as an example, the power supply 2 is used for supplying power to the load independently, and the voltage of the output end of the load switch chip 1 is higher than the voltage of the input end at the moment, if the anti-reverse current protection measures are not applied, the risk of damaging the power supply 1 exists.

At present, aiming at the problem of current reverse-filling at the output end of a load switch chip, the following processing means are mainly provided:

firstly, by utilizing the unidirectional conduction property of the diode, a diode is connected in series between the load switch chip and the load so as to achieve the purpose of preventing current from flowing backwards.

The scheme has simple circuit structure, but the excessive forward conduction voltage of the diode can cause great power loss between the power supply and the load when the system works normally, which is contrary to the development trend of improving the efficiency of the power supply system.

Secondly, comparing the input and output sampling voltages by using a hysteresis comparator, and controlling the grid electrode of the power tube according to the comparison result; meanwhile, in order to prevent the parasitic diode of the power tube from leaking, the substrate potential of the power tube needs to be processed, if the power tube is a PMOS power tube, a substrate potential selection circuit is added in the chip, so that the substrate of the power tube can be switched to the maximum value between VIN and VOUT, and if the power tube is an NMOS power tube, the substrate of the power tube is connected to the reference ground.

The power tube in the scheme adopts a single tube form; the hysteresis value of the comparator can be set to be very small to be applied to current reverse-irrigation prevention under a low-output-input differential pressure scene, wherein the hysteresis value is a critical pressure difference value for triggering reverse-irrigation prevention protection, but the biggest defect is that a redundant comparator circuit and a substrate potential selection circuit cannot work normally when the input voltage is very low, and an additional power rail is needed; in addition, in the anti-reverse-filling protection state, the grid voltage of the power tube is equal to the output voltage or the input voltage, which means that the anti-reverse-filling protection can only be realized within the withstand voltage range of the MOS tube, and the power tube can be damaged if the voltage exceeds the withstand voltage range.

And thirdly, adopting a mode that two power tubes are connected in series, and connecting anodes or cathodes of two parasitic diodes at the same time, so as to realize blocking a channel of reverse current flowing from output to input through a channel of the MOS tube and the parasitic diodes.

Compared with the first scheme, the scheme has smaller on voltage, but the existing circuit structure can only play a role in protection when the output voltage exceeds a larger value of the input voltage, and in practical application, the current of tens of amperes reversely flows when the voltage difference is low, so that the application range is limited to a certain extent.

In view of this, a protection circuit for preventing current reverse current flowing is proposed for the power redundancy scheme, which is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of the above drawbacks of the prior art, the present invention is directed to providing a low-voltage-difference detection anti-reverse-filling protection circuit, a load switch chip and a power supply system, which are used for solving the problems that in the prior art, two power rails are required in scheme 2 and scheme 3 cannot perform anti-reverse-filling protection under low voltage difference.

To achieve the above and other related objects, the present invention provides a low-dropout detection anti-reverse-filling protection circuit, including: the device comprises a first PMOS tube, a second PMOS tube, a pressure difference detection module and a protection control module;

the first PMOS tube and the second PMOS tube are connected in series between the input voltage and the output voltage;

the voltage difference detection module performs low voltage difference detection on the output voltage and the input voltage based on a third PMOS tube with a low threshold value, and triggers the protection control module to turn off the first PMOS tube and the second PMOS tube to prevent current reverse charging and simultaneously performs voltage clamping on the third PMOS tube when the output voltage is larger than the input voltage and the voltage difference value between the output voltage and the input voltage is larger than the absolute value of the threshold voltage of the third PMOS tube.

Optionally, the differential pressure detection module includes: the third PMOS tube, the first clamping unit and the second clamping unit;

the grid electrode of the third PMOS tube is connected with the output end of the first clamping unit, the source electrode of the third PMOS tube is connected with the substrate of the third PMOS tube and the output voltage of the third PMOS tube is connected with the substrate of the third PMOS tube, and the third PMOS tube is used for being conducted when the differential pressure value is larger than the absolute value of the low threshold value;

the first clamping unit is connected between the input voltage and the output voltage and used for clamping the gate-source voltage of the third PMOS tube;

the second clamping unit is connected with the drain electrode of the third PMOS tube and used for clamping the drain voltage of the third PMOS tube and providing bias voltage for the protection control module.

Optionally, the first clamping unit includes: the first resistor, the second resistor and the first triode;

the first end of the first resistor is connected with the input voltage, and the second end of the first resistor is connected with the first end of the second resistor and the grid electrode of the third PMOS tube; the second end of the second resistor is connected with the emitter of the first triode; the base electrode of the first triode is connected with the collector electrode of the first triode and is connected with the output voltage.

Optionally, the second clamping unit includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third resistor, a fourth resistor and a fifth resistor;

the fourth PMOS tube and the fifth PMOS tube are connected in series between the output voltage and the reference ground by adopting a diode connection method and the third resistor; the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the sixth PMOS tube is connected with the substrate of the sixth PMOS tube and the drain electrode of the sixth PMOS tube is connected with the first end of the fourth resistor; the second end of the fourth resistor is connected with the reference ground through the fifth resistor and generates the bias voltage.

Optionally, the protection control module includes: a first protection unit and a second protection unit;

after the first protection unit is triggered, the first PMOS tube is turned off by pulling the grid voltage of the first PMOS tube to the input voltage;

and after the second protection unit is triggered, the second PMOS tube is turned off by pulling the grid voltage of the second PMOS tube to the output voltage.

Optionally, the first protection unit includes: the first NMOS tube, the sixth resistor, the seventh resistor and the seventh PMOS tube;

the grid electrode of the first NMOS tube is connected with bias voltage, the source electrode of the first NMOS tube is connected with the substrate of the first NMOS tube and is connected with the reference ground, and the drain electrode of the first NMOS tube is connected with the first end of the sixth resistor; the second end of the sixth resistor is connected with the input voltage through the seventh resistor and is connected with the grid electrode of the seventh PMOS tube; and the source electrode of the seventh PMOS tube is connected with the substrate of the seventh PMOS tube and the input voltage, and the drain electrode of the seventh PMOS tube is connected with the grid electrode of the first PMOS tube.

Optionally, the second protection unit includes: the second NMOS tube, the eighth resistor, the ninth resistor and the eighth PMOS tube;

the grid electrode of the second NMOS tube is connected with bias voltage, the source electrode of the second NMOS tube is connected with the substrate of the second NMOS tube and is connected with the reference ground, and the drain electrode of the second NMOS tube is connected with the first end of the eighth resistor; the second end of the eighth resistor is connected with the output voltage through the ninth resistor and is connected with the grid electrode of the eighth PMOS tube; and the source electrode of the eighth PMOS tube is connected with the substrate of the eighth PMOS tube and the output voltage, and the drain electrode of the eighth PMOS tube is connected with the grid electrode of the second PMOS tube.

Optionally, the gate of the first PMOS transistor is connected to a first gate control signal, the source is connected to the substrate thereof and to the input voltage, and the drain is connected to the drain of the second PMOS transistor; and the grid electrode of the second PMOS tube is connected with a second grid control signal, and the source electrode of the second PMOS tube is connected with the substrate of the second PMOS tube and is connected with the output voltage.

The invention also provides a load switch chip, comprising: the low-voltage difference detection anti-reverse-filling protection circuit according to any one of the above.

Optionally, the load switch chip further includes: a start control circuit, an overcurrent protection circuit and a thermal shutdown circuit;

the starting control circuit is used for generating a first grid control signal and a second grid control signal after the chip is started to control the first PMOS tube and the second PMOS tube to be conducted;

the overcurrent protection circuit is connected between the low-voltage difference detection anti-reverse-filling protection circuit and the starting control circuit, and is used for sampling the current flowing through the first PMOS tube and the second PMOS tube to obtain a sampling current, and generating an overcurrent protection signal when the sampling current is larger than a reference current;

the thermal shutdown circuit is connected with the starting control circuit and is used for sampling the temperature of the chip to obtain a sampling temperature and generating an over-temperature protection signal when the sampling temperature is greater than a set temperature;

and the starting control circuit also controls the first PMOS tube and the second PMOS tube to be turned off according to the overcurrent protection signal and/or the overtemperature protection signal.

Optionally, the load switch chip further includes: the enabling control circuit is connected with the starting control circuit and is used for starting the chip when the input enabling signal is larger than a first set value and closing the chip when the input enabling signal is smaller than a second set value; wherein the first set value is greater than the second set value.

Optionally, the load switch chip further includes: a reference circuit for providing the reference current; wherein the reference circuit includes: the reference module is used for providing reference voltage, and the operational amplifier module is connected with the output end of the reference module and used for converting the reference voltage into the reference current.

The present invention also provides a power supply system including: at least one load switch chip, at least one power supply and a load according to any one of the above claims;

the power supply is connected to the load through the load switch chip, wherein the power supply supplies power to the load, and the load switch chip performs anti-reverse irrigation protection on the power supply.

As described above, the low-voltage difference detection anti-reverse-filling protection circuit, the load switch chip and the power supply system provided by the invention have the advantages that a low-voltage difference detection circuit under a single power supply rail is designed by using the PMOS tube with a low threshold value in a CMOS process, the anti-reverse-filling protection function can be triggered and started based on a minimum output-input voltage difference value, and the reverse voltage detection sensitivity is improved; meanwhile, even if the input is powered down to very low voltage, the output-input differential pressure value can be normally detected, so that the reverse voltage can be detected and the reverse-filling prevention protection function can be triggered to be started during extremely low input without providing an extra power supply, thereby being beneficial to widening application conditions and widening application range. In addition, the PMOS tube with a low threshold value is subjected to clamping protection, so that damage caused by overvoltage is avoided, and the reliability of the circuit is improved.

Drawings

Fig. 1 is a schematic structural diagram of a low-medium voltage differential detection anti-reverse-filling protection circuit according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of a load switch chip according to a second embodiment of the invention.

Fig. 3 is a schematic diagram showing the actual measurement result of the chip under condition 1 according to the second embodiment of the present invention.

Fig. 4 is a schematic diagram showing the actual measurement result of the chip under condition 2 according to the second embodiment of the present invention.

Fig. 5 is a schematic diagram showing the actual measurement result of the chip under condition 3 according to the second embodiment of the present invention.

Fig. 6 is a schematic structural diagram of a power supply system according to a third embodiment of the invention.

Description of element reference numerals

10 load switch chip, 100 low voltage difference detection anti-reverse-filling protection circuit, 110 voltage difference detection module, 111 first clamping unit, 112 second clamping unit, 120 protection control module, 121 first protection unit, 122 second protection unit, 200 start control circuit, 300 overcurrent protection circuit, 400 thermal shutdown circuit, 500 enable control circuit, 600 reference circuit, 610 reference module, 620 operational amplifier module, 20 power supply, 30 load.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 6. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Example 1

As shown in fig. 1, the present embodiment provides a low-dropout detection anti-reverse-filling protection circuit 100, which includes: the device comprises a first PMOS tube PM1, a second PMOS tube PM2, a pressure difference detection module 110 and a protection control module 120.

The first PMOS tube PM1 and the second PMOS tube PM2 are connected in series between the input voltage VIN and the output voltage VOUT, and current reverse-flowing is prevented by controlling the first PMOS tube PM1 and the second PMOS tube PM2 to be turned off.

As an example, the gate of the first PMOS tube PM1 is connected to the first gate control signal VGH, the source is connected to the substrate thereof and to the input voltage VIN, and the drain is connected to the drain of the second PMOS tube PM 2; the gate of the second PMOS PM2 is connected to the second gate control signal VGL, and the source is connected to the substrate thereof and to the output voltage VOUT. It should be noted that the first gate control signal VGH and the second gate control signal VGL are provided by the front stage start control circuit, and respectively control the first PMOS tube PM1 and the second PMOS tube PM2 to be turned on so as to supply power to the rear stage load.

In this embodiment, the width-to-length ratio of the first PMOS tube PM1 and the second PMOS tube PM2 is equal; the first parasitic diode D1 in the first PMOS tube PM1 and the second parasitic diode D2 in the second PMOS tube PM2 are connected in a back-to-back mode, when the first PMOS tube PM1 and the second PMOS tube PM2 are turned off, reverse current filling from a channel is avoided, and meanwhile, the second parasitic diode D2 is in a reverse cut-off state, and reverse current filling from a substrate is avoided.

The voltage difference detection module 110 performs low voltage difference detection on the output voltage VOUT and the input voltage VIN based on the third PMOS tube lvt_pm3 with a low threshold, and triggers the protection control module 120 to turn off the first PMOS tube PM1 and the second PMOS tube PM2 and also performs voltage clamping on the third PMOS tube lvt_pm3 when the output voltage VOUT is greater than the input voltage VIN and a voltage difference value between the output voltage VOUT and the input voltage VIN is greater than an absolute value of the threshold voltage of the third PMOS tube.

Specifically, the differential pressure detection module 110 includes: the third PMOS transistor lvt_pm3, the first clamping unit 111, and the second clamping unit 112. Wherein,,

the gate of the third PMOS transistor lvt_pm3 is connected to the output terminal of the first clamping unit 111, the source is connected to the substrate thereof and connected to the output voltage VOUT, and the drain is connected to the output terminal of the second clamping unit 112, for conducting when the voltage difference (i.e., VOUT-VIN) is greater than the absolute value of the threshold voltage thereof.

According to the working principle of the MOSFET device, when the gate-source voltage reaches the threshold voltage, the MOSFET device can be conducted to flow current. For the third PMOS transistor LVT_PM3 in the embodiment, the threshold voltage VTH_PM3 is about 300 mV; taking vth_pm3= -300mV as an example, when VOUT-VIN >300mV, the conduction condition of the third PMOS tube lvt_pm3 is satisfied, the third PMOS tube lvt_pm3 is turned on, and the protection control module 120 is triggered to turn off the first PMOS tube PM1 and the second PMOS tube PM2, so that the states of the input voltage and the output voltage can be detected more sensitively, and anti-reverse-filling protection under low voltage difference is realized.

The first clamping unit 111 is connected between the input voltage VIN and the output voltage VOUT, and is used for clamping the gate-source voltage vgs_m3 of the third PMOS transistor lvt_pm3.

As an example, the first clamping unit 111 includes: the first resistor R1, the second resistor R2 and the first triode Q1; the first end of the first resistor R1 is connected with the input voltage VIN, and the second end of the first resistor R2 is connected with the first end of the third PMOS tube LVT_PM3; the second end of the second resistor R2 is connected with the emitter of the first triode Q1; the base of the first triode Q1 is connected with the collector thereof and the output voltage VOUT.

In this embodiment, the first triode Q1 adopts a diode connection method and forms a clamping circuit with the first resistor R1 and the second resistor R2, so that the gate-source voltage vgs_pm3 of the third PMOS tube lvt_pm3 is clamped below 5V, and meanwhile, a bias voltage is provided for the third PMOS tube lvt_pm3.

The second clamping unit 112 is connected to the drain of the third PMOS transistor lvt_pm3, and is configured to clamp the drain voltage vd_m3 of the third PMOS transistor lvt_pm3 and provide the bias voltage VB for the protection control module 120, so as to trigger the protection control module 120 when the third PMOS transistor lvt_pm3 is turned on.

As an example, the second clamping unit 112 includes: the fourth PMOS tube PM4, the fifth PMOS tube PM5, the sixth PMOS tube PM6, the third resistor R3, the fourth resistor R4 and the fifth resistor R5; the fourth PMOS PM4 and the fifth PMOS PM5 are connected in series with the third resistor R3 between the output voltage VOUT and the ground GND by using diode connection; the grid electrode of the sixth PMOS tube PM6 is connected with the grid electrode of the fifth PMOS tube PM5, the source electrode is connected with the substrate of the sixth PMOS tube PM6 and is connected with the drain electrode of the third PMOS tube LVT_PM3, and the drain electrode is connected with the first end of the fourth resistor R4; the second end of the fourth resistor R4 is connected to the ground GND via a fifth resistor R5 and generates the bias voltage VB.

The fourth PMOS PM4 and the fifth PMOS PM5 adopt diode connection and are connected in series with the third resistor R3 between the output voltage VOUT and the ground GND: the grid electrode of the fourth PMOS tube PM4 is connected with the drain electrode thereof and the source electrode of the fifth PMOS tube PM5, and the source electrode is connected with the substrate thereof and the output voltage VOUT; the gate of the fifth PMOS transistor PM5 is connected to the drain thereof and to the ground GND via the third resistor R3, and the source is connected to the substrate thereof.

The protection control module 120 includes: the first protection unit 121 and the second protection unit 122. Wherein,,

after the first protection unit 121 is triggered, the first PMOS transistor PM1 is turned off by pulling the gate voltage of the first PMOS transistor PM1 to the input voltage VIN.

As an example, the first protection unit 121 includes: the first NMOS tube NM1, a sixth resistor R6, a seventh resistor R7 and a seventh PMOS tube PM7; the grid electrode of the first NMOS tube NM1 is connected with the bias voltage VB, the source electrode is connected with the substrate of the first NMOS tube NM1 and is connected with the ground GND, and the drain electrode is connected with the first end of the sixth resistor R6; the second end of the sixth resistor R6 is connected with the input voltage VIN through a seventh resistor R7 and connected with the grid electrode of a seventh PMOS tube PM7; the source electrode of the seventh PMOS tube PM7 is connected with the substrate thereof and the input voltage VIN, and the drain electrode is connected with the grid electrode of the first PMOS tube PM1.

In this embodiment, the circuit composed of the first NMOS transistor NM1, the sixth resistor R6 and the seventh resistor R7 provides the bias voltage for the seventh PMOS transistor PM7, and controls the on and off of the seventh PMOS transistor PM7, thereby completing the control of the gate of the first PMOS transistor PM1.

After the second protection unit 122 is triggered, the second PMOS transistor PM2 is turned off by pulling the gate voltage of the second PMOS transistor PM2 to the output voltage VOUT.

As an example, the second protection unit 122 includes: the second NMOS tube NM2, the eighth resistor R8, the ninth resistor R9 and the eighth PMOS tube PM8; the grid electrode of the second NMOS tube NM2 is connected with the bias voltage VB, the source electrode is connected with the substrate of the second NMOS tube NM2 and is connected with the ground GND, and the drain electrode is connected with the first end of the eighth resistor R8; the second end of the eighth resistor R8 is connected with the output voltage VOUT through a ninth resistor R9 and is connected with the grid electrode of the eighth PMOS tube PM8; the source electrode of the eighth PMOS tube PM8 is connected with the substrate thereof and the output voltage VOUT, and the drain electrode is connected with the grid electrode of the second PMOS tube PM2.

In this embodiment, the circuit composed of the second NMOS transistor NM2, the eighth resistor R8, and the ninth resistor R9 provides the bias voltage for the eighth PMOS transistor PM8, and controls the on and off of the eighth PMOS transistor PM8, thereby completing the control of the gate of the second PMOS transistor PM2.

Next, referring to fig. 1, the working principle of the low-dropout detection anti-reverse-filling protection circuit 100 of the present embodiment will be described; the low-voltage difference detection anti-reverse-filling protection circuit 100 comprises a normal working state and an anti-reverse-filling protection state. Take vth_pm3= -300mV as an example;

1. normal operating state (VIN > VOUT):

in a normal working state, the on-resistance of the first PMOS tube PM1 and the second PMOS tube PM2 is very small, and only has a voltage drop of tens of millivolts from the input voltage VIN to the output voltage VOUT; at this time, the liquid crystal display device,

the branch where the first resistor R1, the second resistor R2 and the first triode Q1 are positioned is not conducted, and the third PMOS tube LVT_PM3 is in a cut-off state;

the gate voltages vg_nm1=vg_nm2=vb=0 of the first NMOS transistor NM1 and the second NMOS transistor NM2, and therefore, the gate voltage vg_pm7=vin of the seventh PMOS transistor PM7, the gate voltage vg_pm8=vout of the eighth PMOS transistor PM8, and the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are also in the off state;

the grid electrodes of the first PMOS tube PM1 and the second PMOS tube PM2 are respectively controlled by a first grid control signal VGH and a second grid control signal VGL, the two MOS tubes are conducted, and current flows to output from input through channels of the first PMOS tube PM1 and the second PMOS tube PM2 to supply power for a later-stage load.

In this state, other branches except the branches where the fourth PMOS tube PM4, the fifth PMOS tube PM5 and the third resistor R3 are located are not turned on, so the anti-reverse-filling protection function of the circuit of this embodiment is not triggered to be turned on.

2. Anti-reverse irrigation protection state (VOUT > VIN):

when the value of VOUT-VIN is enough to enable the low-threshold third PMOS tube LVT_PM3 to be conducted, namely VOUT-VIN is more than 300mV, the anti-reverse-filling protection function of the circuit triggers and is started. The method comprises the following steps:

when 300mV < VOUT-VIN < 700mV, the first triode Q1 is in an off state (the conduction voltage drop of the first triode Q1 is about 700 mV), no current flows back from the output to the input through the first triode Q1, VG_PM3=VIN, |VGS_PM3|= |VIN-VOUT| >300mV, the third PMOS tube LVT_PM3 is conducted and|VGS_PM3| < 5V.

When VOUT-VIN is greater than 700mV, the first transistor Q1 is turned on

VG_PM3=VOUT-VBE_Q1-(VOUT-VBE_Q1-VIN)*R2/(R1+R2)，

VGS_PM3= (VIN-VOUT). Times.R2/(R1+R2) -VBE_Q1/(R1+R2), the absolute value of the gate-source voltage of the third PMOS tube LVT_PM3 is ensured not to be larger than 5V under the maximum pressure difference by reasonably setting the partial pressure proportion of the first resistor R1 and the second resistor R2 to ensure that the absolute value of the gate-source voltage of the third PMOS tube LVT_PM3 is more than 300 mV; vbe_q1 is the voltage difference between the base and the emitter of the first transistor Q1.

In summary, when the output voltage exceeds the input voltage by more than 300mV, the third PMOS transistor lvt_pm3 can be turned on without over-voltage between the gate and the source.

After the third PMOS tube lvt_pm3 is turned on, a channel through which carriers flow is formed under gate oxide between the source and the drain, and current flows from the output to the reference ground through the third PMOS tube lvt_pm3, the sixth PMOS tube PM6, the fourth resistor R4 and the fifth resistor R5, and this branch starts to be turned on.

Meanwhile, the voltage clamping is performed on the drain electrode of the third PMOS transistor lvt_pm3 by using a second clamping unit formed by the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, and the like, so that it can be obtained: the drain voltage vd_pm3=vout- |vgs_pm4| -vgs_pm5|+|vgs_pm6| of the third PMOS transistor lvt_pm3, therefore, the drain-source voltage vds_pm3= - |vgs_pm4|+|vgs_pm5|+|vgs_pm6| of the third PMOS transistor lvt_pm3 is approximately limited to about one|vgs|, the value is less than 5V, and it is ensured that the withstand voltage limit is not exceeded, wherein vgs_pm4 is the gate-source voltage of the fourth PMOS transistor PM4, vgs_pm5 is the gate-source voltage of the fifth PMOS transistor PM5, and vgs_pm6 is the gate-source voltage of the sixth PMOS transistor PM 6; in addition, the substrate of the third PMOS tube lvt_pm3 is a self-connected source, and the voltage difference vbs_pm3 between the substrate of the third PMOS tube lvt_pm3 and the source will not have an overpressure condition, so that the third PMOS tube lvt_pm3 with a low threshold value can always work in a safe state.

Accordingly, the gate voltages vg_nm1=vg_nm2= (VOUT- |vds_pm3| - |vds_pm6|) R5/(r4+r5), where vds_pm6 is the drain-source voltage of the sixth PMOS tube PM 6; as is apparent from the above description, as long as the width-to-length ratio of the third PMOS transistor lvt_pm3 and the sixth PMOS transistor PM6 and the voltage division ratio of the fourth resistor R4 and the fifth resistor R5 are reasonably designed, the gate voltages of the first NMOS transistor NM1 and the second NMOS transistor NM2 can be higher than the respective threshold voltages, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, and current flows from the input voltage VIN to the ground through the seventh resistor R7, the sixth resistor R6 and the first NMOS transistor NM1, and from the output voltage VOUT to the ground through the ninth resistor R9, the eighth resistor R8 and the second NMOS transistor NM 2.

The same applies to the gate bias voltages of the first NMOS transistor NM1 and the second NMOS transistor NM2, where the gate voltage vg_pm7=vds_nm1×r7/(r6+r7) +vin×r6/(r6+r7) of the seventh PMOS transistor PM7, the gate voltage vg_pm8=vds_nm2×r9/(r8+r9) +vout×r8/(r8+r9) of the eighth PMOS transistor PM8, where vds_nm1 is the drain-source voltage of the first NMOS transistor NM1, and vds_nm2 is the drain-source voltage of the second NMOS transistor NM 2; the parameters of the first NMOS tube NM1, the sixth resistor R6, the seventh resistor R7, the second NMOS tube NM2, the eighth resistor R8 and the ninth resistor R9 are properly adjusted, so that the seventh PMOS tube PM7 and the eighth PMOS tube PM8 can be conducted and cannot be overpressurized.

At this time, the gate voltage of the first PMOS transistor PM1 is pulled to the input voltage VIN by the seventh PMOS transistor PM7, the gate voltage of the second PMOS transistor PM2 is pulled to the output voltage VOUT by the eighth PMOS transistor PM8, and VGS of both PMOS transistors is almost 0, so that a channel in which carriers flow cannot be formed. Meanwhile, the second parasitic diode D2 is in a reverse cut-off state, reverse current flowing through the substrate is blocked, so that detection of low voltage difference under a single power rail is completed, a reverse-flow prevention protection function is realized, and safety of the low-threshold PMOS tube LVT_PM3 is ensured.

It can be seen that, in the normal operating state, the input voltage VIN is higher than the output voltage VOUT, and the anti-reverse-filling protection function of the low voltage difference detection anti-reverse-filling protection circuit 100 is not triggered to be turned on. When the input voltage VIN is lower than the output voltage VOUT due to abnormal conditions such as power failure of the input voltage VIN, the anti-reverse-filling protection function of the low-voltage difference detection anti-reverse-filling protection circuit 100 is triggered to be started, the gate voltage of the first PMOS tube PM1 is pulled to the input voltage VIN, the gate voltage of the second PMOS tube PM2 is pulled to the output voltage VOUT, the first PMOS tube PM1 and the second PMOS tube PM2 are controlled to be turned off, and reverse filling of current from the channel of the MOS tube is blocked; meanwhile, the second parasitic diode D2 is in a reverse cut-off state, and current is blocked from reversely filling the substrate of the MOS tube. In addition, the third PMOS tube lvt_pm3 with a low threshold can only work within 5V, so that a series of clamping protection is performed on the third PMOS tube lvt_pm3 to prevent the third PMOS tube lvt_pm3 from being disabled due to overvoltage.

Example two

As shown in fig. 2, the present embodiment provides a load switch chip 10 including: a low-dropout detection anti-reverse-filling protection circuit 100; further, the method further comprises the following steps: the control circuit 200, the overcurrent protection circuit 300, and the thermal shutdown circuit 400 are started. Wherein,,

the low-voltage difference detection anti-reverse-filling protection circuit 100 is implemented by adopting the circuit structure described in the first embodiment, and the related content can be seen in the first embodiment, which is not repeated.

The start control circuit 200 is configured to generate a first gate control signal VGH and a second gate control signal VGL after the chip is started to control the first PMOS tube PM1 and the second PMOS tube PM2 to be turned on.

Further, the load switch chip 10 further includes: an enable control circuit 500 connected to the start control circuit 200 for turning on the chip when the input enable signal is greater than the first set value and turning off the chip when the input enable signal is less than the second set value; wherein the first set point is greater than the second set point. For example, the chip is turned on when the voltage value of the input enable signal is greater than 0.36 vin, and the chip is turned off when the voltage value of the input enable signal is less than 0.16 vin.

The overcurrent protection circuit 300 is connected between the low-voltage difference detection anti-reverse-filling protection circuit 100 and the starting control circuit 200, and is used for sampling the current flowing through the first PMOS tube PM1 and the second PMOS tube PM2 to obtain a sampling current, and generating an overcurrent protection signal when the sampling current is larger than the reference current IREF; the start control circuit 200 controls the first PMOS PM1 and the second PMOS PM2 to turn off according to the overcurrent protection signal, so as to realize the function of starting the overcurrent protection when the current of the MOS device is too high, and prevent the load switch chip from being damaged.

Specifically, the overcurrent protection circuit 300 includes: a current sampling unit and a comparison unit; the current sampling unit samples the current flowing through the branch where the first PMOS tube PM1 and the second PMOS tube PM2 are located to obtain sampling current, the comparison unit is connected with the output end of the current sampling unit, compares the sampling current with the reference current, and generates an overcurrent protection signal when the sampling current is larger than the reference current. In a possible embodiment, the current sampling unit is implemented as a current mirror and the comparison unit is implemented as a comparator.

Further, the load switch chip 10 further includes: reference circuit 600 is used to provide a reference current IREF. Specifically, the reference circuit 600 includes: a reference module 610 and an operational amplifier module 620; the reference module 610 is configured to provide a reference voltage VREF, and the operational amplifier module 620 is connected to an output terminal of the reference module 610 and is configured to convert the reference voltage VREF into a reference current IREF.

The thermal shutdown circuit 400 is connected with the start control circuit 200, and is used for sampling the temperature of the chip to obtain a sampling temperature and generating an over-temperature protection signal when the sampling temperature is greater than a set temperature; the start control circuit 200 controls the first PMOS PM1 and the second PMOS PM2 to turn off according to the over-temperature protection signal, so as to realize the over-temperature protection function when the chip temperature is too high, and prevent the chip from being burned out.

The load switch chip 10 including the low-voltage difference detection anti-reverse-filling protection circuit 100 described in the embodiment is subjected to flow sheet to obtain a corresponding chip; in combination with possible use scenarios of the load switch chip 10, the load switch chip 10 is actually measured under different conditions by using a semiconductor power device analyzer to verify the current reverse-filling prevention capability of the load switch chip 10.

Condition 1: the chip input voltage VIN is pulled down to the reference ground; where vin=0v, vout=1.5V-12V.

Condition 2: the chip input voltage VIN is in a high impedance state after being cut off; wherein VIN is suspended, vout=1.5v-12V.

Condition 3: the chip input voltage VIN is in a low impedance state after failure, and the later-stage voltage still exists; where vin=0v-7v and vout=vin-12V.

The actual measurement result of the load switch chip 10 under the condition 1 is shown in fig. 3, and it can be seen from the graph that the maximum reverse current under the condition is 1.23mA; the actual measurement result under condition 2 is shown in FIG. 4, and it can be seen from the graph that the maximum reverse current under the condition is 1.19mA; as shown in fig. 5, the measured result under condition 3, in which the maximum reverse current is 984 μa, is taken as an example, in which vin=5v and vout=5v-12V, because the value of the input voltage VIN does not affect the test result of the reverse current protection.

From the above three actual measurement results, the low voltage difference detection anti-reverse-filling protection circuit 100 in the load switch chip 10 of the embodiment can trigger the anti-reverse-filling protection function to be started when the voltage difference value between the output voltage VOUT and the input voltage VIN reaches 300mV under the single power supply, and the 300mV voltage difference detection is far smaller than the prior art.

Example III

As shown in fig. 6, the present embodiment provides a power supply system including: at least one load switch chip 10, at least one power source 20 and a load 30, the power source 20 being connected to the load 30 via the load switch chip 10; wherein,,

the load switch chip 10 performs anti-reverse irrigation protection on the power supply 20; the load switch chip 10 is implemented by adopting a chip structure as described in the second embodiment, and details of the related content can be found in the second embodiment, which is not described in detail.

The power supply 20 supplies power to the load 30; the output terminal of the power supply 20 is also typically connected to a capacitor (e.g., C1, C2), which is connected between the output terminal of the power supply 20 and the reference ground.

The load 30 is any electrical device commonly used in the prior art, and this embodiment is not limited thereto.

In practical applications, the power supply system of the present embodiment is usually a power supply redundancy system, that is, includes a plurality of power supplies 20 and corresponding load switch chips 10. Taking the example that the power redundancy system includes two power supplies (i.e., power supply 1 and power supply 2) and two load switch chips (i.e., load switch chip 1 and load switch chip 2):

when the power supply 1 and the power supply 2 are normal, the power supply 1 supplies power to a load through the load switch chip 1 and the power supply 2 supplies power to the load through the load switch chip 2;

when the power supply 1 is abnormal, the power supply 2 supplies power to the load through the load switch chip 2, at the moment, the voltage of the output end of the load switch chip 1 is higher than the voltage of the input end, and the reverse-filling protection circuit 100 is used for preventing the power supply 1 from being subjected to reverse-filling protection through the low-voltage difference detection in the load switch chip 1, so that the power supply 1 is prevented from being damaged due to reverse-filling current.

In summary, the low-voltage difference detection anti-reverse-filling protection circuit, the load switch chip and the power supply system provided by the invention have the advantages that the low-voltage difference detection circuit under a single power supply rail is designed by using the PMOS tube with a low threshold value in the CMOS process, the anti-reverse-filling protection function can be triggered and started based on the minimum output-input voltage difference value, and the reverse voltage detection sensitivity is improved; meanwhile, even if the input is powered down to very low voltage, the output-input differential pressure value can be normally detected, so that the reverse voltage can be detected and the reverse-filling prevention protection function can be triggered to be started during extremely low input without providing an extra power supply, thereby being beneficial to widening application conditions and widening application range. In addition, the PMOS tube with a low threshold value is subjected to clamping protection, so that damage caused by overvoltage is avoided, and the reliability of the circuit is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (13)

1. The utility model provides a low pressure differential detects and prevents reverse filling protection circuit which characterized in that, low pressure differential detects prevents reverse filling protection circuit includes: the device comprises a first PMOS tube, a second PMOS tube, a pressure difference detection module and a protection control module;

the first PMOS tube and the second PMOS tube are connected in series between the input voltage and the output voltage;

the voltage difference detection module performs low voltage difference detection on the output voltage and the input voltage based on a third PMOS tube with a low threshold value, and triggers the protection control module to turn off the first PMOS tube and the second PMOS tube to prevent current reverse charging and simultaneously performs voltage clamping on the third PMOS tube when the output voltage is larger than the input voltage and the voltage difference value between the output voltage and the input voltage is larger than the absolute value of the threshold voltage of the third PMOS tube.

2. The low-dropout detection anti-reverse-filling protection circuit according to claim 1, wherein the dropout detection module includes: the third PMOS tube, the first clamping unit and the second clamping unit;

the grid electrode of the third PMOS tube is connected with the output end of the first clamping unit, the source electrode of the third PMOS tube is connected with the substrate of the third PMOS tube and the output voltage of the third PMOS tube is connected with the substrate of the third PMOS tube, and the third PMOS tube is used for conducting when the differential pressure value is larger than the absolute value of the threshold voltage of the third PMOS tube;

the first clamping unit is connected between the input voltage and the output voltage and used for clamping the gate-source voltage of the third PMOS tube;

the second clamping unit is connected with the drain electrode of the third PMOS tube and used for clamping the drain voltage of the third PMOS tube and providing bias voltage for the protection control module.

3. The low dropout detection anti-reverse-filling protection circuit according to claim 2, wherein the first clamping unit includes: the first resistor, the second resistor and the first triode;

the first end of the first resistor is connected with the input voltage, and the second end of the first resistor is connected with the first end of the second resistor and the grid electrode of the third PMOS tube; the second end of the second resistor is connected with the emitter of the first triode; the base electrode of the first triode is connected with the collector electrode of the first triode and is connected with the output voltage.

4. The low dropout detection anti-reverse-filling protection circuit according to claim 2, wherein the second clamping unit includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third resistor, a fourth resistor and a fifth resistor;

the fourth PMOS tube and the fifth PMOS tube are connected in series between the output voltage and the reference ground by adopting a diode connection method and the third resistor; the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the sixth PMOS tube is connected with the substrate of the sixth PMOS tube and the drain electrode of the sixth PMOS tube is connected with the first end of the fourth resistor; the second end of the fourth resistor is connected with the reference ground through the fifth resistor and generates the bias voltage.

5. The low dropout detection anti-reverse-filling protection circuit according to claim 1, wherein said protection control module includes: a first protection unit and a second protection unit;

after the first protection unit is triggered, the first PMOS tube is turned off by pulling the grid voltage of the first PMOS tube to the input voltage;

and after the second protection unit is triggered, the second PMOS tube is turned off by pulling the grid voltage of the second PMOS tube to the output voltage.

6. The low dropout detection anti-reverse-filling protection circuit according to claim 5, wherein said first protection unit includes: the first NMOS tube, the sixth resistor, the seventh resistor and the seventh PMOS tube;

the grid electrode of the first NMOS tube is connected with bias voltage, the source electrode of the first NMOS tube is connected with the substrate of the first NMOS tube and is connected with the reference ground, and the drain electrode of the first NMOS tube is connected with the first end of the sixth resistor; the second end of the sixth resistor is connected with the input voltage through the seventh resistor and is connected with the grid electrode of the seventh PMOS tube; and the source electrode of the seventh PMOS tube is connected with the substrate of the seventh PMOS tube and the input voltage, and the drain electrode of the seventh PMOS tube is connected with the grid electrode of the first PMOS tube.

7. The low dropout detection anti-reverse-filling protection circuit according to claim 5, wherein said second protection unit includes: the second NMOS tube, the eighth resistor, the ninth resistor and the eighth PMOS tube;

the grid electrode of the second NMOS tube is connected with bias voltage, the source electrode of the second NMOS tube is connected with the substrate of the second NMOS tube and is connected with the reference ground, and the drain electrode of the second NMOS tube is connected with the first end of the eighth resistor; the second end of the eighth resistor is connected with the output voltage through the ninth resistor and is connected with the grid electrode of the eighth PMOS tube; and the source electrode of the eighth PMOS tube is connected with the substrate of the eighth PMOS tube and the output voltage, and the drain electrode of the eighth PMOS tube is connected with the grid electrode of the second PMOS tube.

8. The low-dropout detection anti-reverse-filling protection circuit according to claim 1, wherein a gate of the first PMOS transistor is connected to a first gate control signal, a source is connected to a substrate thereof and to the input voltage, and a drain is connected to a drain of the second PMOS transistor; and the grid electrode of the second PMOS tube is connected with a second grid control signal, and the source electrode of the second PMOS tube is connected with the substrate of the second PMOS tube and is connected with the output voltage.

9. A load switch chip, the load switch chip comprising: the low dropout detection anti-reverse-filling protection circuit according to any one of claims 1 to 8.

10. The load switch chip of claim 9, wherein the load switch chip further comprises: a start control circuit, an overcurrent protection circuit and a thermal shutdown circuit;

the starting control circuit is used for generating a first grid control signal and a second grid control signal after the chip is started to control the first PMOS tube and the second PMOS tube to be conducted;

the overcurrent protection circuit is connected between the low-voltage difference detection anti-reverse-filling protection circuit and the starting control circuit, and is used for sampling the current flowing through the first PMOS tube and the second PMOS tube to obtain a sampling current, and generating an overcurrent protection signal when the sampling current is larger than a reference current;

the thermal shutdown circuit is connected with the starting control circuit and is used for sampling the temperature of the chip to obtain a sampling temperature and generating an over-temperature protection signal when the sampling temperature is greater than a set temperature;

and the starting control circuit also controls the first PMOS tube and the second PMOS tube to be turned off according to the overcurrent protection signal and/or the overtemperature protection signal.

11. The load switch chip of claim 10, wherein the load switch chip further comprises: the enabling control circuit is connected with the starting control circuit and is used for starting the chip when the input enabling signal is larger than a first set value and closing the chip when the input enabling signal is smaller than a second set value; wherein the first set value is greater than the second set value.

12. The load switch chip of claim 10, wherein the load switch chip further comprises: a reference circuit for providing the reference current; wherein the reference circuit includes: the reference module is used for providing reference voltage, and the operational amplifier module is connected with the output end of the reference module and used for converting the reference voltage into the reference current.

13. A power supply system, the power supply system comprising: at least one load switch chip according to any of claims 9-12, at least one power supply and a load;

the power supply is connected to the load through the load switch chip, wherein the power supply supplies power to the load, and the load switch chip performs anti-reverse irrigation protection on the power supply.