CN109831020B - Reverse flow preventing circuit for ultralow-loss two-path power supply switching - Google Patents
Reverse flow preventing circuit for ultralow-loss two-path power supply switching Download PDFInfo
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- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 4
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Abstract
The invention discloses an ultralow-loss two-path power supply switching anti-backflow circuit which comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first path of power supply and a second path of power supply, wherein the first PMOS tube is connected with the second PMOS tube back to back, the first PMOS tube is connected with the first path of power supply, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube through a second pull-up resistor and is grounded through a first bias resistor, the third PMOS tube is connected with the fourth PMOS tube back to back, the third PMOS tube is connected with the second path of power supply, and the grid electrode of the third PMOS tube is connected with the first path of power supply through the first pull-up resistor and is grounded through a second bias resistor; the ultra-low loss two-way power supply switching anti-backflow circuit has the functions of two-way power supply seamless switching and anti-backflow, and protects a front-stage circuit; the low-loss low-voltage power supply has the advantages that the loss is very low, the quiescent current loss can be lower than microampere level, two groups of PMOS (P-channel metal oxide semiconductor) tubes are in back-to-back butt joint, the circuit is simple, the cost is low, and the practicability is high.
Description
Technical Field
The invention relates to the technical field of backflow prevention of a two-way power supply switching circuit, in particular to an ultralow-loss two-way power supply switching backflow prevention circuit.
Background
At present, a plurality of devices use a main power supply and an auxiliary power supply, such as a battery, a charger or a power adapter and the like for a mobile phone: when no external power supply is used, the self-charging battery is used for supplying power, and the load is automatically disconnected from the battery. When the auxiliary power supply is connected, such as a charger or a power adapter, the external power supply is preferably used. The application of the main power supply or other auxiliary power supplies needs a power supply switching circuit, selects between the main power supply and the auxiliary power supply, ensures that the power efficiency is optimal, reduces the power consumption, prolongs the working time of a battery, and particularly has the advantages of reverse flow prevention and front-stage circuit protection.
Dual diode scheme: the two diodes are respectively connected in series with the main power supply and the auxiliary power supply, the circuit is simple, the logic OR function is easy to realize, the selection between the main power supply and the auxiliary power supply can be realized, the power supply is used with high priority, and the defect is that the diodes have about 0.6V voltage drop, and the voltage drop can be along with the power loss of the input current in proportion. As the current increases, the voltage drop also increases, for example, the schottky diode is used for replacing the power, but the power loss is still relatively large: the larger the passing current, the larger the loss. The schottky diode has the disadvantage that reverse current exists when reverse voltage exceeds a threshold value, and the reverse overvoltage does not have the function of preventing reverse current, so that static current is generally in the milliamp level.
Diode + PMOS tube scheme: according to the invention (a multi-input power supply switching circuit, application number: CN 201410700845.1), a Schottky diode is connected in series on Vbus, a PMOS tube is used for controlling and supplying power to a battery Vbat, the voltage drop loss of the diode is large, and the loss is very reduced by using a MOS tube scheme, which is about one tenth of the loss of the Schottky diode.
Triode+pmos/NMOS scheme: for example, the invention patent (power switching and compensating device and method, application number: CN 200410039550.0) uses triode to control PMOS/NMOS tube to supply power to equipment, wherein one path also needs to add additional third high-voltage power control NMOS tube, and obviously the bias resistance of triode is kiloohm level, its quiescent current milliamp level. The disadvantage is that the quiescent operating current of the triode is in the class of milliamperes, the current loss is very large, and the third high voltage power supply which is needed to be used is liable to increase the cost.
Ideal diode scheme: using chip LTC4412, an external P-channel MOSFET is controlled for power switching near ideal diode function. The voltage drop across the MOSFET when turned on is typically 20mV. The gate driver includes an internal voltage clamp for MOSFET protection. When an auxiliary power supply is detected, the STAT pin may be used to enable an auxiliary P-channel MOSFET power switch. The pin may also be used to signal an indication to the microcontroller when an auxiliary power source is connected. A Control (CTL) input enables the user to force the main MOSFET off and put the STAT pin low. The typical value of the static current is 11 mu A, which is irrelevant to the load current, the circuit is very simple, the number of peripheral devices is very small, the device has the function of preventing backflow, and the chip price is relatively high, and the current price is 5-10 yuan per chip. Manufacturing a PCB according to the schematic diagram of page 9 of a chip manual and FIG. 2, testing after welding a patch by using a PMOS tube AO3401A with a resistance value of 500k ohms, wherein the static current is 13.6 mu A only when the lithium battery is powered by 3.78V (without load), and the input-output differential pressure is 17mV; when the independent external power is supplied with 4.2V, the static current is 19.8 mu A, if the battery measurement is connected, the auxiliary PMOS tube (VGS= -0.09V > VGS (th) = -0.7V, in the state of being ready to enter the conducting state, the current should be 0V in the strict sense) is found to have 0.1 mu A backward current flowing to the lithium battery; when a load exists (load current 1A), 0.1 mu A of backward current flows to the lithium battery, and the auxiliary PMOS tube (VGS= -0.0959V) indicates that the internal controller of the LTC4412 cannot be absolutely closed (cut off) by the external PMOS tube or weak backward current exists.
Load (combination) switch+pmos tube scheme: the invention relates to an NMOS+PMOS load switch circuit (an ultralow-loss two-way power supply switching anti-backflow circuit, application number: CN 201810920908.2), which consists of 4 PMOS tubes, 2 NMOS tubes and 10 resistors. The two-way power supply switching circuit belongs to a symmetrical circuit, and adopts one path of NMOS and PMOS load switch to control the PMOS tube of the other path of power supply path; the other path of NMOS and PMOS load switch is used for controlling the PMOS tube of one path of power supply path, the two paths of power supply switching has priority, the power supply with high voltage is preferentially used, the two paths of power supplies are provided with anti-backflow functions, the power supply pre-stage circuit is protected, the static loss is microampere, the circuit is simple, the cost is low, the practicability is strong, and the like, but more discrete components are also used.
Therefore, for the above-described problem of two-way power switching, fewer discrete components are used, and it is necessary to provide an ultra-low loss two-way power switching anti-backflow circuit.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, uses fewer discrete components on the basis of not increasing loss, and provides an ultralow-loss two-path power supply switching anti-backflow circuit.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
An ultralow-loss two-path power supply switching anti-backflow circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a pull-up resistor, a bias resistor, a first path of power supply and a second path of power supply, wherein the pull-up resistor comprises a first pull-up resistor and a second pull-up resistor, and the bias resistor comprises a first bias resistor and a second bias resistor;
The source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube back to back, the drain electrode of the first PMOS tube is connected with a first path of power supply, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and is connected with a second path of power supply through a second pull-up resistor and is grounded through a first bias resistor;
the source electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube back to back, the drain electrode of the third PMOS tube is connected with the second path of power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with the first path of power supply through a first pull-up resistor and is grounded through a second bias resistor;
and the drain electrode of the second PMOS tube is connected with the drain electrode of the fourth PMOS tube and outputs the drain electrode.
In order to further realize the invention, the resistance of the bias resistor is at least two orders of magnitude greater than the resistance of the pull-up resistor.
In order to further realize the invention, the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube use PMOS tubes with the same model.
In order to further realize the invention, the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube all use PMOS tubes with model AO 3401A.
In order to further realize the invention, the first power supply and the second power supply are both direct current power supplies.
An ultralow-loss two-path power supply switching anti-backflow circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a pull-up resistor, a bias resistor, a first path of power supply and a second path of power supply, wherein the pull-up resistor comprises a first pull-up resistor and a second pull-up resistor, and the bias resistor comprises a first bias resistor and a second bias resistor;
the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube back to back, the source electrode of the first PMOS tube is connected with a first path of power supply, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and is connected with a second path of power supply through a second pull-up resistor and is grounded through a first bias resistor;
the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube back to back, the source electrode of the third PMOS tube is connected with the second path of power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with the first path of power supply through a first pull-up resistor and is grounded through a second bias resistor;
And the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube and outputs the second PMOS tube.
Advantageous effects
The two-way power supply switching circuit belongs to a symmetrical circuit, two paths of power supplies are mutually controlled, the voltage is high and is output preferentially, the power supplies are switched seamlessly, and the two paths of power supplies have the backflow prevention function, so that a pre-stage circuit can be protected; the low-loss low-voltage power supply has the advantages that the loss is very low, the quiescent current loss can be lower than microampere level, two groups of PMOS (P-channel metal oxide semiconductor) tubes are in back-to-back butt joint, the circuit is simple, the cost is very low, and the practicability is high; compared with the patent of the invention (an ultralow-loss double-circuit power supply switching anti-backflow circuit with the application number of CN 201810920908.2), the device has the advantages that 2 NMOS (N-channel metal oxide semiconductor) tubes and 6 resistors are fewer, the cost is further reduced, and the circuit loss is similar.
Drawings
FIG. 1 is a schematic diagram of a first embodiment of the present invention;
fig. 2 is a schematic diagram of a second embodiment of the present invention.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings, which are simplified schematic illustrations of the basic structure of the invention, which are only schematically illustrated.
Example 1
As shown in FIG. 1, the ultra-low loss two-path power supply switching anti-backflow circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube (V1), a second PMOS tube (V2), a third PMOS tube (V3), a fourth PMOS tube (V4), a pull-up resistor, a bias resistor, a first path of power supply (Vin 1) and a second path of power supply (Vin 2), wherein:
the pull-up resistor comprises a first pull-up resistor (R1) and a second pull-up resistor (R2), and the bias resistor comprises a first bias resistor (R3) and a second bias resistor (R4).
The source electrode of the first PMOS tube (V1) is connected with the source electrode of the second PMOS tube (V2) back to back, the drain electrode of the first PMOS tube (V1) is connected with the first path of power supply (Vin 1), the grid electrode of the first PMOS tube (V1) is connected with the grid electrode of the second PMOS tube (V2) and is connected with the second path of power supply (Vin 2) through a second pull-up resistor (R2) and is grounded through a first bias resistor (R3), the source electrode of the third PMOS tube (V3) is connected with the source electrode of the fourth PMOS tube (V4) back to back, the drain electrode of the third PMOS tube (V3) is connected with the second path of power supply (Vin 2), the grid electrode of the third PMOS tube (V3) is connected with the grid electrode of the fourth PMOS tube (V4) and is connected with the first path of power supply (Vin 1) through the first pull-up resistor (R1) and is grounded through the second bias resistor (R4), and the drain electrode of the second PMOS tube (V2) is connected with the drain electrode of the fourth PMOS tube (V4) and outputs Vout (12).
And the sizes of the pull-up resistor and the bias resistor are adjusted according to different loss requirements, the resistance value of the bias resistor is at least two orders of magnitude larger than that of the pull-up resistor, and the power consumption requirement is met.
The first power supply and the second power supply are both direct current power supplies, the power supply difference is larger than the absolute value |VGS (th) | of the conduction threshold voltage of the PMOS tube, and the PMOS tube with low threshold conduction voltage is preferably selected on the premise of meeting load current.
The static power consumption of the circuit is very low: because the insulating film is arranged between the grid electrode and the source electrode (channel) of the PMOS, the grid electrode and the source electrode are insulated, the input impedance resistance of the grid electrode and the source electrode is about 10 12～1014 Ω, the bias resistance of the grid electrode of the PMOS can reach hundreds of MΩ, and the current loss can be lower than microampere level according to the bias resistance of the grid electrode.
The P-channel MOS tubes with the same type can be used for the 4 PMOS tubes (V1-V4), the conducting current is determined according to the circuit requirement, the PMOS tubes can be in back-to-back butt joint, the pair tubes have the same parameters, and the symmetrical double-P-channel MOS pair tubes can ensure that the parameter consistency is maintained as much as possible when the temperature changes, and the reliability of the circuit is improved. The combined logic control circuit has the functions of seamless switching of a two-way power supply and backflow prevention.
The PMOS tube can select a power tube device with the on-resistance of several milliohms between a grid electrode (D electrode) and a source electrode (S electrode), and can also use a plurality of PMOS tubes to be connected in parallel to further reduce the on-resistance and reduce the power consumption. After the voltages of the two paths of power supplies are selected and compared, different levels are output to control one path of the two paths of back-to-back butt joint PMOS (P-channel metal oxide semiconductor) tubes to be turned on and the other path of the PMOS tubes to be turned off, and as the PMOS tubes belong to voltage devices, the current of the PMOS tubes is very small when the PMOS tubes are turned on and off, the current can be ignored, and only very small current (microampere level) is lost when the PMOS tubes are turned on. The PMOS tube with the on-resistance of several milliohms between the D pole and the S pole is selected, and the voltage drop through the PMOS tube is very small and can be similar to an ideal power diode.
The circuit is adopted to carry out PCB design and processing patch welding, the PMOS tubes are all AO3401A, and the models of other components are shown in figure 1.
A single-pass power static (no load) test was performed and the results are shown in table 1:
table 1 figure 1 circuit single-pass power static test
As can be seen from table 1, when using the lithium battery with vjn1= 4.093V for power supply, r3=r4=10mΩ, and the quiescent power consumption current consumption is 4.0 μa; r3=r4=1mΩ, the quiescent power consumption current consumption is 0.39 μa, the voltage of the other power interface Vin2 is 0, and no reverse current exists.
Two-way power static test (no load) was performed as shown in table 2:
Table 2 two-way power static test for the circuit of fig. 1
As shown in table 2, the sum of the static power consumption and the current consumption is 9.8 μa, vgs=0.24v of the PMOS transistor V1 (V2), and the power supply interface Vin1 is in the off state without the reverse current. If the bias resistors R3 and R4 between the grid bias resistors of the PMOS tube are welded with larger resistance values, the loss current is smaller.
Based on the test of table 2, vout12 was connected to a load of 6Ω impedance to obtain the test results shown in table 3:
Table 3 fig. 1 circuit load test
As can be seen from table 3, when two power supplies exist, the high voltage interface Vin2 outputs preferentially, and the low voltage interface Vin1 has a bias current but no reverse current.
Example two
As shown in fig. 2, unlike the first embodiment, the drain of the first PMOS transistor (V1) is connected back-to-back to the drain of the second PMOS transistor (V2), the source of the first PMOS transistor (V1) is connected to the first power supply (Vin 1), the drain of the third PMOS transistor (V3) is connected back-to-back to the drain of the fourth PMOS transistor (V4), the source of the third PMOS transistor (V3) is connected to the second power supply (Vin 2), the drain of the second PMOS transistor (V2) is connected to the source of the fourth PMOS transistor (V4) and outputs (Vout 12), and the rest is the same as the first embodiment.
After PCB design and processing patch welding are carried out by adopting the circuit of the invention, static (no-load) test is carried out (the model of the component is shown in figure 2): the PMOS tube is selected from AO3401A. The test results show that: the circuit of fig. 2 is not different from that of fig. 1.
The above description is merely of a preferred embodiment of the present invention, the present invention is not limited to the above embodiment, and minor structural modifications may exist in the implementation process, and if various modifications or variations of the present invention do not depart from the spirit and scope of the present invention and fall within the scope of the appended claims and the equivalent technology, the present invention is also intended to include such modifications and variations.
Claims (4)
1. The ultra-low loss two-path power supply switching anti-backflow circuit is characterized by comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a pull-up resistor, a bias resistor, a first path of power supply and a second path of power supply, wherein the pull-up resistor comprises a first pull-up resistor and a second pull-up resistor, and the bias resistor comprises a first bias resistor and a second bias resistor;
The source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube back to back, the drain electrode of the first PMOS tube is connected with a first path of power supply, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and is connected with a second path of power supply through a second pull-up resistor and is grounded through a first bias resistor;
the source electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube back to back, the drain electrode of the third PMOS tube is connected with the second path of power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with the first path of power supply through a first pull-up resistor and is grounded through a second bias resistor;
The drain electrode of the second PMOS tube is connected with the drain electrode of the fourth PMOS tube and outputs the drain electrode;
the resistance value of the bias resistor is at least two orders of magnitude larger than that of the pull-up resistor;
the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube use PMOS tubes with the same model.
2. The ultra-low loss two-way power switching anti-backflow circuit of claim 1, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are PMOS transistors with model AO 3401A.
3. The ultra-low loss two-way power switching anti-backflow circuit of claim 1, wherein the first and second power sources are both dc power sources.
4. The ultra-low loss two-path power supply switching anti-backflow circuit is characterized by comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a pull-up resistor, a bias resistor, a first path of power supply and a second path of power supply, wherein the pull-up resistor comprises a first pull-up resistor and a second pull-up resistor, and the bias resistor comprises a first bias resistor and a second bias resistor;
the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube back to back, the source electrode of the first PMOS tube is connected with a first path of power supply, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and is connected with a second path of power supply through a second pull-up resistor and is grounded through a first bias resistor;
the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube back to back, the source electrode of the third PMOS tube is connected with the second path of power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with the first path of power supply through a first pull-up resistor and is grounded through a second bias resistor;
the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube and outputs the drain electrode of the second PMOS tube;
the resistance value of the bias resistor is at least two orders of magnitude larger than that of the pull-up resistor;
the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube use PMOS tubes with the same model.
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| CN201910126088.4A CN109831020B (en) | 2019-02-20 | 2019-02-20 | Reverse flow preventing circuit for ultralow-loss two-path power supply switching |
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| CN111987710B (en) * | 2020-08-11 | 2022-11-15 | 深圳市嘉润原新显科技有限公司 | Low-power consumption anti-backflow circuit and multi-input power supply device |
| CN112448473B (en) * | 2021-02-01 | 2021-04-30 | 上海灵动微电子股份有限公司 | Circuit and method for protecting backup domain data |
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| CN209375240U (en) * | 2019-02-20 | 2019-09-10 | 广州奥格智能科技有限公司 | A kind of ultra-low loss two-way power supply switching anti-back flow circuit |
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2019
- 2019-02-20 CN CN201910126088.4A patent/CN109831020B/en active Active
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| CN2596670Y (en) * | 2002-12-17 | 2003-12-31 | 上海贝岭股份有限公司 | Two-way power automatic switching circuit on sheet |
| WO2013078848A1 (en) * | 2011-11-29 | 2013-06-06 | 中兴通讯股份有限公司 | Terminal charging protection circuit |
| CN104022647A (en) * | 2014-06-25 | 2014-09-03 | 上海协霖电子有限公司 | Self-switching voltage stabilizing circuit of power supply |
| CN204721079U (en) * | 2015-04-20 | 2015-10-21 | 北京航天自动控制研究所 | Dual-power automatic switching and charging circuit |
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