CN109871060B - Linear voltage regulator circuit - Google Patents
Linear voltage regulator circuit Download PDFInfo
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- CN109871060B CN109871060B CN201910144744.3A CN201910144744A CN109871060B CN 109871060 B CN109871060 B CN 109871060B CN 201910144744 A CN201910144744 A CN 201910144744A CN 109871060 B CN109871060 B CN 109871060B
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Abstract
The present invention provides a linear regulator circuit, including: a main drive voltage stabilizer circuit and a low voltage drive circuit; the low-voltage driving circuit consists of a power supply sampling module, a comparator, a phase inverter and a second PMOS (P-channel metal oxide semiconductor) tube; the input end of the power supply sampling module is connected with power supply voltage; the input end of the comparator is connected with the power sampling module, and the input end of the comparator is connected with an input reference voltage; the inverter is connected with the comparator; the phase inverter is connected with the grid electrode of the second PMOS tube; the source electrode of the second PMOS tube is connected with power voltage; the drain electrode of the second PMOS tube and the source electrode of the NMOS driving device are jointly used as output end voltage. The linear voltage regulator circuit used by switching the N-type intrinsic transistor and the P-type transistor is used, the threshold voltage for switching the N-type transistor and the P-type transistor is reasonably selected, so that the smooth transition of conduction of the N-type transistor and the P-type transistor is realized, and the circuit can meet the application requirement of a wide power supply voltage range.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a linear regulator circuit.
Background
The conventional linear regulator circuit can use a PMOS transistor or an NMOS transistor as a driver, as shown in fig. 1, and fig. 1 shows a linear regulator circuit using a conventional PMOS transistor as a driver. The conventional linear voltage regulator circuit with the PMOS tube as the driving device comprises three PMOS tubes: PM0 pipe, PM1 pipe and Mpass pipe as the drive device, this linear regulator circuit still includes: the transistor comprises four NMOS (NM0, NM1, NMirr0, NMirr 1) tubes, three resistors (R0, Rc and R1) and a capacitor Cc, wherein the source of the PMOS tube of the driving device is connected with a power supply voltage VCC, the drain of the PMOS tube is an output end V _ LDO, the gate of the PM0 tube is connected with the gate of the PM1 and the drain thereof at a common node PB, the drain of the PM0 tube, the gate of the Mpas tube and one end of the resistor RC at a common node PG, the gate of the NM1 tube, one end of the resistor R0 and one end of the resistor R1 at a common node VFD, the gate and the drain of the NMirr0 tube are connected with the gate of the NMirr1 tube at a common node NB, and the node NB is connected with an input bias current source IB., the other end of the resistor R0, the source of the NMirr1 tube and the source of the NMirr.
When the traditional PMOS tube is used as a driving device, low-voltage application can be supported, but output voltage can overshoot when the power supply is quickly powered on (namely, the power supply is quickly powered on to a required working voltage VCC in a nanosecond level), a node PG is charged from a low level in the process of establishing a working point, and an Mpass tube can be conducted with large current to flush an output end V _ LDO of the LDO to a higher level, so that an overshoot phenomenon is generated. Meanwhile, when the traditional PMOS tube is used as a driving device, the power supply rejection capability of the output voltage of the traditional PMOS tube is not easy to design.
Fig. 2 shows a linear regulator circuit with an NMOS transistor as a driver device. An NMOS (N-channel metal oxide semiconductor) tube Mpass tube in the linear voltage regulator circuit with the NMOS tube as a driving device is used as the driving device, the source electrode of a PM0 tube is connected to the power supply voltage end, and the grid electrode of the PM0 tube is connected with the grid electrode of a PM1 tube and the drain electrode of an NM0 tube; the grid electrode of the NMOS tube Mpass tube of the driving device, the upper plate electrode of the capacitor Cc, the drain electrode of the PM1 tube and the drain electrode of the NM1 tube are connected with a node NG in common.
When the NMOS tube is used as a driving device, the power-on can not overshoot, and the power supply restraining capability of the output voltage can be improved, but the lowest value of the power supply voltage is higher, especially the application situation that the output voltage is higher than the power supply voltage, such as a standard CMOS process platform, the input voltage is 1.62V-5.5V, and the output voltage is required to be 1.6V-1.98V, the low-voltage application can not be supported.
Therefore, a new linear regulator circuit is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a linear regulator circuit, which is used to solve the problem that the NMOS transistor as the driving device in the prior art cannot support low voltage application due to the high minimum value of the power voltage.
To achieve the above and other related objects, the present invention provides a linear regulator circuit, comprising: a main drive voltage stabilizer circuit and a low voltage drive circuit; the main drive voltage stabilizer circuit is provided with a power supply voltage and an NMOS drive device; the power supply voltage is connected with the drain electrode of the NMOS driving device; the low-voltage driving circuit consists of a power supply sampling module, a comparator, an inverter and a second PMOS (P-channel metal oxide semiconductor) tube; the input end of the power supply sampling module is connected with the power supply voltage, and the output is sampling point voltage; the negative pin of the input end of the comparator is connected with the output end of the power supply sampling module, and the positive pin of the input end of the comparator is connected with an input reference voltage; the input end of the phase inverter is connected with the output end of the comparator; the output end of the phase inverter is connected with the grid electrode of the second PMOS tube; the source electrode of the second PMOS tube is connected with the power supply voltage of the main drive voltage stabilizer circuit; and the drain electrode of the second PMOS tube and the source electrode of the NMOS driving device are jointly used as output end voltage.
Preferably, the main drive voltage regulator circuit further includes a first PMOS transistor, a source of the first PMOS transistor is connected to the power supply voltage, and a drain of the first PMOS transistor is connected to a gate of the NMOS drive device.
Preferably, the main driving voltage regulator circuit further includes a P-type MOS transistor PM0 and four N-type MOS transistors: NM0 tube, NM1 tube, NMirr0 tube, NMirr1 tube; the main driving voltage regulator circuit also comprises a resistor R0, a resistor R1 and a capacitor Cc; the source electrode of the PM0 tube is connected to the power supply voltage end, and the grid electrode of the PM0 tube is connected with the grid electrode of the first PMOS tube and the drain electrode of the NM0 tube; the grid electrode of the NM0 tube is connected with an input reference voltage; the drain electrode of the first PMOS tube, the grid electrode of the NMOS driving device, the drain electrode of the NM1 tube and the upper plate of the capacitor Cc are connected with each other; the source electrode of the NM0 tube, the source electrode of the NM1 tube and the drain electrode of the NMirr1 tube are connected with each other; the grid and the drain of the NMirr0 tube and the grid of the NMirr1 tube are connected with a bias current source in common; one end of the resistor R1 and the source electrode of the NMOS driving device are used together as output end voltage; the other end of the resistor R1, the grid of the NM1 tube and one end of the resistor R0 are connected together; the lower plate of the capacitor Cc, the other end of the resistor R0, the source of the NMirr1 tube and the source of the NMirr0 tube are commonly grounded.
Preferably, under the condition of low-voltage application, the value of the power supply voltage is 1.62V to 5.5V, and the value of the output voltage is 1.6V to 1.98V.
Preferably, under the condition of low-voltage application, the power supply voltage is 1.62V, the output end voltage is 1.6V, and the driving current is 10 mA.
Preferably, the threshold voltage of the NMOS drive device is greater than 20mV under all conditions.
Preferably, the threshold voltage of the second PMOS transistor is less than 1.62V.
As described above, the linear regulator circuit of the present invention has the following advantageous effects: the linear voltage regulator circuit used by switching the N-type intrinsic transistor and the P-type transistor is used, the threshold voltage for switching the N-type transistor and the P-type transistor is reasonably selected, so that the smooth transition of conduction of the N-type transistor and the P-type transistor is realized, and the circuit can meet the application requirement of a wide power supply voltage range.
Drawings
FIG. 1 is a circuit diagram of a conventional linear regulator using PMOS transistors as the driving devices;
FIG. 2 is a circuit diagram of a prior art linear regulator using NMOS transistors as the driving devices;
FIG. 3 is a circuit diagram of the linear regulator according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 3, fig. 3 is a circuit diagram of the linear regulator of the present invention. The linear regulator circuit of the present embodiment includes: in fig. 3, the main driving voltage regulator circuit in the left half part and the low voltage driving circuit in the right half part are shown. The two circuits are connected to the source electrode of the NMOS driving device through the drain electrode of the second PMOS tube, and meanwhile, the source electrode of the second PMOS tube and the drain electrode of the NMOS driving device are connected to a power supply voltage VCC.
As shown in fig. 3, the main driving regulator circuit therein is provided with a power supply voltage VCC and an NMOS driving device Mpass tube, which is an N-type intrinsic transistor; the power supply voltage VCC is connected with a drain electrode of the Mpass tube of the NMOS driving device; when the NMOS drive device Mpass tube is used as a drive device of a linear voltage regulator circuit, an overshoot phenomenon (namely, the NMOS drive device Mpass tube is quickly electrified to a required working voltage VCC in a nanosecond level) cannot be generated when the NMOS drive device Mpass tube is electrified, and meanwhile, the power supply restraining capability of output voltage can be improved.
As shown in fig. 3, the low voltage driving circuit is composed of a power sampling module, a comparator CMP, an inverter INV0, and a second PMOS transistor PM 2; the input end of the power supply sampling module is connected with the power supply voltage VCC, and the output of the power supply sampling module is sampling point voltage Vdet; the negative pin of the input end of the comparator CMP is connected with the output end of the power supply sampling module, and the power supply sampling module transmits the sampling point voltage output by itself through sampling to the input end of the comparator CMP. The positive pin of the input end of the comparator CMP is connected with an input reference voltage VREF; the comparator can be viewed as an operational amplifier with a magnification approaching "infinity". The function of the comparator CMP: comparing the magnitudes of the two voltages (representing the magnitude relationship of the two input voltages by the high or low level of the output voltage): when the voltage at the + input terminal is higher than the voltage at the-input terminal, the output of the comparator CMP is at a high level; when the voltage at the "+" input terminal is lower than that at the "-" input terminal, the output of the voltage comparator is at low level.
The input end of the inverter INV0 is connected with the output end of the comparator CMP; the comparator outputs a high level or a low level selected by itself through comparison to the inverter INV0, for example, the comparator CMP outputs a high level, and outputs a low level after passing through the inverter INV 0; if the output of the comparator CMP is low, the output is high after passing through the inverter INV 0. The output end of the inverter INV0 is connected with the grid electrode of the second PMOS tube; that is to say, the sampling voltage output by the power sampling module is screened by the comparator CMP and then transmitted to the inverter, and the inverter takes the received voltage signal as the gate input voltage of the second PMOS transistor.
In fig. 3, the source of the second PMOS transistor PM2 is connected to the power supply voltage VCC of the main driving regulator circuit; and the drain electrode of the second PMOS tube and the source electrode of the NMOS drive device Mpass tube are jointly used as a voltage output end.
As shown in fig. 3, in the present embodiment, the main driving regulator circuit further includes a first PMOS transistor PM1, a source of the first PMOS transistor PM1 is connected to the power supply voltage VCC, and a drain of the first PMOS transistor PM1 is connected to a gate of the NMOS driving device Mpass.
Further, as shown in fig. 3, in this embodiment, the main drive regulator circuit further includes a P-type MOS transistor PM0 and four N-type MOS transistors: NM0 tube, NM1 tube, NMirr0 tube, NMirr1 tube; the main driving voltage regulator circuit also comprises a resistor R0, a resistor R1 and a capacitor Cc; the source electrode of the PM0 tube is connected to the power supply voltage end VCC, the grid electrode of the PM0 tube is connected with the grid electrode of the first PMOS tube PM1 and the drain electrode of the NM0 tube, and the two tubes share a node PB; the grid electrode of the NM0 tube is connected with an input reference voltage VREF; the drain electrode of the first PMOS tube, the grid electrode of the NMOS drive device Mpass, the drain electrode of the NM1 tube and the upper plate of the capacitor Cc are connected with each other and share a node NG; the source electrode of the NM0 tube, the source electrode of the NM1 tube and the drain electrode of the NMirr1 tube are connected with each other.
The gate and the drain of the NMirr0 tube and the gate of the NMirr1 tube in the main drive voltage regulator circuit share a node NB and are connected with a bias current source IB in common; one end of the resistor R1 is mutually connected with the source electrode of the NMOS driving device Mpass tube and the drain electrode of a second PMOS tube in the low-voltage driving circuit and is used as a voltage output end together; the other end of the resistor R1, the grid of the NM1 tube and one end of the resistor R0 are connected in common and share a node VFD; the lower plate of the capacitor Cc, the other end of the resistor R0, the source of the NMirr1 tube, and the source of the NMirr0 tube are commonly Grounded (GND).
The main driving voltage stabilizer circuit is a linear voltage stabilizer circuit which uses a traditional NMOS tube as a driving device, the lowest power supply voltage is the voltage VOUT and Vgs (voltage between grid sources of an Mpass tube) of the voltage output end and the voltage Vds (source drain voltage of a pm1 tube), the Mpass tube selects an N-type intrinsic transistor to be compatible with a standard CMOS (complementary metal oxide semiconductor) process, extra cost is not increased, when large pull current exists on the voltage VOUT of the output end, the voltage VOUT is pulled down, the grid source voltage of the N-type intrinsic transistor is increased, and instantaneous large current can be provided to meet the driving capability required by an external circuit, such as the read-write operation of a memory circuit. Meanwhile, the instantaneous large current is not provided by an output load capacitor any more, so that the area can be reduced, and the cost is reduced.
Under the condition of low-voltage application, the NMOS drive device Mpass of the main drive voltage regulator circuit is used as a switch, and in this embodiment, preferably, under the condition of low-voltage application, the value of the power supply voltage VCC is 1.62V to 5.5V, and the value of the output voltage VOUT is 1.6V to 1.98V. Further, under the condition of low-voltage application, the power supply voltage is 1.62V, the output end voltage is 1.6V, and the driving current is 10 mA. Furthermore, in the embodiment, under all conditions, the threshold voltage of the NMOS driver device is greater than 20mV, that is, the threshold voltage of the NMOS driver device is greater than 20mV under different process corners and different temperatures.
That is, when the input power voltage VCC is 1.62V and the output voltage VOUT is 1.6V, if a 10mA driving current is provided, it is difficult to turn on the intrinsic N-type transistor 20mV gate-source voltage under different process corners and different temperatures under all conditions to provide a sufficient driving current in consideration of the process and temperature effects.
As shown in fig. 3, the low voltage driving circuit in the right half mainly comprises a power sampling module, a comparator CMP, an inverter INV0, and the second PMOS transistor (P-type transistor driving device). When the voltage Vdet at the sampling point is greater than the input reference voltage VREF, the output of the comparator CMP is a low level, and then the output is output through the inverter INV0, the gate voltage of the PM2 transistor is a high level, for the PMOS transistor, the gate is connected with a low voltage, as long as the gate low voltage is less than the voltage of any one of the source and drain electrodes plus the threshold voltage of the PMOS transistor, the PMOS transistor is turned on, otherwise, the PMOS transistor is turned off. Therefore, when the power supply low voltage VCC is a low voltage, and the gate voltage output to the PM2 transistor through the inverter INV0 is a high level, the PM2 transistor is turned off.
Preferably, the threshold voltage of the second PMOS transistor of this embodiment is less than 1.62V.
When the voltage Vdet at the sampling point is less than the input reference voltage VREF, the output of the comparator CMP is a high level, and then the high level is output through the inverter INV0, the gate voltage of the PM2 transistor is a low level, and the PM2 transistor can be completely turned on when the input power voltage VCC is 1.62V, and when the PM2 is turned on, because the source of the PM2 transistor is connected to the power voltage VCC, the source voltage can be transmitted to the drain thereof, the power voltage VCC is transmitted to the output terminal, and the output terminal voltage VOUT is 1.62V.
Meanwhile, the source-drain voltage drop can meet the use requirement by adjusting the width-to-length ratio of the PM2 tube.
In summary, the present invention provides a linear regulator circuit using an N-type intrinsic transistor and a P-type transistor for switching, and reasonably selecting the threshold voltage for switching the N-type transistor and the P-type transistor to achieve a smooth transition between the conduction of the N-type transistor and the conduction of the P-type transistor, and the circuit can meet the requirements of wide power voltage range applications. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A linear regulator circuit, comprising:
a main drive voltage stabilizer circuit and a low voltage drive circuit;
the main drive voltage stabilizer circuit is provided with a power supply voltage and an NMOS drive device; the power supply voltage is connected with the drain electrode of the NMOS driving device;
the low-voltage driving circuit consists of a power supply sampling module, a comparator, an inverter and a second PMOS (P-channel metal oxide semiconductor) tube; the input end of the power supply sampling module is connected with the power supply voltage, and the output is sampling point voltage; the negative pin of the input end of the comparator is connected with the output end of the power supply sampling module, and the positive pin of the input end of the comparator is connected with an input reference voltage; the input end of the phase inverter is connected with the output end of the comparator; the output end of the phase inverter is connected with the grid electrode of the second PMOS tube; the source electrode of the second PMOS tube is connected with the power supply voltage of the main drive voltage stabilizer circuit;
the drain electrode of the second PMOS tube and the source electrode of the NMOS driving device are jointly used as output end voltage; under the condition of low-voltage application, the value of the power supply voltage is 1.62V to 5.5V, and the value of the output end voltage is 1.6V to 1.98V.
2. The linear regulator circuit of claim 1, wherein: the main drive voltage stabilizer circuit further comprises a first PMOS tube, wherein the source electrode of the first PMOS tube is connected to the power voltage, and the drain electrode of the first PMOS tube is connected with the grid electrode of the NMOS drive device.
3. The linear regulator circuit of claim 2, wherein: the main driving voltage stabilizer circuit further comprises a P-type MOS transistor PM0 and four N-type MOS transistors: NM0 tube, NM1 tube, NMirr0 tube, NMirr1 tube; the main driving voltage regulator circuit also comprises a resistor R0, a resistor R1 and a capacitor Cc; the source electrode of the PM0 tube is connected to the power supply voltage end, and the grid electrode of the PM0 tube is connected with the grid electrode of the first PMOS tube and the drain electrode of the NM0 tube; the grid electrode of the NM0 tube is connected with an input reference voltage; the drain electrode of the first PMOS tube, the grid electrode of the NMOS driving device, the drain electrode of the NM1 tube and the upper plate of the capacitor Cc are connected with each other; the source electrode of the NM0 tube, the source electrode of the NM1 tube and the drain electrode of the NMirr1 tube are connected with each other; the grid and the drain of the NMirr0 tube and the grid of the NMirr1 tube are connected with a bias current source in common; one end of the resistor R1 and the source electrode of the NMOS driving device are used together as output end voltage; the other end of the resistor R1, the grid of the NM1 tube and one end of the resistor R0 are connected together; the lower plate of the capacitor Cc, the other end of the resistor R0, the source of the NMirr1 tube and the source of the NMirr0 tube are commonly grounded.
4. The linear regulator circuit of claim 1, wherein: under the condition of low-voltage application, the power supply voltage is 1.62V, the output end voltage is 1.6V, and the driving current is 10 mA.
5. The linear regulator circuit of claim 1, wherein: under all conditions, the threshold voltage of the NMOS drive device is more than 20 mV.
6. The linear regulator circuit of claim 1, wherein: the threshold voltage of the second PMOS tube is less than 1.62V.
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| CN201910144744.3A CN109871060B (en) | 2019-02-27 | 2019-02-27 | Linear voltage regulator circuit |
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| CN201910144744.3A CN109871060B (en) | 2019-02-27 | 2019-02-27 | Linear voltage regulator circuit |
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| US20060170466A1 (en) * | 2005-01-31 | 2006-08-03 | Sangbeom Park | Adjustable start-up circuit for switching regulators |
| CN101776930A (en) * | 2009-01-14 | 2010-07-14 | 易亨电子股份有限公司 | Low-voltage starting circuit capable of bearing high voltage and having reverse-phase protection function |
| US9209688B2 (en) * | 2013-03-08 | 2015-12-08 | Analog Devices Global | Controlling current in a switching regulator |
| CN106774575B (en) * | 2016-12-29 | 2019-05-31 | 北京兆易创新科技股份有限公司 | A kind of low pressure difference linear voltage regulator |
| CN107402594B (en) * | 2017-08-31 | 2019-01-18 | 电子科技大学 | Realize the low-power consumption low pressure difference linear voltage regulator of high power supply voltage transformation |
| CN108287588B (en) * | 2018-01-30 | 2019-10-11 | 上海华虹宏力半导体制造有限公司 | Voltage adjuster |
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