CN109871060A - Linear regulator circuit - Google Patents
Linear regulator circuit Download PDFInfo
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- CN109871060A CN109871060A CN201910144744.3A CN201910144744A CN109871060A CN 109871060 A CN109871060 A CN 109871060A CN 201910144744 A CN201910144744 A CN 201910144744A CN 109871060 A CN109871060 A CN 109871060A
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- voltage
- pipe
- regulator circuit
- pmos tube
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Abstract
The present invention provides a kind of linear regulator circuit, comprising: main driving voltage regulator circuit and low-voltage driving circuit；Low-voltage driving circuit is made of power supply sampling module, comparator, phase inverter and the second PMOS tube；Power supply sampling module input termination supply voltage；Comparator input terminal connects power supply sampling module, input one input reference voltage of termination；Phase inverter is connect with comparator；Phase inverter is connect with the grid of the second PMOS tube；Second PMOS tube source electrode connects supply voltage；The drain electrode of second PMOS tube is with NMOS driving element source electrode collectively as output end voltage.The present invention switches the linear regulator circuit used using N-type intrinsic transistor and P-type transistor, reasonably select the threshold voltage of N-type transistor and P-type transistor switching, to realize the smooth transition of N-type transistor and P-type transistor conducting, which can satisfy the demand of wide power voltage range applications.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of linear regulator circuit.
Background technique
Conventional linear voltage regulator circuit can use PMOS tube or NMOS tube as driving element, as shown in Figure 1, Fig. 1 is shown
It is used as the linear regulator circuit of driving element for traditional PMOS tube.Traditional PMOS tube is used as the linear voltage regulator electricity of driving element
Include three PMOS tube in road: PM0 pipe, PM1 pipe and the Mpass as driving element are managed, the linear regulator circuit further include:
Four NMOS tubes (NM0 pipe, NM1 pipe, NMirr0 pipe, NMirr1 pipe, three resistance (R0, Rc and R1) and a capacitor Cc,
The source electrode of the driving element PMOS tube connects supply voltage VCC, drains as output end V_LDO, the grid of the PM0 pipe and institute
The grid and its drain electrode conode PB of PM1 pipe are stated, one end of the drain electrode of the PM0 pipe, the grid of Mpass pipe and resistance RC is total
Node PG, the grid of the NM1 pipe, one end of resistance R0 and one end conode VFD of resistance R1, the grid of the NMirr0 pipe
The grid conode NB of pole, drain electrode and the NMirr1 pipe, node NB meet an input bias current source IB.The resistance R0's
The other end, the source electrode of the NMirr1 pipe and the NMirr0 pipe source electrode are grounded jointly.
Output voltage can overshoot when can support low pressure applications when traditional PMOS tube is as driving element, but power on fastly, i.e.,
When power supply fast powering-up (when i.e. with nanosecond fast powering-up to required operating voltage VCC), node during operating point is established
PG is electrically charged from low level, and Mpass pipe can be connected high current and the output end V_LDO of LDO is flushed to higher level, to produce
Raw overshoot phenomenon.When traditional PMOS tube is as driving element simultaneously, what the power supply rejection ability of output voltage was also not easy to design
It is very high.
Fig. 2 is shown as the linear regulator circuit that NMOS tube is used as driving element.NMOS tube is used as the linear of driving element
NMOS tube Mpass pipe is connected to the power voltage terminal, grid as driving element, the source electrode of PM0 pipe in voltage regulator circuit
It is connect with the drain electrode of the grid of PM1 pipe, NM0 pipe；The grid of driving element NMOS tube Mpass pipe, capacitor Cc top crown,
The drain electrode of PM1 pipe and the drain electrode conode NG of NM1 pipe.
When NMOS tube is used as driving element, powering on will not be overshooted, while the power supply that output voltage can be improved inhibits energy
Power, but the minimum of supply voltage is higher, the especially output voltage application scenarios higher than supply voltage, such as standard CMOS work
Skill platform, input voltage 1.62V~5.5V, output voltage are required in 1.6V~1.98V, then can not support low pressure applications.
It is, therefore, desirable to provide a kind of new linear regulator circuit solves the above problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of linear regulator circuits, use
In solving in the prior art when NMOS tube is as driving element, low pressure can not be supported since the minimum of supply voltage is higher
Using the problem of.
In order to achieve the above objects and other related objects, the present invention provides a kind of linear regulator circuit, the linear voltage stabilization
Device circuit includes at least: main driving voltage regulator circuit and low-voltage driving circuit；The main driving voltage regulator circuit is equipped with power supply electricity
Pressure and NMOS driving element；The supply voltage connects the drain electrode of the NMOS driving element；The low-voltage driving circuit is by power supply
Sampling module, comparator, phase inverter and the second PMOS tube composition；The power supply sampling module input terminates the supply voltage,
Output is sample amplitude when reproduced；The negative foot of comparator input terminal connects the output end of the power supply sampling module, and input is rectified
Foot connects an input reference voltage；The inverter input is connect with the output end of the comparator；The phase inverter it is defeated
Outlet is connected with the grid of second PMOS tube；The source electrode of second PMOS tube connects the main driving voltage regulator circuit
Supply voltage；The drain electrode of second PMOS tube and the source electrode of the NMOS driving element are collectively as output end voltage.
Preferably, the main driving voltage regulator circuit further includes the first PMOS tube, the source electrode connection of first PMOS tube
In the supply voltage, drain electrode is connected with the grid of the NMOS driving element.
Preferably, the main driving voltage regulator circuit further includes a p-type metal-oxide-semiconductor PM0 pipe and four N-type metal-oxide-semiconductors: NM0
Pipe, NM1 pipe, NMirr0 pipe, NMirr1 pipe；The main driving voltage regulator circuit further includes resistance R0 and resistance R1 and capacitor
Cc；The source electrode of the PM0 pipe is connected to the power voltage terminal, the leakage of grid and the grid, NM0 pipe of first PMOS tube
Pole connection；The grid of the NM0 pipe connects an input reference voltage；The drain electrode of first PMOS tube, the NMOS driver
The drain electrode of the grid, NM1 pipe of part and the top crown of the capacitor Cc are connected with each other；The source electrode of the NM0 pipe, NM1 pipe
The drain electrode of source electrode and the NMirr1 pipe is connected with each other；The grid of the NMirr0 pipe, drain electrode and the NMirr1 pipe grid
A bias current sources are extremely connected jointly；The source electrode of one end of the resistance R1 and the NMOS driving element is collectively as output end
Voltage；One end of the other end of the resistance R1, the grid of NM1 pipe and resistance R0 connects jointly；Under the capacitor Cc
Pole plate, the other end of the resistance R0, the source electrode of the NMirr1 pipe and the NMirr0 pipe source electrode are grounded jointly.
Preferably, under the conditions of low pressure applications, the value of the supply voltage is 1.62V to 5.5V, the output end voltage
Value is 1.6V to 1.98V.
Preferably, under the conditions of low pressure applications, the supply voltage is 1.62V, and the output end voltage is 1.6V, the drive
Streaming current is 10mA.
Preferably, under the conditions of complete, the threshold voltage of NMOS driving element is greater than 20mV.
Preferably, the threshold voltage of second PMOS tube is less than 1.62V.
As described above, linear regulator circuit of the invention, has the advantages that the present invention uses the intrinsic crystalline substance of N-type
Body pipe and P-type transistor switch the linear regulator circuit used, reasonably select the threshold of N-type transistor and P-type transistor switching
Threshold voltage, to realize the smooth transition of N-type transistor and P-type transistor conducting, which can satisfy wide power voltage range
The demand of application.
Detailed description of the invention
Fig. 1 is shown as the linear regulator circuit schematic diagram that traditional PMOS tube is used as driving element；
Fig. 2 is shown as the linear regulator circuit schematic diagram that NMOS tube in the prior art is used as driving element；
Fig. 3 is shown as linear regulator circuit schematic diagram of the invention.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
It please be refering to Fig. 3.It should be noted that only the invention is illustrated in a schematic way for diagram provided in the present embodiment
Basic conception, only shown in schema then with related component in the present invention rather than component count, shape when according to actual implementation
Shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its component cloth
Office's kenel may also be increasingly complex.
As shown in figure 3, Fig. 3 is shown as linear regulator circuit schematic diagram of the invention.The embodiment of the present invention is linearly steady
Transformer circuits include: the low-voltage driving circuit of main the driving voltage regulator circuit and right half part of left-half in Fig. 3.Two electricity
The source electrode of NMOS driving element is connected between road by the drain electrode of the second PMOS tube, meanwhile, the source electrode of the second PMOS tube and
The drain electrode of NMOS driving element is commonly connected to supply voltage VCC.
As shown in figure 3, the main driving voltage regulator circuit therein is equipped with supply voltage VCC and NMOS driving element
Mpass pipe, Mpass pipe are N-type intrinsic transistor；The supply voltage VCC connects the NMOS driving element Mpass pipe
Drain electrode；When the NMOS driving element Mpass pipe is used as the driving element of linear regulator circuit, overshoot will not be generated now by powering on
As (i.e. with nanosecond fast powering-up to required operating voltage VCC), while the power supply rejection ability of output voltage can be improved.
In Fig. 3, the low-voltage driving circuit is by power supply sampling module, comparator CMP, phase inverter INV0 and second
PMOS tube PM2 composition；The power supply sampling module input terminates the supply voltage VCC, and output is sample amplitude when reproduced Vdet；
The negative foot of input terminal of the comparator CMP connects the output end of the power supply sampling module, the power supply sampling module by itself
The sample amplitude when reproduced of sampled output is transferred to the input terminal of the comparator CMP.The positive foot of the comparator CMP input terminal connects
Meet an input reference voltage VREF；Comparator can be regarded as amplification factor close to the operational amplifier of " infinity ".Comparator
The function of CMP: the size for comparing two voltage (with the high or low level of output voltage, indicates that the size of two input voltages is closed
System): when "+" input terminal voltage is higher than "-" input terminal when, comparator CMP output is high level；When "+" input terminal voltage is low
In "-" input terminal when, voltage comparator output be low level.
The input terminal of the phase inverter INV0 is connect with the output end of the comparator CMP；The comparator by its own
It is electric for height to the phase inverter INV0, such as comparator CMP output by the high level or low level output that compare selection
It is flat, after inverted device INV0, export as low level；It is defeated after inverted device INV0 if comparator CMP output is low level
It is out high level.The output end of the phase inverter INV0 is connected with the grid of second PMOS tube；That is, the electricity
The sampled voltage of source sampling module output is transmitted to phase inverter after comparator CMP screening, and the phase inverter will receive
Gate input voltage of the voltage signal as second PMOS tube.
In Fig. 3, the source electrode of the second PMOS tube PM2 is connected to the supply voltage VCC of the main driving voltage regulator circuit；
The drain electrode of second PMOS tube and the source electrode of the NMOS driving element Mpass pipe are collectively as voltage output end.
As shown in figure 3, further include the first PMOS tube PM1 in the present embodiment, in the main driving voltage regulator circuit, described
The source electrode of one PMOS tube PM1 pipe is connected to the supply voltage VCC, the grid of drain electrode and the NMOS driving element Mpass pipe
Pole is connected.
It further, further include a p-type MOS in the main driving voltage regulator circuit as shown in figure 3, in the present embodiment
Pipe PM0 pipe and four N-type metal-oxide-semiconductors: NM0 pipe, NM1 pipe, NMirr0 pipe, NMirr1 pipe；The main driving voltage regulator circuit further includes
Resistance R0 and resistance R1 and capacitor Cc；The source electrode of the PM0 pipe is connected to the power voltage terminal VCC, grid and institute
State the drain electrode connection of the grid, NM0 pipe of the first PMOS tube PM1, the two conode PB；One input of grid connection of the NM0 pipe
Reference voltage VREF；The drain electrode of first PMOS tube, the NMOS driving element Mpass grid, NM1 pipe drain electrode and
The top crown of the capacitor Cc is connected with each other, and conode NG；The source electrode of the NM0 pipe, the source electrode of NM1 pipe and described
The drain electrode of NMirr1 pipe is connected with each other.
The grid of the main grid for driving the NMirr0 pipe in voltage regulator circuit, drain electrode and the NMirr1 pipe is total
Node NB and a bias current sources IB is connected jointly；One end of the resistance R1 and the NMOS driving element Mpass pipe
The drain electrode of the second PMOS tube in source electrode and the low-voltage driving circuit is connected with each other and collectively as voltage output end；It is described
One end of the other end of resistance R1, the grid of NM1 pipe and resistance R0 connects jointly and conode VFD；The capacitor Cc's
Bottom crown, the other end of the resistance R0, the source electrode of the NMirr1 pipe and the NMirr0 pipe source electrode are grounded jointly
(GND)。
Heretofore described main driving voltage regulator circuit is the linear voltage regulator electricity that tradition uses NMOS tube as driving element
Road, minimum power supply voltage, be the voltage output end voltage VOUT and Vgs (voltage between the grid source of Mpass pipe) and
Vds (source-drain voltage of pm1 pipe), the present invention in Mpass pipe select N-type intrinsic transistor, with compatibility standard CMOS processing procedure, no
When increasing extra cost, and having big sourcing current on output end voltage VOUT, voltage VOUT is pulled low, N-type intrinsic transistor
Gate source voltage becomes larger, and can provide instantaneous large-current to meet the desired driving capability of external circuit, such as memory circuit
Read-write operation.Instantaneous large-current is no longer provided by output load capacitance simultaneously, also be can reduce area, is reduced cost.
Under the conditions of low pressure applications, the NMOS driving element Mpass pipe of main driving voltage regulator circuit is equivalent to a switch
It uses, preferably, under the conditions of low pressure applications, the value of the supply voltage VCC is 1.62V to 5.5V, the output to the present embodiment
The value for holding voltage VOUT is 1.6V to 1.98V.Further, under the conditions of low pressure applications, the supply voltage is 1.62V, described
Output end voltage is 1.6V, and the driving current is 10mA.Further, in the present embodiment, under the conditions of complete, NMOS driver
The threshold voltage of part is greater than 20mV, that is to say, that under different process angle and different temperatures, the threshold voltage of NMOS driving element
Greater than 20mV.
That is, when the supply voltage VCC of input is 1.62V, and output end voltage VOUT is 1.6V, if providing 10mA's
Driving current, it is contemplated that the influence of flow-route and temperature, intrinsic N-type transistor under the different process angle of full condition and different temperatures
The gate source voltage of 20mV, which is also hard to turn on, provides enough driving currents.
As shown in figure 3, the low voltage drive circuit of right half part mainly has power supply sampling module, comparator CMP and reverse phase
Device INV0 and second PMOS tube (P-type transistor driving element) composition.When sample amplitude when reproduced Vdet is greater than input reference
When voltage VREF, comparator CMP output is low level, is exported by phase inverter INV0, and the grid voltage of PM2 pipe is high level,
For PMOS tube, grid connects low-voltage, as long as the grid low-voltage is less than source, any pole tension of leakage adds the PMOS
The threshold voltage of pipe, then the PMOS tube is connected, conversely, then ending.Therefore, in the case where power supply low pressure VCC is low-voltage, warp
Phase inverter INV0 export to the PM2 pipe grid voltage be high level in the case where, PM2 pipe cut-off.
Preferably, the threshold voltage of the second PMOS tube of the embodiment of the present invention is less than 1.62V.
And when sample amplitude when reproduced Vdet is less than input reference voltage VREF, comparator CMP output is high level, by anti-
Phase device INV0 output, the grid voltage of PM2 pipe are low level, and in the case that the supply voltage VCC of input is 1.62V, PM2 pipe can
To fully open, when PM2 conducting, since the source electrode of PM2 pipe connects supply voltage VCC, its source voltage can be transmitted
To its drain electrode, supply voltage VCC is not just transferred to output end, and output end voltage VOUT is 1.62V.
Source-drain voltage pressure drop can be made to meet requirement by adjusting the breadth length ratio of PM2 pipe simultaneously.
In conclusion the invention proposes use N-type intrinsic transistor and P-type transistor to switch the linear voltage regulator used
Circuit reasonably selects the threshold voltage of N-type transistor and P-type transistor switching, to realize that N-type transistor and P-type transistor are led
Logical smooth transition, the circuit can satisfy the demand of wide power voltage range applications.So the present invention effectively overcome it is existing
Various shortcoming in technology and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (7)
1. a kind of linear regulator circuit, which is characterized in that the linear regulator circuit includes at least:
Main driving voltage regulator circuit and low-voltage driving circuit；
The main driving voltage regulator circuit is equipped with supply voltage and NMOS driving element；The supply voltage connects the NMOS driving
The drain electrode of device；
The low-voltage driving circuit is made of power supply sampling module, comparator, phase inverter and the second PMOS tube；The power supply sampling
Module input connects the supply voltage, exports as sample amplitude when reproduced；The negative foot of comparator input terminal connects the power supply and adopts
The output end of egf block inputs and rectifies foot one input reference voltage of connection；The inverter input and the comparator
Output end connection；The output end of the phase inverter is connected with the grid of second PMOS tube；The source of second PMOS tube
Pole connects the supply voltage of the main driving voltage regulator circuit；
The drain electrode of second PMOS tube and the source electrode of the NMOS driving element are collectively as output end voltage.
2. linear regulator circuit according to claim 1, it is characterised in that: the main driving voltage regulator circuit further includes
First PMOS tube, the source electrode of first PMOS tube are connected to the supply voltage, drain electrode and the NMOS driving element
Grid is connected.
3. linear regulator circuit according to claim 2, it is characterised in that: the main driving voltage regulator circuit further includes
One p-type metal-oxide-semiconductor PM0 pipe and four N-type metal-oxide-semiconductors: NM0 pipe, NM1 pipe, NMirr0 pipe, NMirr1 pipe；The main driving voltage-stablizer
Circuit further includes resistance R0 and resistance R1 and capacitor Cc；The source electrode of the PM0 pipe is connected to the power voltage terminal, grid
Pole is connect with the drain electrode of the grid, NM0 pipe of first PMOS tube；The grid of the NM0 pipe connects an input reference voltage；Institute
State the top crown of the drain electrode of the first PMOS tube, the grid of the NMOS driving element, the drain electrode of NM1 pipe and the capacitor Cc
It is connected with each other；The drain electrode of the source electrode of the NM0 pipe, the source electrode of NM1 pipe and the NMirr1 pipe is connected with each other；The NMirr0
The grid of the grid of pipe, drain electrode and the NMirr1 pipe connects a bias current sources jointly；One end of the resistance R1 with it is described
The source electrode of NMOS driving element is collectively as output end voltage；The other end of the resistance R1, the grid of NM1 pipe and resistance R0
One end connect jointly；The bottom crown of the capacitor Cc, the other end of the resistance R0, the NMirr1 pipe source electrode and
The NMirr0 pipe source electrode is grounded jointly.
4. linear regulator circuit according to claim 1, it is characterised in that: under the conditions of low pressure applications, the power supply electricity
The value of pressure is 1.62V to 5.5V, and the value of the output end voltage is 1.6V to 1.98V.
5. linear regulator circuit according to claim 4, it is characterised in that: under the conditions of low pressure applications, the power supply electricity
Pressure is 1.62V, and the output end voltage is 1.6V, and the driving current is 10mA.
6. linear regulator circuit according to claim 1, it is characterised in that: under the conditions of complete, the threshold of NMOS driving element
Threshold voltage is greater than 20mV.
7. linear regulator circuit according to claim 1, it is characterised in that: the threshold voltage of second PMOS tube is small
In 1.62V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910144744.3A CN109871060B (en) | 2019-02-27 | 2019-02-27 | Linear voltage regulator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910144744.3A CN109871060B (en) | 2019-02-27 | 2019-02-27 | Linear voltage regulator circuit |
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| Publication Number | Publication Date |
|---|---|
| CN109871060A true CN109871060A (en) | 2019-06-11 |
| CN109871060B CN109871060B (en) | 2021-04-06 |
Family
ID=66919418
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910144744.3A Active CN109871060B (en) | 2019-02-27 | 2019-02-27 | Linear voltage regulator circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113741608A (en) * | 2021-08-30 | 2021-12-03 | 普冉半导体(上海)股份有限公司 | Linear voltage regulator circuit |
| CN115469703B (en) * | 2022-10-27 | 2024-05-03 | 北京智芯微电子科技有限公司 | Linear voltage stabilizing circuit, working method and electronic equipment |
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| CN106774575A (en) * | 2016-12-29 | 2017-05-31 | 北京兆易创新科技股份有限公司 | A kind of low pressure difference linear voltage regulator |
| CN107402594A (en) * | 2017-08-31 | 2017-11-28 | 电子科技大学 | Realize the low-power consumption low pressure difference linear voltage regulator of high power supply voltage transformation |
| CN108287588A (en) * | 2018-01-30 | 2018-07-17 | 上海华虹宏力半导体制造有限公司 | Voltage adjuster |
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| US20060170466A1 (en) * | 2005-01-31 | 2006-08-03 | Sangbeom Park | Adjustable start-up circuit for switching regulators |
| CN101776930A (en) * | 2009-01-14 | 2010-07-14 | 易亨电子股份有限公司 | Low-voltage starting circuit capable of bearing high voltage and having reverse-phase protection function |
| US20140253083A1 (en) * | 2013-03-08 | 2014-09-11 | Analog Devices Technology | Controlling current in a switching regulator |
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| CN109871060B (en) | 2021-04-06 |
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