CN110045779A - A kind of voltage selecting circuit and method - Google Patents
A kind of voltage selecting circuit and method Download PDFInfo
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- CN110045779A CN110045779A CN201910239185.4A CN201910239185A CN110045779A CN 110045779 A CN110045779 A CN 110045779A CN 201910239185 A CN201910239185 A CN 201910239185A CN 110045779 A CN110045779 A CN 110045779A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
Abstract
The invention discloses a kind of voltage selecting circuit and methods, circuit includes peak point current source circuit, hysteresis comparator circuit and voltage follower circuit, the input of peak point current source circuit terminates supply voltage, and output end is connected with hysteresis comparator circuit, for generating bias current sources；The input terminal of hysteresis comparator circuit is connected with the first input voltage source and second source voltage, and output end is connected with voltage follower circuit, for generating logic level；Voltage follower circuit selects the first input voltage source of output or the second input voltage source according to logic level.The present invention provides bias current in order to fast and accurately select in two voltage sources a lower or higher voltage as output, by peak point current source circuit, therefore the quiescent dissipation of circuit is lower；The hysteresis comparator circuit of source input eliminates the Miller effect of parasitic capacitance, has many advantages, such as that fast response time, anti-noise jamming ability are strong；In addition voltage selecting circuit structure is simple, saves chip area.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, more particularly, to a kind of voltage selecting circuit and method.
Background technique
Analog power technical field, which is passed through, compares two input voltages frequently with voltage selecting circuit, thus selection wherein compared with
High or lower input voltage is as output voltage.For example, the LDO circuit with reversed input current defencive function, internal past
Toward voltage selecting circuit can be added to ensure the substrate electric potential of power tube at work always in suitable current potential.Otherwise, defeated
Enter the unexpected power down of voltage, when the various abnormal conditions such as due to voltage spikes occurs in output end, the parasitic body diode in power tube can
It can be connected, to generate the phenomenon that electric current flows backward, biggish damage is caused to chip itself and supplying cell.
Fig. 1 show Chinese invention patent application " integrated circuit and voltage selecting circuit " (application number:
201510292905.5, applying date: on May 26th, 2015) in a kind of voltage selecting circuit for proposing, the circuit structure is simple,
It only include two p-types metal-oxide-semiconductor P1 and P2, but when the two input voltages difference for needing to compare is smaller, P1 and P2 fail
Conducting, circuit cannot select suitable voltage as output at this time.In addition, in some traditional voltage selecting circuits, usually
Using the hysteresis comparator of grid input as voltage comparator circuit, the Miller effect of input terminal parasitic capacitance reduces comparator
Bandwidth, increase its response time.
Summary of the invention
In view of the drawbacks of the prior art, the purpose of the present invention is to provide a kind of voltage selecting circuit and methods, it is intended to solve
Certainly in the prior art when two input supply voltages are closer to, it cannot correctly select suitable input supply voltage as output
The problem of.
To achieve the above object, it is an aspect of this invention to provide that providing a kind of voltage selecting circuit, including peak point current
Source circuit, hysteresis comparator circuit and voltage follower circuit；The input of peak point current source circuit terminates supply voltage, output end and late
Stagnant comparison circuit is connected, for generating bias current sources；The input terminal of hysteresis comparator circuit and the first input voltage source and second
Input voltage source is connected, and output end is connected with voltage follower circuit, for generating logic level；Voltage follower circuit is according to output
Logic level selection the first input voltage source of output or the second input voltage source.
Preferably, bias current sources are mirrored to obtain the first mirror current source, the second mirror image electricity by hysteresis comparator circuit
Stream source and third mirror current source.
Preferably, hysteresis comparator circuit includes source input pair, and source input is to utilization the first mirror current source and second
Mirror current source compares the size of the first input voltage source and the second input voltage source as bias current.
Preferably, logic level is for judging whether to introduce third mirror current source in hysteresis comparator circuit as negative
It carries.
Preferably, voltage follower circuit includes two PMOS tube, by logic level control switch.
It is another aspect of this invention to provide that providing a kind of voltage selection method based on foregoing circuit, comprising:
Input supply voltage obtains bias current sources by peak point current source circuit；
Bias current sources relatively obtain the logic level of control voltage output by sluggish；
Logic level control circuit switch, selects output voltage.
Preferably, selecting output voltage can be high voltage or low-voltage.
Contemplated above technical scheme through the invention, can obtain it is following the utility model has the advantages that
1, the present invention provides bias current by peak point current source circuit, therefore the quiescent dissipation of circuit is lower, in wider electricity
Steady operation is remained in the voltage range of source, and there is turn-off function；
2, the hysteresis comparator circuit that the present invention uses can eliminate the Miller effect of parasitic capacitance using source as input,
To improve the bandwidth of comparator, reduce the response time；
3, the present invention can reduce the influence of noise by the sluggishness that third mirror current source introduces, and improve the anti-dry of circuit
Disturb ability；
4, the voltage follower circuit that the present invention uses only includes two PMOS switch pipes, and structure is simple, saves chip area.
Detailed description of the invention
Fig. 1 is a kind of schematic illustration of voltage selecting circuit of the prior art；
Fig. 2 is a kind of structural block diagram of voltage selecting circuit provided by the invention；
Fig. 3 is a kind of structural schematic diagram of low-voltage selection circuit provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram for high voltage selection circuit that further embodiment of this invention provides；
Description of symbols:
100,200,300,400: voltage selecting circuit, 201: supply voltage VDD, 202,302,402: peak current source electricity
Road, 203: bias current IBIAS, the 203A: the first mirror current source I1, the 203B: the second mirror current source I2, 203C: third mirror image
Current source I3, 204,304,404: hysteresis comparator circuit, 206,306,406: voltage follower circuit, 207,307,407: source is defeated
Enter pair, 208,210,308,310,408,410: the output logic level of hysteresis comparator circuit, 209: the first input voltage source V1,
213: the second input voltage source V2, 215: output voltage source Vout, 222,333,444: multichannel current mirror, 301,401: the first late
Stagnant reverser inv1,303,403: the second phase inverter inv2.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 2 shows a kind of structural block diagrams of voltage selecting circuit 200 proposed by the present invention, including peak point current source circuit
202, the hysteresis comparator circuit 204 and voltage follower circuit 206 of source input, in some embodiments, voltage selecting circuit 200
It is configured to from the first input voltage V1With the second input voltage V2Middle selection appropriate ones are delivered to output.
Specifically, the input of peak point current source circuit 202 terminates supply voltage VDD, output end and hysteresis comparator circuit 204
It is connected, in wider supply voltage VDDSteady operation is remained in range, it is final to generate bias current sources IBIAS；First input voltage
Source V1With the second input voltage source V2The hysteresis comparator circuit input inputted from source, hysteresis comparator circuit include source input pair,
Output end is connected with the voltage follower circuit, by multichannel current mirror come mirror image bias current sources IBIASObtain the first mirror image electricity
Stream source I1, the second mirror current source I2And third mirror current source I3, source input is to the first mirror current source I of utilization1With
Two mirror current source I2As bias current and active load, compare the first input voltage source V1With the second input voltage source V2's
Size exports logic level 208 and 210；Comparator circuit judges whether to introduce third mirror image electricity according to output logic level 208
Stream source I3It is formed sluggish；Voltage follower circuit is according to output selection output the first input voltage source or second of logic level 210
Input voltage source.
Fig. 3 shows a kind of structural schematic diagram of low-voltage selection circuit, it should be noted that circuit diagram shown in Fig. 3 is only voltage
One of various embodiments of selection circuit 200, Fig. 4 are also another embodiments of voltage selecting circuit 200.It is shown in Fig. 3
Embodiment in voltage selecting circuit 200 peak point current source circuit 202 include: first, second, third PMOS tube P1, P2,
P3, first, second NMOS tube N1, N2 and first resistor R1, the source electrode of the first PMOS tube P1 meet power supply VDD, grid connects enable signal
EN0, the grounded-grid of the second PMOS tube P2, source electrode connect the drain electrode of the first PMOS tube P1, drain electrode and the first NMOS tube N1 grid
It is shorted and is connected to first resistor R1 anode, the source electrode of third PMOS tube P3 meets power supply VDD, grid with drain electrode be shorted and be connected to
The drain electrode of second NMOS tube N2, the drain electrode of the first NMOS tube N1 and the grid of the second NMOS tube N2 are shorted and are connected to first resistor
The source electrode of R1 negative terminal, the first NMOS tube N1 and the second NMOS tube N2 are grounded.
More specifically, for the peak point current mirror circuit 302 shown in Fig. 3, the grid of the first PMOS tube P1 connects enabled letter
Number EN0, the height of enable signal EN0 can control the switch of entire circuit.Second PMOS tube P2 is down that breadth length ratio is very than pipe
It is small, guarantee the first NMOS tube N1 and the second NMOS tube N2 work in sub-threshold region, to reduce quiescent dissipation；Third PMOS tube P3
Effect with the 4th PMOS tube P4 is by bias current IBIASBe converted to bias voltage VBIAS.Pass through the first NMOS tube N1 and second
There are a kind of relationships of peak point current between two groups of electric currents of NMOS tube N2, can be released according to sub-threshold region formula:
Wherein n is subthreshold numerical constant, usually 1.3~1.5, IN1And IN2Respectively flow through the first NMOS tube N1 and second
Two groups of electric currents of NMOS tube N2, (W/L)N1(W/L)N2The respectively breadth length ratio of the first NMOS tube N1 and the second NMOS tube N2.
Then, the hysteresis comparator circuit 204 of the source input of voltage selecting circuit 200 wraps in the embodiment shown in fig. 3
Include the four, the five, the 6th PMOS tube P4, P5, P6, third, the four, the 5th NMOS tube N3, N4, N5, second resistance R2, third electricity
R3, the first sluggish phase inverter inv1, the second sluggish phase inverter inv2 are hindered, the source electrode of the 4th to the 6th PMOS tube P4~P6 connects power supply
VDD, the grid of the 4th to the 6th PMOS tube P4~P6 is all connected to the grid of third PMOS tube P3, the drain electrode of the 4th PMOS tube P4
Drain electrode, grid with third NMOS tube N3 are shorted and are connected to the grid of the 4th NMOS tube N4, the drain electrode of the 5th PMOS tube P5,
Source electrode are shorted and is connected to the input terminal of the first sluggish phase inverter inv1 by the drain electrode of four NMOS tube N4, the 5th NMOS tube N5, the
The drain electrode of six PMOS tube P6 is connected to the drain electrode of the 5th NMOS tube N5, and the output end of the first sluggish phase inverter inv1 is connected to second
The output end of the input terminal of sluggish phase inverter inv2, the second sluggish phase inverter inv2 is connected to the grid of the 5th NMOS tube N5, the
The source electrode of three NMOS tube N3 and the 4th NMOS tube N4 is connected respectively to the anode of second resistance and 3rd resistor, second resistance and
The negative terminal of three resistance is separately connected the first input voltage source V1With the second input voltage source V2。
Although may be regarded as various it should be noted that multichannel current mirror 333 is fundamental current mirror in embodiment shown in Fig. 3
Any one of form current mirror, such as the common-source common-gate current mirror of automatic biasing.
In the embodiment shown in fig. 3, the 4th PMOS tube P4 mirror image peak current source IBIASThe the first mirror image electricity generated afterwards
Stream source I1, bias current and active load as third NMOS tube N3；5th PMOS tube P5 mirror image peak current source IBIASAfter produce
Raw and the first mirror current source I1The second equal mirror current source I2, as the bias current of the 4th NMOS tube N4 and active negative
It carries.As two input voltage source V1=V2When, the electric current for flowing through third NMOS tube N3 and the 4th NMOS tube N4 is identical, at circuit
In equilibrium state；Work as V1< V2When, the grid voltage V of third NMOS tube N3XMeeting and V1It is synchronous to reduce, the grid of the 4th NMOS tube N4
Voltage can be also pulled low, and the electric current at this moment flowing through the 4th NMOS tube N4 will reduce, and the voltage of net0 point can be raised.Similarly,
Work as V1> V2When, the grid voltage V of third NMOS tube N3XMeeting and V1Synchronous to improve, the grid voltage of the 4th NMOS tube N4 can also be drawn
Height, the electric current at this moment flowing through the 4th NMOS tube N4 just will increase, and the voltage of net0 point can be pulled low.First sluggish phase inverter inv1
Meeting carries out shaping to the voltage waveform of net0 point, prevents intermediate state, while exporting logic level 308；Second sluggish reverse phase
Device inv2 output and the reversed logic level 310 of logic level 308.Logic level 310 can control leading for the 5th NMOS tube N5
Logical and closing, to decide whether to introduce third mirror current source I3, ultimately form sluggishness.
It for above-mentioned hysteresis comparator circuit 304, is further described, if the first input voltage source V1It fixes, then third
The grid voltage V of NMOS tube N3 and the 4th NMOS tube N4xAlso relatively fixed, work as V2< V1And V2It is gradually increased, flows through the 4th NMOS tube N4
Electric current be gradually reduced, when export logic level 308 and 310 just jump when, there are following relationships:
Wherein μnIndicate electron mobility, COXIndicate unit area gate oxide capacitance, VTNIndicate metal-oxide-semiconductor threshold voltage,Indicate the breadth length ratio of the 4th NMOS tube N4, VxIndicate the first input voltage source V1The grid of 4th NMOS tube N4 of one timing
Pressure, V2H、V2LRespectively indicate the first input voltage source V1One the second input voltage source of timing comparator V2High jump threshold value, low jump
Variable threshold value.
If the first input voltage source V1It is fixed, V2> V1And V2It is gradually reduced, when output logic level 308 and 310 is just sent out
When raw jump, there are following relationships:
For above-mentioned hysteresis comparator circuit 304, change third mirror current source I3The adjustable hysteresis space of size.
Then, the voltage follower circuit 206 of voltage selecting circuit 200, including the 7th PMOS in the embodiment shown in fig. 3
Pipe P7 and the 8th PMOS tube P8.Wherein, the grid of the 7th PMOS tube P7 and the 8th PMOS tube P8 is separately connected the second sluggish reverse phase
Source electrode and substrate the connection input second of the output logic electricity 310,308 of device and the first sluggish phase inverter, the 7th PMOS tube P7 are defeated
Enter voltage source V2, the first input voltage source V of source electrode and substrate connection input of the 8th PMOS tube P81, the 7th PMOS tube P7 and the 8th
The drain electrode of PMOS tube P8, which is connected, exports Vout.Work as V2< V1When, output logic level 308 is high level, and output logic level 310 is
Low level, the 7th PMOS tube P7 conducting, the 8th PMOS tube P8 cut-off, Vout=V2；Conversely, working as V2> V1When, export logic level
308 be low level, and output logic level 310 is high level, the 7th PMOS tube P7 cut-off, the 8th PMOS tube P8 conducting, Vout=
V1.Therefore, the voltage follower circuit 306 in embodiment illustrated in fig. 3 is low voltage output circuit.
As mentioned above, voltage selecting circuit 200 also embodiment can carry out implementation as shown in Figure 4.Voltage choosing shown in Fig. 4
It selects circuit 400 and is substantially similar to voltage selecting circuit 300, difference essentially consists in voltage follower circuit.Reality shown in Fig. 4
Apply voltage follower circuit 406 in example, including the 7th PMOS tube P7 and the 8th PMOS tube P8.Wherein, the 7th PMOS tube P7 and the 8th
The grid of PMOS tube P8 is separately connected the output logic level 410 and 408 of the second sluggish phase inverter and the first sluggish phase inverter, the
The source electrode of seven PMOS tube P7 connects input voltage source V1, the source electrode connection input voltage source V of the 8th PMOS tube P82, the 7th PMOS tube
The drain electrode of P7 and the 8th PMOS tube P8 and substrate, which are connected, exports Vout.Work as V2< V1When, output logic level 408 is high level, defeated
Logic level 410 is low level, P7 conducting, P8 cut-off, V outout=V1；Conversely, working as V2> V1When, output logic level 408 is
Low level, output logic level 410 are high level, P7 cut-off, P8 conducting, Vout=V2.Therefore, the electricity in embodiment illustrated in fig. 4
Voltage follower circuit 406 is voltage output circuit.
It should be noted that the circuit diagram of above-mentioned whole embodiment is based on standard CMOS process, peak point current source circuit and sluggishness
The substrate of PMOS tube meets power supply V in comparison circuitDD, source electrode are shorted with itself for PMOS tube substrate in low voltage output circuit,
PMOS tube substrate meets output voltage V in voltage output circuitout, the substrate of all NMOS tubes is grounded.If being based on other works
Skill, it is easy to which change is made to metal-oxide-semiconductor substrate electric potential.For example, it is to be understood that when using double trap CMOS technologies, NMOS tube
Substrate can source electrode are shorted with itself.
In conclusion the present invention can fast and accurately select a lower or higher voltage in two input voltage sources to make
For output voltage.Meanwhile the present invention have quiescent dissipation is low, operating voltage range is wide, fast response time, strong antijamming capability,
Advantages of simple structure and simple.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include
Within protection scope of the present invention.
Claims (7)
1. a kind of voltage selecting circuit, which is characterized in that including peak point current source circuit, hysteresis comparator circuit and voltage output electricity
Road；The input of the peak point current source circuit terminates supply voltage, and output end is connected with the hysteresis comparator circuit, for generating
Bias current sources；The input terminal of the hysteresis comparator circuit is connected with the first input voltage source and second source voltage, output end
It is connected with the voltage follower circuit, for generating logic level；The voltage follower circuit is according to the output logic level
Selection the first input voltage source of output or the second input voltage source.
2. circuit according to claim 1, which is characterized in that the bias current sources pass through the hysteresis comparator circuit quilt
Mirror image obtains the first mirror current source, the second mirror current source and third mirror current source.
3. circuit according to claims 1 and 2, which is characterized in that the hysteresis comparator circuit includes source input pair, institute
It is defeated to comparing first using first mirror current source and second mirror current source as bias current to state source input
Enter the size of voltage source and the second input voltage source.
4. circuit according to claims 1 and 2, which is characterized in that the logic level is for judging whether described slow
Third mirror current source is introduced in stagnant comparator circuit as load.
5. circuit according to claim 1, which is characterized in that the voltage follower circuit includes two PMOS tube, by institute
State logic level control switch.
6. a kind of voltage selection method based on circuit described in any one of claim 1 to 5 characterized by comprising
Input supply voltage obtains bias current sources by peak point current source circuit；
The bias current sources relatively obtain the logic level of control voltage output by sluggish；
The logic level control circuit switch, selects output voltage.
7. method as claimed in claim 6, which is characterized in that described to select output voltage for high voltage output or low-voltage
Output.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910239185.4A CN110045779B (en) | 2019-03-27 | 2019-03-27 | Voltage selection circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910239185.4A CN110045779B (en) | 2019-03-27 | 2019-03-27 | Voltage selection circuit and method |
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| CN110045779A true CN110045779A (en) | 2019-07-23 |
| CN110045779B CN110045779B (en) | 2020-06-09 |
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| CN201910239185.4A Expired - Fee Related CN110045779B (en) | 2019-03-27 | 2019-03-27 | Voltage selection circuit and method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110320957A (en) * | 2019-08-05 | 2019-10-11 | 北京中科银河芯科技有限公司 | A kind of voltage selecting circuit |
| CN110518687A (en) * | 2019-08-06 | 2019-11-29 | 成都锐成芯微科技股份有限公司 | A kind of power supply automatic switchover circuit |
| CN115454199A (en) * | 2022-09-20 | 2022-12-09 | 圣邦微电子（北京）股份有限公司 | Current selection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110320957A (en) * | 2019-08-05 | 2019-10-11 | 北京中科银河芯科技有限公司 | A kind of voltage selecting circuit |
| CN110320957B (en) * | 2019-08-05 | 2022-01-07 | 北京中科银河芯科技有限公司 | Voltage selection circuit |
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| CN115454199A (en) * | 2022-09-20 | 2022-12-09 | 圣邦微电子（北京）股份有限公司 | Current selection circuit |
| CN115454199B (en) * | 2022-09-20 | 2024-02-06 | 圣邦微电子（北京）股份有限公司 | Current selection circuit |
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