CN110045779B - Voltage selection circuit and method - Google Patents

Voltage selection circuit and method Download PDF

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CN110045779B
CN110045779B CN201910239185.4A CN201910239185A CN110045779B CN 110045779 B CN110045779 B CN 110045779B CN 201910239185 A CN201910239185 A CN 201910239185A CN 110045779 B CN110045779 B CN 110045779B
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circuit
voltage
source
tube
pmos tube
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CN110045779A (en
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邹志革
吴文海
徐文韬
皮庆广
童乔凌
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Huazhong University of Science and Technology
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

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Abstract

The invention discloses a voltage selection circuit and a method, wherein the circuit comprises a peak current source circuit, a hysteresis comparison circuit and a voltage output circuit, wherein the input end of the peak current source circuit is connected with a power voltage, and the output end of the peak current source circuit is connected with the hysteresis comparison circuit and is used for generating a bias current source; the input end of the hysteresis comparison circuit is connected with the first input voltage source and the second input voltage source, and the output end of the hysteresis comparison circuit is connected with the voltage output circuit and used for generating a logic level; the voltage output circuit selectively outputs the first input voltage source or the second input voltage source according to the logic level. In order to quickly and accurately select a lower or higher voltage of two voltage sources as an output, the peak current source circuit provides bias current, so that the static power consumption of the circuit is lower; the hysteresis comparison circuit input from the source end eliminates the Miller effect of parasitic capacitance, and has the advantages of high response speed, strong noise interference resistance and the like; the output circuit has simple structure and saves chip area.

Description

Voltage selection circuit and method
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a voltage selection circuit and a voltage selection method.
Background
The field of analog power supply technology often employs a voltage selection circuit to compare two input voltages, thereby selecting the higher or lower input voltage as the output voltage. For example, an LDO circuit with a reverse input current protection function often includes a voltage selection circuit therein to ensure that the substrate potential of the power transistor is always at an appropriate potential during operation. Otherwise, when the input voltage suddenly drops and the output end has voltage spikes and other abnormal conditions, the parasitic body diode in the power tube may be conducted, so that the phenomenon of current backflow is generated, and the chip and the power supply battery are greatly damaged.
Fig. 1 shows a voltage selection circuit proposed in the chinese patent application integrated circuit and voltage selection circuit (application number: 201510292905.5, application date: 2015, 5, month and 26), which has a simple structure and only includes two P-type MOS transistors P1 and P2, but when the difference between two input voltages to be compared is small, both P1 and P2 are not turned on, and at this time, the circuit cannot select a proper voltage as an output. In addition, in some conventional voltage selection circuits, a gate-input hysteresis comparator is generally used as a voltage comparison circuit, and the miller effect of the parasitic capacitance of the input end reduces the bandwidth of the comparator and increases the response time of the comparator.
Disclosure of Invention
The present invention provides a voltage selection circuit and method, which is used to solve the problem in the prior art that when the voltages of two input power supplies are relatively close, the appropriate input power supply voltage cannot be correctly selected as the output.
To achieve the above object, according to an aspect of the present invention, there is provided a voltage selection circuit including a peak current source circuit, a hysteresis comparison circuit, and a voltage output circuit; the input end of the peak current source circuit is connected with the power voltage, and the output end of the peak current source circuit is connected with the hysteresis comparison circuit and is used for generating a bias current source; the input end of the hysteresis comparison circuit is connected with the first input voltage source and the second input voltage source, and the output end of the hysteresis comparison circuit is connected with the voltage output circuit and used for generating a logic level; the voltage output circuit selectively outputs the first input voltage source or the second input voltage source according to the output logic level.
Preferably, the bias current source is mirrored through the hysteresis comparison circuit to obtain a first mirror current source, a second mirror current source and a third mirror current source.
Preferably, the hysteresis comparison circuit includes a source terminal input pair, and the source terminal input pair compares the magnitudes of the first input voltage source and the second input voltage source by using the first mirror current source and the second mirror current source as bias currents.
Preferably, the logic level is used to determine whether to introduce a third mirror current source as a load in the hysteresis comparison circuit.
Preferably, the voltage output circuit comprises two PMOS tubes, and the switch is controlled by a logic level.
According to another aspect of the present invention, there is provided a voltage selection method based on the above circuit, including:
inputting power supply voltage, and obtaining a bias current source through a peak current source circuit;
the bias current source obtains a logic level of the control voltage output through hysteresis comparison;
the logic level control circuit switches to select the output voltage.
Preferably, the selected output voltage may be a high voltage or a low voltage.
Through the technical scheme of the invention, the following beneficial effects can be achieved:
1. the peak current source circuit provides bias current, so the static power consumption of the circuit is lower, the circuit can still stably work within a wider power voltage range, and the circuit has a turn-off function;
2. the hysteresis comparison circuit adopted by the invention adopts the source end as the input, so that the Miller effect of the parasitic capacitance can be eliminated, the bandwidth of the comparator is improved, and the response time is reduced;
3. according to the invention, the influence of noise can be reduced through the hysteresis introduced by the third mirror current source, and the anti-interference capability of the circuit is improved;
4. the voltage output circuit adopted by the invention only comprises two PMOS switching tubes, the structure is simple, and the chip area is saved.
Drawings
FIG. 1 is a schematic diagram of a voltage selection circuit of the prior art;
FIG. 2 is a block diagram of a voltage selection circuit according to the present invention;
FIG. 3 is a schematic diagram of a low voltage selection circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a high voltage selection circuit according to another embodiment of the present invention;
description of reference numerals:
100. 200, 300, 400: voltage selection circuit, 201: supply voltage V DD202, 302, 402: peak current source circuit, 203: bias current IBIASAnd 203A: first mirror current source I1And 203B: second mirror current source I2And 203C: third mirror current source I3204, 304, 404: hysteresis comparison circuitWay, 206, 306, 406: voltage output circuit, 207, 307, 407: source input pair, 208, 210, 308, 310, 408, 410: output logic level of hysteresis comparison circuit, 209: a first input voltage source V1,213: a second input voltage source V2,215: output voltage source V out222, 333, 444: multi-way current mirror, 301, 401: first hysteresis inverter inv1, 303, 403: a second inverter inv 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
FIG. 2 shows a block diagram of a voltage selection circuit 200 according to the present invention, which includes a peak current source circuit 202, a source-side input hysteresis comparator circuit 204, and a voltage output circuit 206, in some embodiments, the voltage selection circuit 200 is configured to select a first input voltage V from a first input voltage V1And a second input voltage V2Selects the appropriate one to deliver to the output.
Specifically, the input terminal of the peak current source circuit 202 is connected to the power voltage VDDThe output end is connected with the hysteresis comparison circuit 204 and the output end is connected with the hysteresis comparison circuit at a wider power supply voltage VDDCan still stably work within the range, and finally generates a bias current source IBIAS(ii) a A first input voltage source V1And a second input voltage source V2The input end of the hysteresis comparison circuit is connected with the input end of the voltage output circuit, the output end of the hysteresis comparison circuit is connected with the voltage output circuit, and the bias current source I is mirrored through a plurality of current mirrorsBIASObtaining a first mirror current source I1A second mirror current source I2And a third mirror current source I3The source terminal input pair utilizes a first mirror current source I1And a second mirror current source I2Comparing the first input voltage source V as a bias current with the active load1And a second input voltage source V2The output logic levels 208 and 210; the comparator circuit outputs a logic level 2 according to the output08 judges whether to introduce a third mirror current source I3Forming hysteresis; the voltage output circuit selectively outputs either the first input voltage source or the second input voltage source according to the output logic level 210.
Fig. 3 is a schematic diagram of a low voltage selection circuit, it should be noted that the circuit diagram shown in fig. 3 is only one of various embodiments of the voltage selection circuit, and fig. 4 is another embodiment of the voltage selection circuit. The peak current source circuit 302 of the voltage selection circuit 300 in the embodiment shown in fig. 3 includes: the first, second and third PMOS tubes P1, P2 and P3, the first and second NMOS tubes N1 and N2 and the first resistor R1, the source of the first PMOS tube P1 is connected with the power supply VDDThe grid electrode of the second PMOS tube P2 is connected with an enable signal EN0, the grid electrode of the second PMOS tube P2 is grounded, the source electrode of the second PMOS tube P1 is connected with the drain electrode of the first PMOS tube P1, the drain electrode of the second PMOS tube P1 is in short circuit with the grid electrode of the first NMOS tube N1 and is connected to the positive end of a first resistor R1, and the source electrode of the third PMOS tube P3 is connectedDDThe grid electrode and the drain electrode are in short circuit and are connected to the drain electrode of the second NMOS tube N2, the drain electrode of the first NMOS tube N1 and the grid electrode of the second NMOS tube N2 are in short circuit and are connected to the negative end of the first resistor R1, and the source electrodes of the first NMOS tube N1 and the second NMOS tube N2 are grounded.
More specifically, for the peak current mirror circuit 302 shown in fig. 3, the gate of the first PMOS transistor P1 is connected to the enable signal EN0, and the high or low of the enable signal EN0 can control the switching of the whole circuit. The second PMOS tube P2 is an inverse ratio tube, the width-length ratio is very small, and the first NMOS tube N1 and the second NMOS tube N2 are ensured to work in a subthreshold region, so that the static power consumption is reduced; the third PMOS tube P3 and the fourth PMOS tube P4 have the function of biasing current IBIASConversion to bias voltage VBIAS. The relationship of two sets of currents passing through the first NMOS transistor N1 and the second NMOS transistor N2 has a peak current, which can be derived according to the sub-threshold region formula:
Figure GDA0002451782330000051
wherein n is a subthreshold constant, usually 1.3-1.5, IN1And IN2Two sets of current (W/L) respectively flowing through the first NMOS transistor N1 and the second NMOS transistor N2N1And (W/L)N2The width-to-length ratios of the first NMOS transistor N1 and the second NMOS transistor N2, respectively.
Next, in the embodiment shown in fig. 3, the hysteresis comparator 304 input to the source terminal of the voltage selection circuit 300 includes fourth, fifth and sixth PMOS transistors P4, P5 and P6, third, fourth and fifth NMOS transistors N3, N4 and N5, a second resistor R2, a third resistor R3, a first hysteresis inverter inv1, a second hysteresis inverter inv2, and sources of the fourth to sixth PMOS transistors P4 to P6 connected to the power supply VDDThe gates of the fourth to sixth PMOS transistors P4-P6 are all connected to the gate of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4 is shorted with the drain and gate of the third NMOS transistor N3 and connected to the gate of the fourth NMOS transistor N4, the drain of the fifth PMOS transistor P5, the drain of the fourth NMOS transistor N4, and the source of the fifth NMOS transistor N5 are shorted and connected to the input terminal of the first hysteresis inverter inv1, the drain of the sixth PMOS transistor P6 is connected to the drain of the fifth NMOS transistor N5, the output terminal of the first hysteresis inverter inv1 is connected to the input terminal of the second hysteresis inverter inv2, the output terminal of the second hysteresis inverter inv2 is connected to the gate of the fifth NMOS transistor N5, the sources of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the positive terminals of the second resistor and the third resistor, and the negative terminal of the third resistor are connected to the voltage source V of the first input resistor, respectively1And a second input voltage source V2。
It should be noted that although the multiplexing current mirror 333 is a basic current mirror in the embodiment shown in fig. 3, it may be considered any of various forms of current mirrors, such as a self-biased cascode current mirror.
In the embodiment shown in fig. 3, the fourth PMOS transistor P4 mirrors the peak current source IBIASPost-generated first mirror current source I1As the bias current and the active load of the third NMOS transistor N3; fifth PMOS pipe P5 mirror peak current source IBIASPost-generation and first mirror current source I1Equal second mirror current source I2As the bias current and the active load of the fourth NMOS transistor N4. When two input voltage sources V1＝V2When the current flowing through the third NMOS transistor N3 and the current flowing through the fourth NMOS transistor N4 are completely the same, the circuit is in a balanced state; when V is1＜V2While, the gate voltage V of the third NMOS transistor N3XWill be mixed with V1When the synchronization is reduced, the gate voltage of the fourth NMOS transistor N4 is also pulled low, and the current flowing through the fourth NMOS transistor N4 is reduced, and the voltage at the net0 point is pulled high. In the same way, when V1＞V2While, the gate voltage V of the third NMOS transistor N3XWill be mixed with V1When the synchronization is increased, the gate voltage of the fourth NMOS transistor N4 is also pulled high, and the current flowing through the fourth NMOS transistor N4 is increased, so that the voltage at the net0 point is pulled low. The first hysteretic inverter inv1 shapes the voltage waveform at net0 point, prevents the occurrence of intermediate state, and outputs logic level 308; the second hysteretic inverter inv2 outputs a logic level 310 that is the inverse of logic level 308. The logic level 310 can control the on and off of the fifth NMOS transistor N5 to determine whether to introduce the third mirror current source I3Eventually forming a hysteresis.
For the hysteresis comparison circuit 304, it is further described that if the first input voltage source V is provided1Fixed, the gate voltage V of the third NMOS transistor N3 and the fourth NMOS transistor N4xIs also relatively fixed when V2＜V1And V is2The current flowing through the fourth NMOS transistor N4 gradually decreases, and when the output logic levels 308 and 310 just jump, the following relationship exists:
Figure GDA0002451782330000061
wherein munDenotes the electron mobility, COXExpressing the capacitance of gate oxide per unit area, VTNWhich represents the threshold voltage of the MOS transistor,
Figure GDA0002451782330000062
represents the width-length ratio, V, of the fourth NMOS transistor N4xRepresenting a first input voltage source V1A gate voltage, V, of a timed fourth NMOS transistor N42H、V2LRespectively represent a first input voltage source V1A timing comparator second input voltage source V2High transition threshold, low transition threshold.
If the first input voltage source V is1Fixation, V2＞V1And V is2Decreasing, when the output logic levels 308 and 310 just transition, the following relationship exists:
Figure GDA0002451782330000063
for the hysteresis comparator 304, the third mirror current source I is changed3Can adjust the hysteresis space.
Next, in the embodiment shown in fig. 3, the voltage output circuit 306 of the voltage selection circuit 300 includes a seventh PMOS transistor P7 and an eighth PMOS transistor P8. The gates of the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are respectively connected to the output logic circuits 310 and 308 of the second hysteretic inverter and the first hysteretic inverter, and the source and the substrate of the seventh PMOS transistor P7 are connected to the input second input voltage source V2The source and the substrate of the eighth PMOS tube P8 are connected to the input first input voltage source V1The drains of the seventh PMOS tube P7 and the eighth PMOS tube P8 are connected to output Vout. When V is2＜V1When the output logic level 308 is high, the output logic level 310 is low, the seventh PMOS transistor P7 is turned on, the eighth PMOS transistor P8 is turned off, and V is set toout＝V2(ii) a On the contrary, when V2＞V1When the output logic level 308 is low, the output logic level 310 is high, the seventh PMOS transistor P7 is turned off, the eighth PMOS transistor P8 is turned on, and V is setout＝V1. Therefore, the voltage output circuit 306 in the embodiment shown in fig. 3 is a low voltage output circuit.
As mentioned above, the voltage selection circuit 200 can also be implemented by the embodiment shown in FIG. 4. The voltage selection circuit 400 shown in fig. 4 is substantially similar to the voltage selection circuit 300, with the main difference being the voltage output circuit. In the embodiment shown in fig. 4, the voltage output circuit 406 includes a seventh PMOS transistor P7 and an eighth PMOS transistor P8. The gates of the seventh PMOS transistor P7 and the eighth PMOS transistor P8 are respectively connected to the output logic levels 410 and 408 of the second hysteretic inverter and the first hysteretic inverter, and the source of the seventh PMOS transistor P7 is connected to the input voltage source V1The source of the eighth PMOS pipe P8 is connected with the input voltage source V2Seventh and eighth PMOS transistors P7 andthe drain electrode of the PMOS pipe P8 is connected with the substrate to output Vout. When V is2＜V1When the output logic level 408 is high, the output logic level 410 is low, P7 is turned on, P8 is turned off, and V is setout＝V1(ii) a On the contrary, when V2＞V1When the output logic level 408 is low, the output logic level 410 is high, P7 is turned off, P8 is turned on, and V is setout＝V2. Thus, the voltage output circuit 406 in the embodiment shown in FIG. 4 is a high voltage output circuit.
It should be noted that the circuit diagrams of all the above embodiments are based on a standard CMOS process, and the substrates of the PMOS transistors in the peak current source circuit and the hysteresis comparison circuit are connected with a power supply VDDThe PMOS tube substrates in the low-voltage output circuit are all in short circuit with the source electrode thereof, and the PMOS tube substrates in the high-voltage output circuit are all connected with the output voltage VoutAnd the substrates of all the NMOS tubes are grounded. If based on other processes, the potential of the MOS tube substrate can be easily changed. For example, it should be understood that when a double well CMOS process is employed, the NMOS transistor substrate may be shorted to its source.
In summary, the present invention can quickly and accurately select the lower or higher voltage of the two input voltage sources as the output voltage. Meanwhile, the invention has the advantages of low static power consumption, wide working voltage range, high response speed, strong anti-interference capability, simple structure and the like.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (7)

1. A voltage selection circuit is characterized by comprising a peak current source circuit, a hysteresis comparison circuit and a voltage output circuit; the input end of the peak current source circuit is connected with the power voltage, and the output end of the peak current source circuit is connected with the hysteresis comparison circuit and is used for generating bias current; the input end of the hysteresis comparison circuit is connected with a first input voltage source and a second input voltage source, and the output end of the hysteresis comparison circuit is connected with the voltage output circuit and used for generating a logic level; the voltage output circuit selectively outputs a first input voltage source or a second input voltage source according to the logic level;
the peak current source circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a first resistor, wherein the source electrode of the first PMOS tube is connected with a power voltage, the grid electrode of the first PMOS tube is connected with an enable signal, the grid electrode of the second PMOS tube is grounded, the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is in short circuit with the grid electrode of the first NMOS tube and is connected to the positive end of the first resistor, the source electrode of the third PMOS tube is connected with the power voltage, the grid electrode of the third PMOS tube is in short circuit with the drain electrode of the second NMOS tube and is connected to the negative end of the first resistor, and the source;
the hysteresis comparison circuit comprises a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second resistor, a third resistor, a first hysteresis inverter and a second hysteresis inverter, wherein the source electrodes of the fourth PMOS tube to the sixth PMOS tube are connected with power supply voltage, the grid electrodes of the fourth PMOS tube to the sixth PMOS tube are connected with the grid electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube is in short circuit with the drain electrode and the grid electrode of the third NMOS tube and is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fifth PMOS tube, the drain electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are in short circuit and are connected with the input end of the first hysteresis inverter, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the output end of the first hysteresis inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the grid electrode of the fifth NMOS tube, the source electrodes of the third NMOS tube and the fourth NMOS tube are respectively connected with the positive end, the negative ends of the second resistor and the third resistor are respectively connected with a first input voltage source and a second input voltage source.
2. The circuit of claim 1, wherein the bias current is mirrored through the hysteresis comparison circuit to obtain a first mirrored current source, a second mirrored current source, and a third mirrored current source.
3. The circuit of claim 2, wherein the hysteresis comparison circuit comprises a source input pair that compares the magnitude of a first input voltage source and a second input voltage source using the first mirror current source and the second mirror current source as bias currents.
4. A circuit according to claim 1 or 2, wherein the logic level is used to determine whether to introduce a third mirror current source as a load in the hysteresis comparator circuit.
5. The circuit of claim 1, wherein the voltage output circuit comprises two PMOS transistors, the switches being controlled by the logic level.
6. A voltage selection method based on the circuit of any one of claims 1 to 5, comprising:
inputting power supply voltage, and obtaining bias current through a peak current source circuit;
the bias current obtains a logic level of control voltage output through hysteresis comparison;
the logic level control circuit switches to select the output voltage.
7. The method of claim 6, wherein the selected output voltage is either a high voltage output or a low voltage output.
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CN110320957B (en) * 2019-08-05 2022-01-07 北京中科银河芯科技有限公司 Voltage selection circuit
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US7298181B2 (en) * 2005-12-06 2007-11-20 Pulsecore Semiconductor Corp. Highest supply selection circuit
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CN104767518A (en) * 2015-04-20 2015-07-08 成都岷创科技有限公司 Substrate switching circuit based on CMOS
US10281502B2 (en) * 2017-05-31 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Maximum voltage selection circuit
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