CN216794966U

CN216794966U - Power-on reset circuit

Info

Publication number: CN216794966U
Application number: CN202121055233.3U
Authority: CN
Inventors: 赖练章; 马文鑫
Original assignee: Shanghai Biyang Technology Co ltd
Current assignee: Suzhou Huaxin Semiconductor Technology Co ltd
Priority date: 2021-05-18
Filing date: 2021-05-18
Publication date: 2022-06-21
Anticipated expiration: 2031-05-18

Abstract

The utility model provides a power-on reset circuit, which comprises a current mirror circuit for providing bias, a first detection circuit for comparing reference voltage with set threshold voltage, a second detection circuit for detecting the reference voltage and power supply voltage, a Schmitt trigger for hysteresis and a phase inverter for driving, wherein the input end of the first detection circuit is connected with the output end of the current mirror circuit; the first detection circuit and the second detection circuit are respectively arranged at the input end and the output end of the Schmitt trigger, and the phase inverter is arranged at the output end of the second detection circuit; the first detection circuit and the second detection circuit are both connected with a reference voltage Vref. The Vref is larger than the threshold voltage of the NMOS transistor N3 and the threshold voltage of the PMOS transistor P9, so that the influence of temperature and a process corner is reduced; i3 is adjusted through a resistor R2 and a resistor R3 to control the voltage of power-on reset; VI N first turns on P4, P5 and P8, allowing Vref to be active later, so that Vref is only active after the supply voltage is up to specification.

Description

Power-on reset circuit

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to a power-on reset circuit capable of reducing the influence of temperature and process corners.

Background

In the prior art, as shown in fig. 2, the power-on reset circuit has little correlation between Vref and the power supply voltage; the circuit is greatly influenced by temperature; the circuit is greatly influenced by the process angle; the voltage cannot be detected simultaneously whether threshold voltage values of a PMOS (P-Channel Metal Oxide Semiconductor) and an NMOS (N-Channel Metal Oxide Semiconductor) are met; and the voltage value of the power-on reset can not be regulated and controlled.

SUMMERY OF THE UTILITY MODEL

Aiming at the technical problems in the prior art, the utility model provides the power-on reset circuit, and the Vref reduces the influence of temperature and process angle by being larger than the threshold voltage of the NMOS transistor N3 and the PMOS transistor P9; i3 is adjusted through a resistor R2 and a resistor R3, so that the voltage of power-on reset is controlled; VIN first turns on PMOS transistors P4, P5, and P8, allowing Vref to be active later, so that Vref is functional after the supply voltage is up to specification.

The technical scheme for solving the technical problems is as follows: a power-on reset circuit comprises a current mirror circuit for providing bias, a first detection circuit for comparing a reference voltage with a set threshold voltage, a second detection circuit for detecting the reference voltage and a power supply voltage, a Schmitt trigger for hysteresis and an inverter for driving, wherein the input end of the first detection circuit is connected with the output end of the current mirror circuit; the first detection circuit and the second detection circuit are respectively arranged at the input end and the output end of the Schmitt trigger, and the phase inverter is arranged at the output end of the second detection circuit; the first detection circuit and the second detection circuit are both connected with a reference voltage Vref.

Preferably, the current mirror circuit comprises a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a resistor R1, an NMOS tube N1 and an NMOS tube N2; the PMOS tube P1 and the resistor R1 are connected in series to serve as current bias, and the PMOS tube P2, the PMOS tube P3, the NMOS tube N1 and the NMOS tube N2 serve as current mirrors.

Preferably, the first detection circuit comprises a PMOS tube P4, a PMOS tube P5, an NMOS tube N3 and an NMOS tube N4; the PMOS tube P4 is connected with the NMOS tube N3 in series, the grid electrode of the NMOS tube N3 is connected with a reference voltage Vref, the grid electrode of the PMOS tube P4 is connected with the grid electrode of the PMOS tube P3, and the drain electrode of the PMOS tube P4 is connected with the grid electrode of the NMOS tube N4; the PMOS tube P5 is connected with the NMOS tube N4 in series, the grid electrode of the PMOS tube P5 is connected with the grid electrode of the PMOS tube P3, and the drain electrode of the PMOS tube P5 is connected with the input end of the Schmitt trigger;

the second detection circuit comprises a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, a PMOS tube P10, an NMOS tube N5, an NMOS tube N6, an NMOS tube N7, an NMOS tube N8, a resistor R2 and a resistor R3; the output end of the Schmidt trigger is connected with the grid electrode of a PMOS tube P6 and the grid electrode of an NMOS tube N5, the drain electrode of the NMOS tube N5 is connected with the source electrode of the PMOS tube P10, and the PMOS tube P6 and a resistor R2 are connected with the PMOS tube P7 in parallel; the PMOS transistor P7, the resistor R3, the PMOS transistor P10 and the NMOS transistor N7 are connected in series, the PMOS transistor P9 is connected in series with the NMOS transistor N6, the grid electrode of the PMOS transistor P9 is connected with the drain electrode of the PMOS transistor P9, the source electrode of the PMOS transistor P9 is connected with the reference voltage Vref, and the grid electrode of the NMOS transistor N6 is connected with the grid electrode of the NMOS transistor N1; the drain electrode of the PMOS tube P10 and the drain electrode of the NMOS tube N7 are both connected with the grid electrode of the NMOS tube N8, the grid electrode of the NMOS tube N7 is connected with the grid electrode of the NMOS tube N1, the grid electrode of the PMOS tube P10 is connected with the grid electrode of the NMOS tube N9, the PMOS tube P8 and the NMOS tube N8 are connected in series, and the grid electrode of the PMOS tube P8 is connected with the grid electrode of the PMOS tube P3.

Preferably, the inverter comprises an inverter Inv1 and an inverter Inv2, and the drain of the NMOS transistor N8 and the source of the PMOS transistor P3 are both connected to the input terminal of the inverter Inv 1; the input end of the inverter Inv2 is connected to the output end of the inverter Inv1, and the output end of the inverter Inv2 is connected to the power-on reset interface POR.

The utility model has the beneficial effects that: the utility model provides a power-on reset circuit, wherein Vref reduces the influence of temperature and process angle by being larger than the threshold voltage of an NMOS transistor N3 and a PMOS transistor P9; i3 is adjusted through a resistor R2 and a resistor R3, so that the voltage of power-on reset is controlled; VIN first turns on PMOS transistors P4, P5, and P8, allowing Vref to be active later, so that Vref is functional after the supply voltage is up to specification.

Drawings

Fig. 1 is a schematic block diagram of the circuit of the present invention.

Fig. 2 is a schematic block diagram of a prior art circuit.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, unless otherwise specified and limited, it is to be noted that the terms "mounted," "connected," and "connected" are to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, a communication between two elements, a direct connection, or an indirect connection via an intermediate medium, and specific meanings of the terms may be understood by those skilled in the art according to specific situations.

As shown in fig. 1, the present embodiment discloses a power-on reset circuit, which includes a current mirror circuit providing a bias, a first detection circuit for comparing a reference voltage with a set threshold voltage, an input terminal of the first detection circuit being connected to an output terminal of the current mirror circuit, a second detection circuit for detecting the reference voltage and a power supply voltage, a schmitt trigger for hysteresis, and an inverter for driving; the first detection circuit and the second detection circuit are respectively arranged at the input end and the output end of the Schmitt trigger, and the phase inverter is arranged at the output end of the second detection circuit; the first detection circuit and the second detection circuit are both connected with a reference voltage Vref.

The following explains the working principle of the embodiment with reference to the above technical solutions of the embodiment: in this embodiment, the PMOS transistors P1 and R1 serve as current sources to bias the PMOS transistor P2. The PMOS tube P2, the PMOS tube P3, the NMOS tube N1 and the NMOS tube N2 form a current mirror, the grid electrode of the PMOS tube P3 is connected with the grid electrodes of the PMOS tube P4, the PMOS tube P5 and the PMOS tube P8, the grid electrode of the NMOS tube N1 is connected with the grid electrodes of the NMOS tube N6 and the NMOS tube N7, and when the current mirror is conducted, the power supply voltage is detected to be larger than the threshold voltage of the PMOS tube P3 and the threshold voltage of the NMOS tube N2. The Vref voltage is connected to the gate of NMOS transistor N3 and the gate of PMOS transistor P9. When Vref is greater than the threshold voltage of NMOS transistor N3: NMOS transistor N3 is conducted, a channel is formed by PMOS transistor P4 and NMOS transistor N3, the potential of a node 1 is charged high, NMOS transistor N4 is conducted, a channel is formed by NMOS transistor N4 and NMOS transistor P5, the point of a node 2 is charged high, and a Schmidt trigger outputs a low potential. When Vref is less than the threshold voltage of NMOS transistor N3: the NMOS transistor N3 is turned off, the PMOS transistor P4 and the NMOS transistor N3 do not form a channel, the potential of a node 1 is low (the PMOS transistor P4 is charged slowly), the NMOS transistor N4 is also turned off at the moment, the PMOS transistor P5 and the NMOS transistor N4 do not form a channel, the point of a node 2 is low (the PMOS transistor P5 is charged slowly), and the Schmidt trigger outputs high potential. When Vref is larger than the threshold voltage of PMOS transistor P9: the PMOS transistor P9 is conducted to form a path with the NMOS transistor N6, the current flowing through the path between the PMOS transistor P9 and the NMOS transistor N6 is I1(I is (1/2) uC (W/L) (Vgs-Vth) ^2), the current I2 of the path between the PMOS transistor P10 and the NMOS transistor N7 on the other side of the current mirror is equal to I1, and the voltage of the node 5 is equal to the voltage of Vref. When Vref is less than the threshold voltage of PMOS transistor P9: the PMOS transistor P9 is turned off, no current is generated, the PMOS transistor P10 is also turned off at this time, the voltage of the node 6 is low, the NMOS transistor N8 is turned off, the node 7 is charged by P8, and the potential gradually rises. When the schmitt trigger output is high: the NMOS tube N5 is connected, the PMOS tube P6 is disconnected, the PMOS tubes P7 and R3 and the NMOS tube N5 form a passage, the current directly flows to the ground, the point 6 of the node is low, the NMOS tube N8 is disconnected, and the node 7 is slowly charged by the P8. When the schmitt trigger output is low: the PMOS transistor P6 is turned on, the N5 is turned off, the PMOS transistors P6, R2, R3, the PMOS transistor P10 and the NMOS transistor N7 form a path, the current mirror knows that I1 is I2, the node 5 is Vref, and the series circuit current of the PMOS transistors P6, R2 and R3 is I3 vin (t)/(R2+ R3). Known from kirchhoff's law: when I3 is larger than I2, the node 6 is charged high, the circuit of the PMOS tube P8 and the NMOS tube N8 is conducted, and the node 7 is at low voltage; when I3< ═ I2, node 6 is pulled low, NMOS transistor N8 is turned off, and node 7 is slowly charged by PMOS transistor P8.

In conclusion: the Vref is larger than the threshold voltage of the NMOS transistor N3 and the threshold voltage of the PMOS transistor P9, so that the influence of temperature and a process corner is reduced;

i3 is regulated through R2 and R3, so that the voltage of power-on reset is controlled; VIN first turns on PMOS transistor P4, PMOS transistor P5 and PMOS transistor P8, allowing Vref activity to function later, so that Vref can only function after the supply voltage meets the requirements.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the utility model have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the utility model, the scope of which is defined by the claims and their equivalents.

Claims

1. A power-on reset circuit is characterized by comprising a current mirror circuit for providing bias, a first detection circuit for comparing a reference voltage with a set threshold voltage, a second detection circuit for detecting the reference voltage and a power supply voltage, a Schmitt trigger for hysteresis and an inverter for driving, wherein the input end of the first detection circuit is connected with the output end of the current mirror circuit; the first detection circuit and the second detection circuit are respectively arranged at the input end and the output end of the Schmitt trigger, and the phase inverter is arranged at the output end of the second detection circuit; the first detection circuit and the second detection circuit are both connected with a reference voltage Vref.

2. A power-on reset circuit as claimed in claim 1, wherein the current mirror circuit comprises a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, a resistor R1, an NMOS transistor N1, and an NMOS transistor N2; the PMOS tube P1 and the resistor R1 are connected in series to serve as current bias, and the PMOS tube P2, the PMOS tube P3, the NMOS tube N1 and the NMOS tube N2 serve as current mirrors.

3. The power-on reset circuit as claimed in claim 2, wherein the first detection circuit comprises a PMOS transistor P4, a PMOS transistor P5, an NMOS transistor N3 and an NMOS transistor N4; the PMOS tube P4 is connected with the NMOS tube N3 in series, the grid electrode of the NMOS tube N3 is connected with a reference voltage Vref, the grid electrode of the PMOS tube P4 is connected with the grid electrode of the PMOS tube P3, and the drain electrode of the PMOS tube P4 is connected with the grid electrode of the NMOS tube N4; the PMOS tube P5 is connected with the NMOS tube N4 in series, the grid electrode of the PMOS tube P5 is connected with the grid electrode of the PMOS tube P3, and the drain electrode of the PMOS tube P5 is connected with the input end of the Schmitt trigger;

4. The power-on reset circuit as claimed in claim 3, wherein the inverter comprises an inverter Inv1 and an inverter Inv2, and the drain of the NMOS transistor N8 and the source of the PMOS transistor P3 are both connected to the input terminal of the inverter Inv 1; the input end of the inverter Inv2 is connected to the output end of the inverter Inv1, and the output end of the inverter Inv2 is connected to the power-on reset interface POR.