CN114553204B - Driving circuit and method of high-side N-type power MOS - Google Patents
Driving circuit and method of high-side N-type power MOS Download PDFInfo
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- CN114553204B CN114553204B CN202210153028.3A CN202210153028A CN114553204B CN 114553204 B CN114553204 B CN 114553204B CN 202210153028 A CN202210153028 A CN 202210153028A CN 114553204 B CN114553204 B CN 114553204B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0036—Means reducing energy consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0054—Gating switches, e.g. pass gates
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a driving circuit and a method of a high-side N-type power MOS (metal oxide semiconductor), belonging to the technical field of power electronics, and comprising a current bias unit, a floating voltage generation unit, a power tube charging current adjustment unit and a power tube charging current adjustment unit, wherein the current bias unit generates bias currents required by the floating voltage generation unit and the power tube charging current adjustment unit; the floating voltage generating unit generates bias voltages required by the power tube charging unit and the power tube charging current adjusting unit; the power tube charging current adjusting unit judges whether the grid voltage of the high-side N-type MOS tube exceeds the voltage of the Miller platform, if so, the power tube charging unit is driven to amplify the current of the grid of the high-side N-type MOS tube, and otherwise, the power tube charging unit is driven to charge the grid of the high-side N-type MOS tube according to preset current; the power tube charging unit charges the grid electrode of the high-side N-type MOS tube; the power tube discharging unit discharges the grid electrode of the high-side N-type MOS tube; the high-side N-type MOS transistor is driven by low resistance, the switching loss is reduced, and the anti-interference performance of the high-side NMOS is improved.
Description
Technical Field
The invention belongs to the technical field of power electronics, and particularly relates to a driving circuit and a driving method of a high-side N-type power MOS.
Background
As shown in fig. 1, a high-side NMOS and a load are connected in series in sequence between a power supply and a reference ground; the control end of the high-side NMOS is connected with a drive circuit; the high side NMOS is used to drive resistive, inductive loads. In practical applications, in order to reduce the electromagnetic interference caused by the high-side NMOS, the slew rate of the switching point needs to be controlled, that is, Δ V/Δ t, where Δ V is the voltage difference and Δ t is the variation time.
As shown in fig. 2, which shows the miller plateau effect during the turn-on phase of the high-side NMOS, it can be seen that the voltage variation of the drain occurs during a plateau phase when the gate voltage is higher than the threshold voltage Vth, as shown in fig. 2 at the t3 phase.
Fig. 3 shows a method for implementing the driving circuit in fig. 1. M0 is a high-side NMOS tube which needs to be driven. MP0, MP1, MP2 provide the bias current required by the driver circuit. The current of MP1 flows through Zener diode D0 to generate a bias voltage of SOURCE + 5V. The current mirror composed of MN0 and MN1 is used for providing bias current of the input stages of MN2 and MN3, and the current mirror composed of MP3 and MP4 is a load of the input stages of MN2 and MN 3. R0 is used to turn off M0. The working principle is as follows: when M0 needs to be turned on, the Ibias current is supplied to MP0 for driving. At this time, the VGS voltage of M0 is 0V, and the charging current of the gate of M0 is determined by the current mirror ratios of MP0/MP2, MN0/MN1, MP3/MP4, the Ibias current and the discharging resistor R0. When the gate voltage of M0 is charged to VS +5V, the charging is stopped.
In the driving circuit shown in fig. 3, in order to control the slew rate of the switching point, i.e., Δ V/Δ t (at stage t 3), the charging current is fixed to a predetermined design value, which causes two problems. Firstly, after the period t3, the drive current of the gate is insufficient, the high-side NMOS is not completely turned on, so that the on-resistance is increased, and the power consumption of the high-side NMOS is increased.
Disclosure of Invention
In order to solve the above-mentioned drawbacks, the present invention provides a driving circuit and method for a high-side N-type power MOS.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a driver circuit for a high side N-type power MOS, comprising:
the current bias unit is used for generating bias current required by the floating voltage generation unit and the power tube charging current adjustment unit; the current bias unit comprises a current mirror formed by a first switching tube, a second switching tube and a third switching tube, wherein the first ends of the first switching tube, the second switching tube and the third switching tube are all connected with an external power supply, the second end of the first switching tube is connected with an external current source, and the external current source is all connected with the control ends of the first switching tube, the second switching tube and the third switching tube;
the floating voltage generating unit is used for generating bias voltages required by the power tube charging unit and the power tube charging current adjusting unit; the floating voltage generating unit comprises a first voltage-stabilizing tube and a resistance voltage-dividing circuit connected with the first voltage-stabilizing tube in parallel, wherein the first end of the first voltage-stabilizing tube is connected with the second end of the second switch tube, the second end of the first voltage-stabilizing tube is connected with the source electrode of the high-side N-type MOS tube, and the resistance voltage-dividing circuit comprises a first resistor and a second resistor which are sequentially connected in series;
the power tube charging current adjusting unit is used for judging whether the grid voltage of the high-side N-type MOS tube exceeds the voltage of the Miller platform, if so, the current of the grid of the high-side N-type MOS tube is amplified by the driving power tube charging unit, and otherwise, the grid of the high-side N-type MOS tube is charged by the driving power tube charging unit according to the preset current; the power tube charging current adjusting unit comprises a sixth switch tube, a seventh switch tube, an eighth switch tube, a second voltage-regulator tube, a ninth switch tube, a thirteenth switch tube, a fourteenth switch tube and a fifteenth switch tube, wherein the first ends of the second voltage-regulator tube, the sixth switch tube and the seventh switch tube are all connected with an external power supply, the first end of the eighth switch tube is connected with the second end of the seventh switch tube, the second end of the second voltage-regulator tube is connected with the second end of the sixth switch tube and the control end of the eighth switch tube, the control end of the sixth switch tube is connected with an external current source, the first end of the fourteenth switch tube is connected with the second end of the sixth switch tube, the control end of the fourteenth switch tube is connected between a first resistor and a second resistor, the second ends of the fourteenth switch tube and the fifteenth switch tube are connected with the first end of the thirteenth switch tube, the control end of the fifteenth switch tube is connected with the grid electrode of the high-side N-type MOS tube, the control ends of the thirteenth switch tube and the ninth switch tube are connected with the source electrode of the ninth switch tube;
the power tube charging unit is used for charging the grid electrode of the high-side N-type MOS tube;
and the power tube discharge unit is used for discharging the grid electrode of the high-side N-type MOS tube.
The circuit is further improved in that: the power tube charging unit comprises a fourth switch tube, a fifth switch tube, an eleventh switch tube, a twelfth switch tube and a tenth switch tube, wherein the first ends of the fourth switch tube and the fifth switch tube are connected with an external power supply, the second end of the fourth switch tube is connected with the control end of the seventh switch tube, the second end of the eighth switch tube, the first end of the eleventh switch tube, the control end of the fourth switch tube and the control end of the fifth switch tube, the second end of the fifth switch tube is connected with the first end of the twelfth switch tube and the high-side N-type power MOS grid electrode, the second end of the eleventh switch tube is connected with the first end of the fifteenth switch tube, the first end of the tenth switch tube and the second end of the twelfth switch tube, the control end of the eleventh switch tube is connected with the first end of the first voltage-regulator tube, the control end of the twelfth switch tube is connected with the grid electrode of the high-side N-type MOS tube, the second end of the tenth switch tube is connected with the source electrode of the high-side N-type MOS tube, and the control end of the tenth switch tube is connected with the second end of the tenth switch tube.
The circuit is further improved in that: the power tube discharging unit comprises a third resistor, the first end of the third resistor is connected with the grid electrode of the high-side N-type MOS tube, and the second end of the third resistor is connected with the source electrode of the high-side N-type MOS tube.
The circuit is further improved in that: the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch Guan Junwei are enhancement type P channel MOS tubes, and the ninth switch tube, the tenth switch tube, the eleventh switch tube, the twelfth switch tube, the thirteenth switch tube, the fourteenth switch tube and the fifteenth switch tube are enhancement type N channel MOS tubes.
A driving method of a high-side N-type power MOS is applied to the driving circuit, and comprises the following steps: charging a grid electrode of the high-side N-type MOS tube;
and judging whether the grid charging voltage of the high-side N-type MOS tube exceeds the voltage of the Miller platform, if so, increasing the current of the grid of the high-side N-type MOS tube by the driving power tube charging unit, and amplifying the current.
The method is further improved in that: the judging whether the grid charging voltage of the high-side N-type MOS tube exceeds the voltage of the Miller platform, if so, increasing the current of the driving power tube charging unit to the grid of the high-side N-type MOS tube, and the judging comprises the following steps:
and if the grid charging voltage of the high-side N-type MOS tube does not exceed the voltage of the Miller platform, driving the power tube charging unit to charge the grid of the high-side N-type MOS tube according to the preset current.
Due to the adoption of the technical scheme, the invention has the technical progress that:
the invention provides a driving circuit and a method of a high-side N-type MOS tube.A charging current adjusting unit of a power tube dynamically adjusts the grid current of the high-side N-type MOS tube in the starting process of the high-side N-type MOS tube, so that the high-side N-type MOS tube is charged with preset current when in a non-Miller platform stage, and when the Miller platform stage is finished, the charging current is increased to quickly increase the grid voltage of the high-side N-type MOS tube, thereby realizing that the high-side N-type MOS tube is driven by low resistance, reducing the switching loss and improving the anti-interference performance of the high-side NMOS.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts;
fig. 1 is a driving circuit of a high-side N-type power MOS provided in the prior art;
FIG. 2 illustrates the Miller plateau effect of the high-side NMOS turn-on phase provided by the prior art;
fig. 3 is a topology diagram of a driving circuit of a high-side N-type power MOS provided in the prior art;
FIG. 4 is a driving circuit topology diagram of a high-side N-type power MOS according to the present invention;
fig. 5 is a schematic diagram of the miller plateau effect of the driving circuit and method for the high-side N-type power MOS according to the present invention.
Detailed Description
In this application, the first ends of the first switch tube MP0, the second switch tube MP1, the third switch tube MP2, the fourth switch tube MP3, the fifth switch tube MP4, the sixth switch tube MP5, the seventh switch tube MP6 and the eighth switch tube MP7 are the source electrodes, the second ends are the drain electrodes, and the control ends are the gate electrodes.
The first ends of the ninth switching tube MN0, the tenth switching tube MN1, the eleventh switching tube MN2, the twelfth switching tube MN3, the thirteenth switching tube MN4, the fourteenth switching tube MN5 and the fifteenth switching tube MN6 are the drain electrodes, the second ends are the source electrodes, and the control ends are the gate electrodes.
The first end of the voltage-stabilizing tube is the input end, and the second end is the output end.
As shown in fig. 4, the present application provides a driving circuit and method for a high-side N-type power MOS, the circuit including: the power tube charging circuit comprises a current biasing unit 10, a floating voltage generating unit 20, a power tube charging current adjusting unit 30, a power tube charging unit 40 and a power tube discharging unit 50.
The current bias unit 10 generates bias currents required by the floating voltage generation unit 20 and the power tube charging current adjustment unit 30; the floating voltage generating unit 20 generates bias voltages required by the power tube charging unit 40 and the power tube charging current adjusting unit 30; the power tube charging current adjusting unit 30 determines whether the gate voltage of the high-side N-type MOS tube exceeds the voltage of the miller platform, if so, the power tube charging unit 40 is driven to amplify the current of the gate of the high-side N-type MOS tube, otherwise, the power tube charging unit is driven to charge the gate of the high-side N-type MOS tube according to a preset current; the power tube charging unit 40 charges the grid electrode of the high-side N-type MOS tube; the power tube discharge unit 50 discharges the grid electrode of the high-side N-type MOS tube.
The driving circuit method comprises the following steps: charging a grid electrode of the high-side N-type MOS tube; and judging whether the grid charging voltage of the high-side N-type MOS tube exceeds the voltage of the Miller platform, if so, driving the power tube charging unit 40 to amplify the current of the grid of the high-side N-type MOS tube, and otherwise, driving the power tube charging unit to charge the grid of the high-side N-type MOS tube according to a preset current.
Specifically, the circuit is provided with a power tube charging current adjusting unit 30, the gate current of the high-side NMOS is dynamically adjusted in the starting process of the high-side NMOS, so that the high-side NMOS is charged with a preset current when being in a non-miller platform stage, and when the miller platform stage is finished, the charging current is increased to rapidly increase the gate voltage of the high-side NMOS, so that the high-side NMOS is driven by low resistance, the switching loss is reduced, and the anti-interference performance of the high-side NMOS is improved.
In this embodiment, the current bias unit 10 includes a current mirror formed by a first switch tube MP0, a second switch tube MP1 and a third switch tube MP2, first ends of the first switch tube MP0, the second switch tube MP1 and the third switch tube MP2 are all connected to an external power supply, a second end of the first switch tube MP0 is connected to an external current source, and the external current source is all connected to control ends of the first switch tube MP0, the second switch tube MP1 and the third switch tube MP 2. The first switch tube MP0, the second switch tube MP1 and the third switch tube MP2 may be enhancement P-channel MOS tubes.
In practical application, the floating voltage generating unit 20 includes a first voltage regulator tube and a resistor voltage divider circuit connected in parallel with the first voltage regulator tube, a first end of the first voltage regulator tube is connected with a second end of the second switch tube MP1, and a second end of the first voltage regulator tube is connected with a source electrode of the high-side N-type MOS tube. The first voltage-stabilizing tube can be a first Zener tube D0, the resistance voltage-dividing circuit can be a resistance voltage-dividing circuit formed by connecting a plurality of resistors in series, or can be two resistors connected in series in sequence, and the voltage Vref of the low-voltage side of the resistance voltage divider is slightly larger than the voltage of M0 VGS of Mi Leping in power off.
In this embodiment, the power transistor charging current adjusting unit 30 includes a sixth switch transistor MP5, a seventh switch transistor MP6, an eighth switch transistor MP7, a second voltage regulator transistor, a ninth switch transistor MN0, a thirteenth switch transistor MN4, a fourteenth switch transistor MN5, and a fifteenth switch transistor MN6, where the sixth switch transistor MP5, the seventh switch transistor MP6, and the eighth switch transistor MP7 may be enhancement-type P-channel MOS transistors, the ninth switch transistor MN0, the thirteenth switch transistor MN4, the fourteenth switch transistor MN5, and the fifteenth switch transistor MN6 may be enhancement-type N-channel MOS transistors, and the second voltage regulator transistor may be a second zener diode D1.
The specific connection relationship is as follows: the first ends of a second voltage-regulator tube, a sixth switch tube MP5 and a seventh switch tube MP6 are connected with an external power supply, the first end of an eighth switch tube MP7 is connected with the second end of the seventh switch tube MP6, the second end of the second voltage-regulator tube is connected with the second end of the sixth switch tube MP5 and the control end of the eighth switch tube MP7, the control end of the sixth switch tube MP5 is connected with an external current source, the first end of a fourteenth switch tube MN5 is connected with the second end of the sixth switch tube MP5, the control end of the fourteenth switch tube MN5 is connected between a first resistor R1 and a second resistor R2, the second ends of the fourteenth switch tube MN5 and a fifteenth switch tube MN6 are connected with the first end of a thirteenth switch tube MN4, the control end of the fifteenth switch tube MN6 is connected with the grid electrode of a high-side N-type transistor, the second ends of the thirteenth switch tube MN4 and the ninth switch tube MN0 are connected with the source electrode of a high-side N-type MOS transistor, and the second end of the thirteenth switch tube MN0 is connected with the control end of the ninth switch tube MN0 and the control end of the ninth switch tube.
In this embodiment, the power transistor charging unit 40 includes a fourth switch transistor MP3, a fifth switch transistor MP4, an eleventh switch transistor MN2, a twelfth switch transistor MN3, and a tenth switch transistor MN1, the fourth switch transistor MP3, the fifth switch transistor MP4 may be enhancement-type P-channel MOS transistors, the eleventh switch transistor MN2, the twelfth switch transistor MN3, and the tenth switch transistor MN1 may be enhancement-type N-channel MOS transistors, specifically, the fourth switch transistor MP3, the first end of the fifth switch transistor MP4 are all connected to an external power supply, the second end of the fourth switch transistor MP3 is all connected to a control end of a seventh switch transistor MN6, the second end of an eighth switch transistor MP7, the first end of the eleventh switch transistor MN2, the control end of the fourth switch transistor MP3, the control end of the fifth switch transistor MP4, the second end of the fifth switch transistor MP4 is all connected to the first end of the twelfth switch transistor MN3, the first end of a high-side N power transistor MN2, the second end of the fifth switch transistor MP4 is connected to a gate of the twelfth switch transistor MN3, the gate of the tenth switch transistor MN2, the second end of the eleventh switch transistor MP2 is connected to the gate of the tenth switch transistor MN, the gate of the tenth switch transistor MN2, the fifth switch transistor MP2 is connected to the gate of the tenth switch transistor MN, the fifth switch transistor MN, the gate of the tenth switch transistor MN3, and the gate of the tenth switch transistor MN2, the gate of the tenth switch transistor MN2 are connected to the gate of the tenth switch transistor MN, and the tenth switch transistor MN 2.
In this embodiment, the power transistor discharge unit 50 includes a third resistor R0, a first end of the third resistor R0 is connected to the gate of the high-side N-type MOS transistor, and a second end of the third resistor R0 is connected to the source of the high-side N-type MOS transistor.
The embodiment provides a driving circuit and a method of a high-side N-type MOS transistor, which are used for adjusting a gate current of a high-side NMOS to realize low-resistance driving and improve the switching performance of the NMOS, and the operating principle of the driving circuit is as follows:
as shown in FIG. 4, two resistors R1 and R2 of the channel are connected in parallel on the side D0, and the resistance values of the two resistors are designed to make the generated divided voltage Vref slightly larger than the voltage of M0 VGS at Mi Leping station time. The MN5/MN6 input stage is used for detecting whether the grid voltage of the M0 exceeds the voltage of the Miller platform, and the MN4 is used for providing bias current of the input stage. When the grid voltage of M0 does not exceed the voltage of the Miller platform, the current of MN4 passes through the MN5 tube, the current of MP2 is designed to be smaller than that of MN4, the redundant current passes through the Zener tube D1, VGS of MP7 is 5V, MP7 is in a conducting state, and MP6 is connected with MP3 in parallel to form a current mirror with MP 4. When the gate voltage of M0 exceeds the voltage of the Miller stage, the current of MN4 passes through the MN6 tube, the MP7 tube is closed by the current of MP5, VGS is 0V, MP6 is removed from the current mirror, the proportion of the current mirror is increased, the current in MP4 is increased, and the current in MN2 is increased, so that the current in MP4 is further increased. The current equations for front and back MP4 are:
by reasonably setting the parameters in the formula, the design requirement of the slew rate of the Miller platform of M0 can be met, and after the Miller platform, the grid charging current of M0 is increased to optimize the switching performance of the NMOS.
The opening schematic of M0 is shown in FIG. 5. Briefly, when M0 is turned on, the bias current is turned on, at this time, the gate charging current of M0 is provided by MP4, and at this time, the current of MP4 is before IMP4, the formula is as above, when the VGS voltage of M0 is higher than the threshold voltage Vth, M0 is turned on, the SOURCE voltage rises, and at this time, the VGS voltage of M0 is in the miller plateau region; when the voltage of SOURCE rises to be close to the voltage of DRAIN, the VGS voltage of M0 finishes the Miller platform area and starts to rise; when the VGS voltage of M0 is higher than the predetermined voltage Vref, the current of MP4 is IMP4, and the VGS voltage of M0 is pulled up to 5V rapidly according to the above formula. It can be seen that the design requirement of the preset voltage Vref is that the VGS voltage higher than M0 is the voltage Vth + VOV in the miller plateau region, and the specific value is determined by the parameters of M0 and the load condition in the application.
The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solution of the present invention by those skilled in the art should fall within the protection scope defined by the claims of the present invention without departing from the spirit of the present invention.
Claims (6)
1. A driving circuit of a high-side N-type power MOS, comprising:
the current bias unit is used for generating bias current required by the floating voltage generation unit and the power tube charging current adjustment unit; the current bias unit comprises a current mirror formed by a first switching tube, a second switching tube and a third switching tube, wherein the first ends of the first switching tube, the second switching tube and the third switching tube are all connected with an external power supply, the second end of the first switching tube is connected with an external current source, and the external current source is all connected with the control ends of the first switching tube, the second switching tube and the third switching tube;
the floating voltage generating unit is used for generating bias voltages required by the power tube charging unit and the power tube charging current adjusting unit; the floating voltage generating unit comprises a first voltage-stabilizing tube and a resistance voltage-dividing circuit connected with the first voltage-stabilizing tube in parallel, wherein the first end of the first voltage-stabilizing tube is connected with the second end of the second switch tube, the second end of the first voltage-stabilizing tube is connected with the source electrode of the high-side N-type MOS tube, and the resistance voltage-dividing circuit comprises a first resistor and a second resistor which are sequentially connected in series;
the power tube charging current adjusting unit is used for judging whether the grid voltage of the high-side N-type MOS tube exceeds the voltage of the Miller platform, if so, the current of the grid of the high-side N-type MOS tube is amplified by the driving power tube charging unit, and otherwise, the grid of the high-side N-type MOS tube is charged by the driving power tube charging unit according to preset current; the power tube charging current adjusting unit comprises a sixth switch tube, a seventh switch tube, an eighth switch tube, a second voltage-regulator tube, a ninth switch tube, a thirteenth switch tube, a fourteenth switch tube and a fifteenth switch tube, wherein the first ends of the second voltage-regulator tube, the sixth switch tube and the seventh switch tube are all connected with an external power supply, the first end of the eighth switch tube is connected with the second end of the seventh switch tube, the second end of the second voltage-regulator tube is connected with the second end of the sixth switch tube and the control end of the eighth switch tube, the control end of the sixth switch tube is connected with an external current source, the first end of the fourteenth switch tube is connected with the second end of the sixth switch tube, the control end of the fourteenth switch tube is connected between the first resistor and the second resistor, the second ends of the fourteenth switch tube and the fifteenth switch tube are connected with the first end of the thirteenth switch tube, the control end of the fifteenth switch tube is connected with the grid electrode of the high-side N-type MOS switch tube, the third end of the thirteenth switch tube is connected with the high-side switch tube, the source electrode of the ninth switch tube is connected with the control end of the ninth switch tube, and the ninth switch tube;
the power tube charging unit is used for charging the grid electrode of the high-side N-type MOS tube;
and the power tube discharge unit is used for discharging the grid electrode of the high-side N-type MOS tube.
2. The driving circuit of a high-side N-type power MOS of claim 1, wherein the power transistor charging unit comprises a fourth switch transistor, a fifth switch transistor, and a tenth switch transistorAThe first ends of the fourth switching tube and the fifth switching tube are connected with an external power supply, the second end of the fourth switching tube is connected with the control end of the seventh switching tube, the second end of the eighth switching tube, the first end of the tenth switching tube, the control end of the fourth switching tube and the control end of the fifth switching tube, the second end of the fifth switching tube is connected with the first end of the twelfth switching tube and the high-side N-type power MOS grid electrode, the second end of the eleventh switching tube is connected with the first end of the fifteenth switching tube, the first end of the tenth switching tube, the second end of the eleventh switching tube and the control end of the tenth switching tubeThe second end of the twelfth switching tube is connected, the control end of the eleventh switching tube is connected with the first end of the first voltage-stabilizing tube, the control end of the twelfth switching tube is connected with the grid electrode of the high-side N-type MOS tube, the second end of the tenth switching tube is connected with the source electrode of the high-side N-type MOS tube, and the control end of the tenth switching tube is connected with the second end of the third switching tube.
3. The driving circuit of a high-side N-type power MOS of claim 1, wherein the power transistor discharge unit comprises a third resistor, a first terminal of the third resistor is connected to the gate of the high-side N-type power MOS, and a second terminal of the third resistor is connected to the source of the high-side N-type power MOS.
4. The driving circuit of a high-side N-type power MOS of claim 1, wherein the first switch transistor, the second switch transistor, and the third switch transistor are enhancement P-channel MOS transistors.
5. The driving circuit of a high-side N-type power MOS according to claim 1, wherein the sixth switch transistor, the seventh switch transistor, and the eighth switch Guan Junwei are enhancement type P-channel MOS transistors, and the ninth switch transistor, the thirteenth switch transistor, the fourteenth switch transistor, and the fifteenth switch transistor are enhancement type N-channel MOS transistors.
6. The driving circuit of a high-side N-type power MOS according to claim 2, wherein the fourth switching transistor and the fifth switching transistor are enhancement type P-channel MOS transistors, and the tenth switching transistor, the eleventh switching transistor and the twelfth switching transistor are enhancement type N-channel MOS transistors.
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| CN103916113A (en) * | 2012-12-31 | 2014-07-09 | 意法半导体研发(深圳)有限公司 | Drive circuit for driving power transistor |
| CN105226919A (en) * | 2015-11-04 | 2016-01-06 | 广州金升阳科技有限公司 | A kind of soft-sphere model method of power MOSFET and circuit |
| CN106849925A (en) * | 2016-12-25 | 2017-06-13 | 惠州市亿能电子有限公司 | Flash NMOS drive circuits |
| US10911045B1 (en) * | 2020-04-03 | 2021-02-02 | University Of Electronic Science And Technology Of China | Segmented direct gate drive circuit of a depletion mode GaN power device |
| CN113691108A (en) * | 2021-08-12 | 2021-11-23 | 广东省大湾区集成电路与系统应用研究院 | Drive circuit of low-side NMOS |
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| CN111555737B (en) * | 2020-05-21 | 2022-05-20 | 广东省大湾区集成电路与系统应用研究院 | Controllable voltage slew rate N type MOS high side drive circuit |
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| CN103916113A (en) * | 2012-12-31 | 2014-07-09 | 意法半导体研发(深圳)有限公司 | Drive circuit for driving power transistor |
| CN105226919A (en) * | 2015-11-04 | 2016-01-06 | 广州金升阳科技有限公司 | A kind of soft-sphere model method of power MOSFET and circuit |
| CN106849925A (en) * | 2016-12-25 | 2017-06-13 | 惠州市亿能电子有限公司 | Flash NMOS drive circuits |
| US10911045B1 (en) * | 2020-04-03 | 2021-02-02 | University Of Electronic Science And Technology Of China | Segmented direct gate drive circuit of a depletion mode GaN power device |
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