CN115189683A - Drive circuit for low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment - Google Patents

Drive circuit for low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment Download PDF

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Publication number
CN115189683A
CN115189683A CN202210734837.3A CN202210734837A CN115189683A CN 115189683 A CN115189683 A CN 115189683A CN 202210734837 A CN202210734837 A CN 202210734837A CN 115189683 A CN115189683 A CN 115189683A
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China
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low
side nmos
control signal
resistor
electrode
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Chinese (zh)
Inventor
王飞
郑鲲鲲
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Guangdong Hongyixin Automobile Electronic Technology Co ltd
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Guangdong Hongyixin Automobile Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

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Abstract

The invention provides a driving circuit for a low-side NMOS (N-channel metal oxide semiconductor) tube, which comprises: the low-side NMOS transistor comprises a control signal input end, a current bias module and a driving module, wherein the control signal input end is connected with the input end of the current bias module, the output end of the current bias module is connected with the input end of the driving module, and the output end of the driving module is connected with the grid electrode of the low-side NMOS transistor; wherein: the current bias module is used for generating bias current under the action of a control signal generated by the control signal input end; the drive module is used for: controlling the current charged by the grid electrode of the low-side NMOS tube under the action of the bias current, and controlling the discharge current of the low-side NMOS tube in the process of discharging the grid electrode of the low-side NMOS tube; so as to control the slew rate of the output voltage of the low-side NMOS tube.

Description

Drive circuit for low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment
Technical Field
The invention relates to the field of driving of power tubes, in particular to a driving circuit for a low-side NMOS tube and electronic equipment.
Background
In the prior art, an NMOS tube and a load can be connected in series between a power supply and a reference ground in sequence; the NMOS tube can be a low-side NMOS tube, the grid electrode of the NMOS tube is connected with the driving circuit, and the NMOS tube can be used for driving resistive and inductive loads.
In practical applications, in order to reduce the electromagnetic interference caused by the low-side NMOS, the slew rate of the switching point needs to be controlled.
In the prior art, an effective means for controlling the slew rate is lacked.
Disclosure of Invention
The invention provides a driving circuit of a low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment, which are used for effectively controlling the slew rate of a switching point.
According to a first aspect of the present invention, there is provided a driving circuit for a low side NMOS transistor, the driving circuit comprising: the low-side NMOS transistor comprises a control signal input end, a current bias module and a driving module, wherein the control signal input end is connected with the input end of the current bias module, the output end of the current bias module is connected with the input end of the driving module, and the output end of the driving module is connected with the grid electrode of the low-side NMOS transistor; wherein:
the current bias module is used for generating bias current under the action of a control signal generated by the control signal input end;
the drive module is used for: controlling the current charged by the grid electrode of the low-side NMOS tube under the action of the bias current, and controlling the discharge current of the low-side NMOS tube in the process of discharging the grid electrode of the low-side NMOS tube; so as to control the slew rate of the output voltage of the low-side NMOS tube.
Optionally, the current bias module includes a first resistor, a second resistor, a first triode, a second triode, a third triode, and a fourth triode; wherein:
the first end of the first resistor is connected with the control signal input end, the second end of the first resistor is connected with the collector electrode of the first triode, the emitter electrode of the first triode is connected with the collector electrode of the third triode and the base electrode of the fourth triode, and the base electrode of the first triode is connected with the base electrode of the second triode; the collector of the second triode is used as the output end of the current bias module and is used for outputting the bias current; the emitting electrode of the second triode is connected with the collecting electrode of the fourth triode and the base electrode of the third triode, the emitting electrode of the third triode is connected with the first end of the second resistor, the emitting electrode of the fourth triode is connected with the second end of the second resistor, and the first end of the second resistor is further connected with the source electrode of the low-side NMOS tube.
Optionally, the driving module includes a first PMOS transistor, a second PMOS transistor, a third resistor, and a fourth resistor; wherein:
the source electrode of the first PMOS tube is connected with the control signal input end, and the drain electrode of the first PMOS tube is connected with the output end of the current bias module; the source electrode of the second PMOS tube is connected with the control signal input end, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the first PMOS tube is further connected with the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the first end of the third resistor, the second end of the third resistor is connected with the grid electrode of the low-side NMOS tube, the first end of the fourth resistor is connected with the source electrode of the second PMOS tube, and the second end of the fourth resistor is connected with the second end of the second resistor.
Optionally, when the control signal generated by the control signal input terminal is a high level signal, the driving module is configured to: based on the bias current, the first PMOS tube and the second PMOS tube charge the grid electrode of the low-side NMOS tube, and then the low-side NMOS tube is conducted.
Optionally, when the control signal generated by the control signal input terminal is a high level signal, the driving module is further configured to:
based on the bias current, the fourth resistor charges the grid electrode of the low-side NMOS tube.
Optionally, when the control signal generated by the control signal input terminal is a low level signal, the driving module is configured to: and discharging the grid electrode of the low-side NMOS tube through a passage formed by the third resistor and the second PMOS tube.
Optionally, when the control signal generated by the control signal input terminal is a low-level signal, the driving module is further configured to: discharging the grid electrode of the low-side NMOS tube through the fourth resistor;
and when the grid electrode of the low-side NMOS tube discharges to the breakover voltage of the parasitic diode in the second PMOS tube, a passage formed by the third resistor and the second PMOS tube is cut off, and the grid electrode of the low-side NMOS tube continuously discharges to zero level through the fourth resistor.
Optionally, the first triode to the fourth triode are all NPN triodes.
Optionally, the control signal input end is further connected to an external output control signal module, and the external output control signal module outputs a control signal to the control signal input end.
Optionally, the drain of the low-side NMOS transistor is connected to a power supply through a load, and the source of the low-side NMOS transistor is grounded.
According to a second aspect of the present invention, there is provided an electronic device, comprising the driving circuit for the low-side NMOS transistor of the first aspect.
According to the drive circuit and the electronic equipment for the low-side NMOS tube, under the action of the control signal generated by the control signal input end, the charging/discharging current of the low-side NMOS tube is controlled through the current bias module and the drive module, so that the slew rate of the output voltage of the low-side NMOS tube is controlled, and the electromagnetic interference caused by the low-side NMOS tube is reduced.
In a preferred embodiment, the discharge of the low-side NMOS transistor is limited by the third resistor and the fourth resistor, and when the voltage drops to the on-voltage of the parasitic diode in the second PMOS transistor, the path formed by the third resistor and the second PMOS transistor is cut off, so that the gate of the low-side NMOS transistor can continue to discharge to a zero level through the fourth resistor.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a driving circuit for a low-side NMOS transistor according to an embodiment of the present invention;
FIG. 2 is a diagram of Miller plateau during the turn-on phase of a low-side NMOS;
FIG. 3 is a first schematic diagram illustrating a driving circuit for a low side NMOS transistor according to an embodiment of the present invention;
FIG. 4 is a second schematic diagram illustrating a driving circuit for a low side NMOS transistor according to an embodiment of the present invention;
description of reference numerals:
1-a control signal input;
2-a current bias module;
201-a first resistance;
202-a first triode;
203-a second triode;
204-a third triode;
205-a fourth transistor;
206-a second resistance;
3-a drive module;
301-a first PMOS transistor;
302-a second PMOS transistor;
303-third resistance;
304-a fourth resistance;
4-low side NMOS transistor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Before the present application is proposed, the applicant has made a sufficient study on a driving circuit for a low side NMOS transistor, and based on the study, has proposed a driving circuit structure for a low side NMOS transistor shown in fig. 1, and the driving circuit structure for a low side NMOS transistor shown in fig. 1 includes: the control signal input end (namely IN), the resistor (namely R0) and the low-side NMOS tube (namely M0).
The control signal input end (i.e., IN) is connected to a first end of the resistor (i.e., R0), a second end of the resistor (i.e., R0) is connected to a gate of the low-side NMOS transistor (i.e., M0), a drain of the low-side NMOS transistor (i.e., M0) is connected to a power supply through a load, and a source of the low-side NMOS transistor (i.e., M0) is grounded.
Specifically, when the control signal generated by the control signal input terminal is a high level signal, the low side NMOS transistor (i.e., M0) is turned on, and when the control signal generated by the control signal input terminal is a low level signal, the low side NMOS transistor (i.e., M0) is turned off, and then the current is limited to charge/discharge the low side NMOS transistor (i.e., M0) by a value of a resistor (i.e., R0), wherein a charge/discharge current calculation formula is as follows:
Icharge＝(VIN-VGS)/R0；
Idischarge＝VGS/R0；
and the applicant researches the turn-on characteristic and the voltage swing of the low-side NMOS tube by combiningSpecifically, referring to fig. 2, fig. 2 is a diagram showing the miller plateau effect at the turn-on stage of the low-side NMOS, and the voltage V of the drain is known DS The change occurs in a plateau phase where the gate voltage is higher than the threshold voltage Vth, i.e., the t3 phase shown in fig. 2.
Wherein Icharge is a charging current, idischarge is a discharging current, VIN is a voltage of the control signal input terminal, VGS is a level of the low-side NMOS transistor (i.e., M0) at Mi Leping, and R0 is a resistance value; generally, VIN and VGS are fixed values, and only the value of R0 can be adjusted, and when a specific charge/discharge current is required, the value of R0 generally cannot meet the requirement.
In view of the above, the applicant formally utilized the miller plateau effect in the low-side NMOS turn-on stage, specifically, in the miller plateau stage, I DS And V GS (I GS ) Is relatively stable, and V DS Under the condition of rapid change, a novel driving circuit structure for a low-side NMOS tube is provided, which can control the charging current of the grid electrode of the low-side NMOS tube and the discharging current of the low-side NMOS tube in the process of discharging the grid electrode of the low-side NMOS tube; and further controlling the slew rate of the output voltage of the low-side NMOS tube.
The scheme of the invention is specifically explained as follows:
referring to fig. 3, the present invention provides a driving circuit for a low side NMOS transistor, the driving circuit comprising: the low-side NMOS transistor comprises a control signal input end 1, a current bias module 2 and a drive module 3, wherein the control signal input end 1 is connected with the input end of the current bias module 2, the output end of the current bias module 2 is connected with the input end of the drive module 3, and the output end of the drive module 3 is connected with the grid electrode of the low-side NMOS transistor 4; wherein:
the current bias module 2 is used for generating bias current under the action of a control signal generated by the control signal input end 1;
the drive module 3 is configured to: controlling the current charged by the grid electrode of the low-side NMOS tube 4 under the action of the bias current, and controlling the discharge current of the low-side NMOS tube 4 in the process of discharging the grid electrode of the low-side NMOS tube; so as to control the slew rate of the output voltage of the low-side NMOS tube 4.
The slew rate is the conversion rate of the output voltage, and the larger the slew rate is, the larger the working current is.
In a preferred embodiment, the control signal input terminal 1 is further connected to an external output control signal module, and the external output control signal module outputs a control signal to the control signal input terminal 1.
The drain electrode of the low-side NMOS tube 4 is connected with a power supply through a load, and the source electrode of the low-side NMOS tube 4 is grounded; further, the low-side NMOS transistor 4 may be a low-side NMOS transistor that needs to be driven, and the low-side NMOS transistor is used for driving resistive and inductive loads. In the prior art, a driving circuit can only adjust charging/discharging current according to one resistor, but the value of one resistor cannot meet specific current requirements generally; therefore, the electromagnetic interference caused by the low-side NMOS transistor cannot be avoided.
In the invention, under the action of the control signal generated by the control signal input end 1, the current bias module 2 and the driving module 3 can control the charging/discharging current of the low-side NMOS tube 4 so as to meet the requirement of a specific current value, further control the slew rate of the output voltage of the low-side NMOS tube 4 and reduce the electromagnetic interference caused by the low-side NMOS tube.
Referring to fig. 4, the current bias module 2 includes a first resistor 201, a second resistor 206, a first transistor 202, a second transistor 203, a third transistor 204, and a fourth transistor 205; wherein:
a first end of the first resistor 201 is connected to the control signal input terminal 1, a second end of the first resistor 201 is connected to a collector of the first triode 202, an emitter of the first triode 202 is connected to a collector of a third triode 204 and a base of the fourth triode 205, and a base of the first triode 202 is connected to a base of the second triode 203; the collector of the second triode 203 is used as the output end of the current bias module 2 and is used for outputting the bias current; the emitter of the second triode 203 is connected to the collector of the fourth triode 205 and the base of the third triode 204, the emitter of the third triode 204 is connected to the first end of the second resistor 206, the emitter of the fourth triode 205 is connected to the second end of the second resistor 206, and the first end of the second resistor 206 is further connected to the source of the low-side NMOS transistor 4.
As a preferred embodiment, the first to fourth transistors are NPN transistors. Of course, the invention is not limited thereto, and other types of transistors, such as PNP transistor, etc., are within the scope of the invention.
With regard to the driving module 3, please continue to refer to fig. 4, the driving module 3 includes a first PMOS transistor 301 (i.e., MP 1), a second PMOS transistor 302 (i.e., MP 2), a third resistor 303, and a fourth resistor 304; the first PMOS transistor 301 and the second PMOS transistor 302 form a current mirror: (ii) a
The source electrode of the first PMOS transistor 301 and the source electrode of the second PMOS transistor 302 are both connected to the control signal input terminal 1, and the drain electrode of the first PMOS transistor 301 is connected to the output terminal of the current bias module 2; the gate of the first PMOS transistor 301 is connected to the gate of the second PMOS transistor 302, the gate of the first PMOS transistor 301 is further connected to the drain of the first PMOS transistor 301, the drain of the second PMOS transistor 302 is connected to the first end of the third resistor 303, the second end of the third resistor 303 is connected to the gate of the low-side NMOS transistor 4, the first end of the fourth resistor 304 is connected to the source of the second PMOS transistor 302, and the second end of the fourth resistor 304 is connected to the second end of the second resistor 206.
Wherein, when the control signal generated by the control signal input terminal 1 is a high level signal, the driving module 3 is configured to: based on the bias current, the gate of the low-side NMOS transistor 4 is charged through the branch formed by the first PMOS transistor 301, the second PMOS transistor 302, and the third resistor 303, so as to turn on the low-side NMOS transistor 4.
In addition, when the control signal generated by the control signal input terminal 1 is a high level signal, the driving module 3 is further configured to:
based on the bias current, the fourth resistor 304 charges the gate of the low-side NMOS transistor 4.
In a specific embodiment, when the level output by the control signal input terminal 1 is from low to high, the bias current generated by the current bias module 2 charges the gate of the low-side NMOS transistor 4 through the current mirror unit (i.e., the first PMOS transistor 301 (i.e., MP 1), the second PMOS transistor 302 (i.e., MP 2)) and the third resistor 303, and the parallel fourth resistor 304 also charges the gate of the low-side NMOS transistor 4. In practice, the current can be controlled at Mi Leping when the low-side NMOS transistor 4 is turned on by adjusting the circuit parameters of the current bias module 2 and the driving module 3, so as to meet the slew rate design requirement of the drain of the low-side NMOS transistor 4.
In the embodiment shown in fig. 4, the gate charge current value of the low-side NMOS is calculated as follows:
Icharge＝IQ1(W/L_MP2)/(W/L_MP1)+(VIN-VGS)/R4；
IQ1 is a bias current generated by the current bias module 2, W/L _ MP2 is a width-to-length ratio of a channel of the second PMOS transistor 302, (W/L _ MP 1) is a width-to-length ratio of a channel of the first PMOS transistor 301, VIN is a voltage of a control signal input terminal 1, VGS is a level of the low-side NMOS transistor 4 when the transistor is Mi Leping, and R4 is a resistance value of the fourth resistor 304.
In actual operation, the value of R4 may be set to be large enough so that:
IQ1(W/L_MP2)/(W/L_MP1)>>(VIN-VGS)/R4；
the gate charge current value Icharge of the low-side NMOS can be simplified as:
Icharge＝IQ1(W/L_MP2)/(W/L_MP1)。
in this case, since IQ1 is independent of VIN voltage, icharge is also independent of VIN voltage. Since Icharge is related to IQ1, W/L _ MP2 and W/L _ MP1, icharge can satisfy the slew rate of the specific voltage of the low-side NMOS during the charging process by setting the parameters of the corresponding components. The slew rate of the low-side NMOS transistor in the charging process is controllable.
Wherein, in order to control the discharge current of the low side NMOS4 transistor, when the control signal generated by the control signal input terminal 1 is a low level signal, the driving module 3 is configured to: the gate of the low-side NMOS transistor 4 is discharged through a path formed by the third resistor 303 and the second PMOS transistor 302.
In addition, when the control signal generated by the control signal input terminal 1 is a low level signal, the driving module 3 is further configured to: the gate of the low-side NMOS transistor 4 is discharged through the fourth resistor 304.
In the embodiment shown in fig. 4, the discharge current value of the gate of the low-side NMOS is calculated as follows:
Idischarge＝(VGATE-VIN-VBE)/R3+(VGATE-VIN)/R4；
VGATE is a gate voltage of the low-side NMOS transistor 4, VIN is a voltage of the control signal input terminal 1, VBE is a voltage drop of a parasitic diode in the second PMOS transistor 302, R3 is a resistance value of the third resistor 303, and R4 is a resistance value of the fourth resistor 304.
In actual operation, the value of R4 may be set to be large enough so that:
(VGATE-VIN-VBE)/R3 > > (VGATE-VIN)/R4, the calculation formula of the discharge current value of the gate of the low side NMOS can be simplified as follows:
Idischarge＝(VGATE-VIN-VBE)/R3。
in this case, idischarge can satisfy a specific voltage slew rate of the low-side NMOS transistor during the discharge process by setting the resistance R3 of the third resistor 303 to a large value. The slew rate of the low-side NMOS tube in the discharge process is controllable.
When the gate of the low-side NMOS transistor 4 discharges to the on-state voltage of the parasitic diode in the second PMOS transistor 302, the path formed by the third resistor 303 and the second PMOS transistor 302 is cut off, and the gate of the low-side NMOS transistor 4 continues to discharge to the zero level through the fourth resistor 304.
Therefore, the driving circuit of the low-side NMOS transistor provided by the embodiment of the invention can meet the specific charging current value and the specific discharging current value of the gate of the low-side NMOS transistor through the design of circuit parameters, so as to meet the slew rate requirement of the voltage of the low-side NMOS transistor, and can achieve complete discharge in the discharging process.
The invention also provides electronic equipment comprising the drive circuit for the low-side NMOS tube.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (11)

1. A driving circuit for a low side NMOS transistor, the driving circuit comprising: the low-side NMOS transistor comprises a control signal input end, a current bias module and a driving module, wherein the control signal input end is connected with the input end of the current bias module, the output end of the current bias module is connected with the input end of the driving module, and the output end of the driving module is connected with the grid electrode of the low-side NMOS transistor; wherein:
the current bias module is used for generating bias current under the action of a control signal generated by the control signal input end;
the drive module is used for: controlling the current charged by the grid electrode of the low-side NMOS tube under the action of the bias current, and controlling the discharge current of the low-side NMOS tube in the process of discharging the grid electrode of the low-side NMOS tube; so as to control the slew rate of the output voltage of the low-side NMOS tube.
2. The driving circuit for a low side NMOS transistor according to claim 1, wherein said current bias module comprises a first resistor, a second resistor, a first transistor, a second transistor, a third transistor and a fourth transistor; wherein:
the first end of the first resistor is connected with the control signal input end, the second end of the first resistor is connected with the collector electrode of the first triode, the emitter electrode of the first triode is connected with the collector electrode of the third triode and the base electrode of the fourth triode, and the base electrode of the first triode is connected with the base electrode of the second triode; a collector of the second triode is used as an output end of the current bias module and is used for outputting the bias current; the emitting electrode of the second triode is connected with the collecting electrode of the fourth triode and the base electrode of the third triode, the emitting electrode of the third triode is connected with the first end of the second resistor, the emitting electrode of the fourth triode is connected with the second end of the second resistor, and the first end of the second resistor is further connected with the source electrode of the low-side NMOS tube.
3. The driving circuit for a low side NMOS transistor according to claim 2, wherein said driving module comprises a first PMOS transistor, a second PMOS transistor, a third resistor, and a fourth resistor; wherein:
the source electrode of the first PMOS tube is connected with the control signal input end, and the drain electrode of the first PMOS tube is connected with the output end of the current bias module; the source electrode of the second PMOS tube is connected with the control signal input end, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the first PMOS tube is further connected with the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the first end of the third resistor, the second end of the third resistor is connected with the grid electrode of the low-side NMOS tube, the first end of the fourth resistor is connected with the source electrode of the second PMOS tube, and the second end of the fourth resistor is connected with the second end of the second resistor.
4. The driving circuit for a low-side NMOS transistor according to claim 3, wherein when the control signal generated at the control signal input terminal is a high level signal, the driving module is configured to: based on the bias current, the first PMOS tube and the second PMOS tube charge the grid electrode of the low-side NMOS tube, and then the low-side NMOS tube is conducted.
5. The driving circuit for a low-side NMOS transistor according to claim 4, wherein when the control signal generated at the control signal input terminal is a high level signal, the driving module is further configured to:
based on the bias current, the fourth resistor charges the grid electrode of the low-side NMOS tube.
6. The driving circuit for a low side NMOS transistor according to claim 3, wherein when the control signal generated at the control signal input terminal is a low level signal, the driving module is configured to: and discharging the grid electrode of the low-side NMOS tube through a passage formed by the third resistor and the second PMOS tube.
7. The driving circuit for a low side NMOS transistor according to claim 6, wherein when the control signal generated at the control signal input terminal is a low level signal, the driving module is further configured to: discharging the grid electrode of the low-side NMOS tube through the fourth resistor;
and when the grid electrode of the low-side NMOS tube discharges to the breakover voltage of the parasitic diode in the second PMOS tube, the passage formed by the third resistor and the second PMOS tube is cut off, and the grid electrode of the low-side NMOS tube continuously discharges to zero level through the fourth resistor.
8. The driving circuit for a low side NMOS transistor according to claim 7, wherein said first to fourth transistors are NPN transistors.
9. The driving circuit for the low side NMOS transistor according to claim 8, wherein said control signal input terminal is further connected to an external output control signal module, said external output control signal module outputting a control signal to said control signal input terminal.
10. The driving circuit for the low side NMOS transistor according to any one of claims 1-9, wherein the drain of said low side NMOS transistor is connected to the power supply via the load, and the source of said low side NMOS transistor is grounded.
11. An electronic device comprising the driving circuit for the low-side NMOS transistor according to any one of claims 1 to 10.
CN202210734837.3A 2022-06-14 2022-06-14 Drive circuit for low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment Withdrawn CN115189683A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115800978A (en) * 2022-11-07 2023-03-14 广东鸿翼芯汽车电子科技有限公司 Drive circuit for low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115800978A (en) * 2022-11-07 2023-03-14 广东鸿翼芯汽车电子科技有限公司 Drive circuit for low-side NMOS (N-channel metal oxide semiconductor) tube and electronic equipment

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Application publication date: 20221014

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