CN216959308U

CN216959308U - Current limiting circuit

Info

Publication number: CN216959308U
Application number: CN202220562540.9U
Authority: CN
Inventors: 胡志武
Original assignee: Zf Electric Drive Technology Shenyang Co ltd
Current assignee: Zf Electric Drive Technology Shenyang Co ltd
Priority date: 2022-03-15
Filing date: 2022-03-15
Publication date: 2022-07-12
Anticipated expiration: 2032-03-15

Abstract

The utility model discloses a current limiting circuit which comprises a P-type field effect transistor (Q1), a triode (Q3) and a current sampling resistor (R1), wherein one end of the current sampling resistor (R1) is connected to an input end, the other end of the current sampling resistor (R1) is connected to the source electrode of the P-type field effect transistor (Q1), the drain electrode of the P-type field effect transistor (Q1) is connected to an output end, the grid electrode of the P-type field effect transistor (Q1) is grounded through a first resistor (R6), the emitter electrode of the triode (Q3) is connected to the input end, the collector electrode of the triode (Q3) is grounded, and the base electrode of the triode (Q3) is connected to the source electrode of the P-type field effect transistor (Q1). The utility model utilizes the P-type field effect transistor as an overcurrent trigger source, and the P-type field effect transistor works in a variable resistance region by adjusting the driving voltage of the P-type field effect transistor, so that the output impedance of the power supply is dynamically adjusted, and the current output is stabilized.

Description

Current limiting circuit

Technical Field

The present invention relates to a current limiting circuit, and more particularly, to a current limiting circuit for adjusting the output series impedance of a power supply.

Background

Damage to the power supply can occur when the output of the power supply exceeds the rated load or is short circuited. For this phenomenon, current-limiting protection design is performed on the product when designing the power supply. One current limiting protection circuit includes two transistors, and the current limiting is achieved by an interlock circuit formed by the two transistors. The current-limiting protection circuit is simple in structure, but cannot be recovered in a current-limiting protection state, the driving capability is small, and if the circuit is required to be recovered, an extra resistor is required. Another current-limiting protection circuit commonly used in the related art uses an integrated operational amplifier to detect an output current, and adjusts the output current through a feedback loop, so as to achieve the purpose of current limiting and constant current. But this solution is costly.

SUMMERY OF THE UTILITY MODEL

The utility model provides a current limiting circuit with both adjustment precision and cost, aiming at solving the defects that the interlocking circuit in the prior art has poor driving capability, the circuit with high adjustment precision has high cost and is difficult to be suitable for low-cost products.

The purpose of the utility model is realized by the following technical scheme:

a current limiting circuit is characterized by comprising a P-type field effect transistor, a triode and a current sampling resistor, wherein one end of the current sampling resistor is connected to an input end, the other end of the current sampling resistor is connected to a source electrode of the P-type field effect transistor, a drain electrode of the P-type field effect transistor is connected to an output end, a grid electrode of the P-type field effect transistor is grounded through a first resistor, an emitting electrode of the triode is connected to the input end, a collector electrode of the triode is grounded, and a base electrode of the triode is connected to the source electrode of the P-type field effect transistor.

Preferably, the current limiting circuit further includes a first voltage dividing resistor and a second voltage dividing resistor connected in series with each other between the input terminal and the ground, and a first capacitor, one end of the first capacitor is connected to the input terminal, and the other end of the first capacitor is grounded through the second voltage dividing resistor.

Preferably, the current limiting circuit further comprises a zener diode, an anode of the zener diode is connected to the collector of the triode, and a cathode of the zener diode is connected to the source of the P-type field effect transistor.

Preferably, the current limiting circuit further comprises a snubber circuit connected between the source of the P-type fet and the drain of the P-type fet for reducing drain-source spike voltage.

Preferably, the absorption circuit includes a second resistor and a second capacitor connected in series with each other.

Preferably, the first resistor is used for limiting the gate current of the PFET and suppressing the noise coupled by the grounding end.

Preferably, the current sampling resistor is a thick film resistor with the accuracy of 0.1% -1%. The accuracy here refers to the accuracy of the resistor, and the higher the accuracy, the higher the current sampling accuracy, and according to U ═ I × R, the higher the constant current accuracy achieved by the high-accuracy resistor.

Preferably, the current limiting circuit further comprises a third capacitor connected in parallel with the current sampling resistor to further improve the immunity to interference.

Preferably, the third capacitor is a ceramic capacitor.

The utility model has the technical effects that:

1. the P-type field effect transistor is used as an overcurrent trigger source, and the P-type field effect transistor works in a variable resistance region by adjusting the driving voltage of the P-type field effect transistor, so that the output impedance of the power supply is dynamically adjusted, and the current output is stabilized.

2. The slow start of the switching action of the P-type field effect transistor is realized through the combination of the divider resistor and the capacitor.

Drawings

FIG. 1 is a schematic diagram of a current limiting circuit according to an embodiment of the utility model;

FIG. 2 is a schematic diagram illustrating a current direction of a slow start of a current limiting circuit according to an embodiment of the utility model;

FIG. 3 is a schematic diagram illustrating the direction of current flow in the transistor of the current limiting circuit according to an embodiment of the present invention;

fig. 4 is a schematic current flow diagram illustrating the Vgs capacitance discharge of a pfet in accordance with an embodiment of the present invention;

fig. 5 is a schematic diagram of a current limiting circuit according to another embodiment of the utility model.

Detailed Description

The following further describes embodiments of the present invention in conjunction with the accompanying drawings.

The current limiting circuit according to an embodiment of the present invention is described in detail below with reference to fig. 1 to 4. The current limiting circuit comprises a P-type field effect transistor Q1, a triode (P-type transistor) Q3 and a current sampling resistor R1, wherein one end of the current sampling resistor R1 is connected to an input end Vin, the other end of the current sampling resistor R1 is connected to a source electrode of the P-type field effect transistor Q1, a drain electrode of the P-type field effect transistor Q1 is connected to an output end Vout, and a grid electrode of the P-type field effect transistor Q1 is grounded. In addition, the emitter of the transistor Q3 is connected to the input terminal Vin, the collector of the transistor Q3 is pulled to ground through the first resistor R6, wherein the first resistor R6 is used for limiting the current of the gate of the pfet Q1 and suppressing the noise coupled by the ground terminal, and the base of the transistor Q3 is connected to the source of the pfet Q1. Wherein the switching of transistor Q3 is controlled by current sampling resistor R1.

Referring mainly to fig. 3-4, the current limiting circuit operates as follows: when the output current is less than the current limit point, e.g., 100mA, transistor Q3 is disabled and the magnitude of the output current is determined by the load connected to the output terminal Vout. When the load is heavy and the output current exceeds a current limiting point (for example 100mA), the voltage drop of the current sampling resistor R1 exceeds the driving threshold of the triode Q3, so that the triode Q3 is conducted, and the current can be divided into two paths, wherein one path is from the emitter to the collector of the triode Q3; the other path is from the emitter of a triode Q3 to the base, and the path creates conditions for the Vgs discharge of a P-type field effect transistor Q1. When the load current drops below 100mA, the voltage drop across the current sampling resistor R1 falls below the driving threshold of transistor Q3, causing transistor Q3 to turn off.

Specifically, when the transistor Q3 is turned on, the voltage stored in the Vgs (gate-source) capacitor of the pfet Q1 is discharged through the transistor Q3, and as the Vgs voltage decreases, the resistance between the electrodes (drain-source) of the pfet Q1DS increases. According to the characteristics of the pfet, the magnitude of Vgs voltage is related to the magnitude of DS resistance, and when Vgs drops to a certain value, that is, when the DS resistance increases to a certain value, the impedance of the whole circuit remains unchanged, that is, although the load impedance decreases, the DS resistance of the pfet Q1 increases, thereby limiting and maintaining the load current constant.

Besides, the current limiting circuit further includes a first voltage dividing resistor R3 and a second voltage dividing resistor R4 connected in series with each other between the input terminal Vin and the ground, and a first capacitor C1, wherein one end of the first capacitor C1 is connected to the input terminal Vin, and the other end of the first capacitor C1 is connected to the ground through the second voltage dividing resistor R4. The Vgs voltage of the pfet Q1 is fixed by a voltage dividing resistor, and is, for example, 12V. Referring mainly to fig. 2, the first capacitor C1 is a slow start capacitor, when the current limiting circuit is just powered on, since the voltage across the first capacitor C1 is zero, the voltage across the second voltage-dividing resistor R4 is the highest, and as the first capacitor C1 is charged, the charging current is smaller and smaller, the voltage across the second voltage-dividing resistor R4 gradually decreases, and the voltage across the first capacitor C1 is also larger and larger, thereby ensuring that Vgs of the P-type fet Q1 is slowly increased, and thus realizing the slow start of the switching operation of the P-type fet Q1.

The current limiting circuit further comprises a voltage stabilizing diode D3, wherein the anode of the voltage stabilizing diode D3 is connected to the collector of the triode Q3, and the cathode of the voltage stabilizing diode D3 is connected to the source of the P-type field effect transistor Q1. The zener diode prevents the Vgs of the pfet Q1 from exceeding the limit while the input voltage fluctuates.

The current limiting circuit further comprises a snubber circuit connected between the source of the PFET Q1 and the drain of the PFET Q1 for reducing drain-source spike voltage at pulse start-up. The absorption circuit comprises a second resistor R2 and a second capacitor C2 which are connected in series with each other.

In some preferred embodiments (see fig. 5), the current sampling resistor R1 is a thick film resistor with an accuracy of up to 0.1%. In order to improve the interference resistance, a ceramic capacitor C3 can be connected in parallel with the current sampling resistor.

The current limiting circuit of the utility model utilizes the P-type field effect transistor as an overcurrent trigger source, and the P-type field effect transistor works in a variable resistance region by adjusting the driving voltage of the transistor, thereby dynamically adjusting the output impedance of the power supply. The technical scheme of the utility model can realize constant current with certain precision requirement at lower cost.

While specific embodiments of the utility model have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the utility model is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the utility model, and these changes and modifications are within the scope of the utility model.

Claims

1. A current limiting circuit is characterized by comprising a P-type field effect transistor (Q1), a triode (Q3) and a current sampling resistor (R1), wherein one end of the current sampling resistor (R1) is connected to an input end, the other end of the current sampling resistor (R1) is connected to the source electrode of the P-type field effect transistor (Q1), the drain electrode of the P-type field effect transistor (Q1) is connected to an output end, the grid electrode of the P-type field effect transistor (Q1) is grounded through a first resistor (R6),

the emitter of the triode (Q3) is connected to the input end, the collector of the triode (Q3) is grounded, and the base of the triode (Q3) is connected to the source of the P-type field effect transistor (Q1).

2. The current-limiting circuit of claim 1, further comprising a first voltage-dividing resistor (R3) and a second voltage-dividing resistor (R4) connected in series with each other between the input terminal and the ground, and a first capacitor (C1), wherein one end of the first capacitor (C1) is connected to the input terminal, and the other end of the first capacitor (C1) is connected to the ground through the second voltage-dividing resistor (R4).

3. The current-limiting circuit of claim 1, further comprising a zener diode (D3), wherein an anode of the zener diode (D3) is connected to the collector of the transistor (Q3), and a cathode of the zener diode (D3) is connected to the source of the pfet (Q1).

4. The current-limiting circuit of any of claims 1-3, further comprising a snubber circuit connected between the source of the PFET (Q1) and the drain of the PFET (Q1) for reducing drain-to-source spike voltage.

5. The current-limiting circuit of claim 4, wherein the snubber circuit comprises a second resistor (R2) and a second capacitor (C2) connected in series with each other.

6. A current limiting circuit as claimed in any one of claims 1 to 3 wherein the first resistor (R6) is used for gate current limiting of the pfet (Q1) and for noise rejection by ground coupling.

7. A current limiting circuit as claimed in any one of claims 1 to 3 wherein the current sampling resistor (R1) is a thick film resistor with an accuracy of 0.1% to 1%.

8. A current limiting circuit according to any of claims 1-3, characterized in that the current limiting circuit further comprises a third capacitor (C3) in parallel with the current sampling resistor.

9. The current-limiting circuit of claim 8, wherein the third capacitor is a ceramic capacitor.